Documente Academic
Documente Profesional
Documente Cultură
Created by
Jerry Kaczynski
Agenda
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Introduction
Basic Ideas
UVM
Conclusion
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What Is UVM?
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System-Level Designs.
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class Base_Counter;
int contents;
function new();
contents = -7;
endfunction
task clear();
contents = 0;
endtask
task count();
contents += 1;
endtask
function int show();
return contents;
endfunction
endclass
property
methods
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endpackage
TLM Ports
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connected to it.
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(put)
producer
FIFO
subscriber2
(get)
consumer
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11
Module
Bus
monitor
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slave
clk
reset
enable
din[]
dout[]
ready
my_ifc
Bus
Module
SV Interface is a module-level
container for signal and port
direction data.
It can also contain behavioral
code (tasks, assertions, etc.)
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Virtual Interfaces
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Monitors
Drivers
...
Scoreboards
System Bus
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Control Logic
15
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16
Create environments/tests
Create top-level module
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18
19
reset
enable
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Interface Modport
Clock
Generator
System
Reset
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Top Level
Module
reset
enable
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Interface Modport
Clock
Generator
System
Reset
21
Top Level
Module
Packet
reset
enable
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Interface Modport
Clock
Generator
System
Reset
22
Top Level
Module
Sequence
Packet
Packet
Packet
reset
enable
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Interface Modport
Clock
Generator
System
Reset
23
Top Level
Module
Sequencer
Sequence
Packet
Packet
Packet
Monitor
Driver
Environment
reset
enable
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Interface Modport
Clock
Generator
System
Reset
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Top Level
Module
Sequencer
Sequence
Packet
Packet
Packet
Monitor
Driver
Virtual Interface
Virtual Interface
Environment
reset
enable
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Interface Modport
Clock
Generator
System
Reset
25
Top Level
Module
Sequencer
Sequence
Packet
Packet
Packet
Monitor
Driver
Virtual Interface
Virtual Interface
Environment
reset
enable
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Interface Modport
Clock
Generator
System
Reset
TEST:
run_test()
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Top Level
Module
Agent
Sequencer
Sequence
Packet
Packet
Packet
Monitor
Driver
Virtual Interface
Virtual Interface
Environment
reset
enable
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Interface Modport
Clock
Generator
System
Reset
TEST:
run_test()
Monitor+Sequence+Driver=Agent
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Top Level
Module
Scoreboard
Agent
Sequencer
Sequence
Packet
Packet
Packet
Monitor
Driver
Virtual Interface
Virtual Interface
Environment
reset
enable
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Interface Modport
Clock
Generator
System
Reset
TEST:
run_test()
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Top Level
Module
Scoreboard
Master
Agent
Sequencer
Sequence
Packet
Packet
Packet
Environment
Monitor
Driver
VI
VI
reset
enable
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Interface Modport
Clock
Generator
System
Reset
TEST:
run_test()
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Top Level
Module
Scoreboard
Slave
Agent Master
Agent
Sequencer
Sequencer
Sequence
Packet
Packet
Packet
Monitor
VI
Environment
Environment
TestTest
Driver
Monitor
VI
VI
Driver
VI
reset
enable
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Interface Modport
Clock
Generator
System
Reset
TEST:
run_test()
UVM Factory
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UVM Phases
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build
connect
end_of_elaboration
start_of_simulation
run
extract
check
report
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endclass
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Building Sequence
class my_seq extends uvm_sequence #(packet);
integer n_packets = 8;
`uvm_object_utils_begin(my_seq)
`uvm_field_int( n_packets, UVM_ALL_ON )
`uvm_object_utils_end
function new(string name="my_seq");
super.new(name);
endfunction
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Creating Driver
class my_drv extends uvm_driver #(packet);
virtual my_ifc vif;
`uvm_component_utils(my_drv)
function new (string name, uvm_component parent);
super.new(name, parent);
endfunction
forever begin
Transfers packet data
seq_item_port.get_next_item(req_tr);
to the interface
if (vif.reset=='1) wait(vif.reset=='0);
@(negedge vif.clk) vif.din = req_tr.pdata;
if (req_tr.last_item) vif.enable = '0; else vif.enable = '1;
@(posedge vif.clk);
`uvm_info("my_drv", {"Transaction Completed:\n", req_tr.sprint()}, UVM_MEDIUM);
seq_item_port.item_done();
end
Signals end of item processing
endtask
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to the sequencer
endclass
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Writing Monitor
class my_mon extends uvm_monitor;
virtual my_ifc vif;
int packet_count = 0;
uvm_analysis_port#(packet) ap;
`uvm_component_utils_begin(av_mon)
`uvm_field_int(packet_count, UVM_ALL_ON)
`uvm_component_utils_end
function new (string name, uvm_component parent);
super.new(name, parent);
ap = new("ap", this);
endfunction
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. . .
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ap.write(tr);
@(posedge vif.clk) void'(this.end_tr(tr));
end //if
end //forever
endtask
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Building Environment
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1ps;
1ns;
import uvm_pkg::*;
`include "uvm_macros.svh"
import my_pkg::*;
localparam CLK_PERIOD = 10;
localparam CLK_HP = CLK_PERIOD / 2.0;
logic clk;
my_ifc vif(clk);
my_env my_test;
my_dut DUT (vif);
UUT instance
Connecting virtual and real interface
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endmodule
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6.
Create test package that will contain all UVM test class descriptions.
Import uvm_pkg package and include uvm_macros.svh header in the
test package.
Include all UVM test component sources in the test package
(this way you avoid placing the same headers in all individual sources).
Include DUT sources and test package in the header of your top-level
module description.
Import uvm_pkg package and include uvm_macros.svh header inside
the top-level module description.
Compile top-level module source with your simulator-specific options.
Thats it! You are ready to go!
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UVM in Riviera-PRO
Aldec simulator provides most recent and some archival versions of
UVM library tailored to better use tool features.
Specifying +UVM_ALDEC_RECORDING +UVM_SET_RECORDING_DETAIL
switches in simulator command line records transactions for display
in the waveform.
HDL editor has built-in templates for the majority of UVM classes.
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Conclusion
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Q&A
Aldec, Inc.
Riviera-PRO
Active-HDL
+1.702.990.4400
sales@aldec.com
Europe
Israel
Japan
China
India
Taiwan
sales-eu@aldec.com
sales-il@aldec.com
ALINT
Design Rule Checking
HES
Hardware Emulation Solutions
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info@aldec.com.cn
DO-254-CTS
sales-in@aldec.com
sales-tw@aldec.com
Microsemi Prototyping
RTAX/RTSX
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