Progress report

:2

Reporting period: Week 11

Submitting date:
2/12/2014

Objectives:
The main objective of this report is to build and construct the VHDL design
for 8-bit booth multiplier.

Introduction:
In this report, we present the booth multiplier VHDL design: first of all, we
include the project Gantt chart to show the progress of the booth multiplier
design up to date .Then, we show the step by step operation flowchart of the
booth multiplier VHDL design. Next, we include the VHDL code for the booth
multiplier.
In addition, we show the schematic block diagram of the booth multiplier
VHDL design explaining all the inputs and outputs and all the possible
signals.
1. Gantt chart

Table 1: Gant Chart of project planning

Week
Task
Project planning
Overview of
booth multiplier
Flow chart of project
Overall
design
block
diagram
Booth Multiplier
VHDL design
Booth Multiplier
VHDL Testbench
Functional Simulation
LCD driver design
Testing on FPGA board

Week 10

Week 11

Week 12

Week 13

Week 14

Displaying result on LCD

(X * Y)= C
Final Report and
interview Session

2. Project Scope

The input will be in 8 bits multiply by 8 bits which will produce 16

bits of accurate multiplied answer.

The input and output of the system will only process and produce
fixed point value.

The system also accepts negative value which is called signed number.

VHDL (Very high speed integrated circuit Hardware Description

Language) is used as the language for the system.

All the process will be running using Quartus II then implement it

on Altera DE2 FPGA board to display the multiplication result.

3. Flowchart of booth multiplier VHDL design

Figure 1 shows the step by step operation of booth multiplier
VHDL design. First of all, understanding the booth multiplier operations
as shown and explained in progress report 1 is an important to design
the VHDL with highest speed and minimum logic utilization. Then the
main components for the design are identified and they are arranged
to make the design looks more systematic and easy. This arrangement
is done by designing the block diagram as shown already in progress
report 1.
By referring to the overall block diagram, the most important
components are data path unit and control unit. The components are
then designed in VHDL by Quartus II software as a platform. After
identifying the main components, then we start designing the control

unit and also the data path unit. Next, we test and simulate the design
for both control and data path unit. If it is not functioning then we
troubleshoot the control unit and data path unit design. Once the
design is functioning, then we do analysis of the speed and logic
utilization of the design.

start

Understand Booth multiplier

operation

Identify main component

used
Design block diagram

Design control unit

Troubleshoot

Design data path unit

Program in VHDL

NO

Test & simulation

Ye

End

Figure 1: Flowchart of Booth multiplier VHDL design

4. Booth multiplier design

The booth multiplier design is divided into two main units which are
data path unit and control unit.

a. Data Path Unit

Data path unit has three main components which are shifter, adder
and negative. Because of the three main operations of booth multiplier,
shift only, add Y then shift and add Y then shift, the multiplexers in the
design is performing the shifting based on the inputs selection given by
the selector. Therefore, there are 15 multiplexers, and 15 adders, and a
negative used as a 2s complement by adding it with Y. All the adding,
shifting and subtracting operations are controlled by the control unit.

b. Control Unit
For control unit, we used 15 processing AND gates as controlling
unit for the data path unit (shifter, adder and Negative). For loop from
(0 to 7) has been used to multiply all 8-bits for inputs X and Y. Once the
4

booth multiplier algorithm achieved when 00, 01, 10 or 11, then the
shifting, adding is performed according to the sequence produced by
the control unit to the data path unit.

5. VHDL code
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity Booth is
port(x: in std_logic_vector(7 downto 0);
y: in std_logic_vector(7 downto 0);
O: out std_logic_vector(15 downto 0));
end Boothm;
architecture boot of Booth is
begin
process (x, y)
variable a : std_logic_vector(16 downto 0);
variable s : std_logic_vector(7 downto 0);
variable p : std_logic_vector(7 downto 0);
variable i : integer ;
5

begin
a := "00000000000000000";
s := y;
a(8 downto 1) := x;
for i in 0 to 7 loop
if (a(1) = '1' and a(0) = '0') then
p := (a(16 downto 9));
a(16 downto 9) := (p - s);
elsif (a(1) = '0' and a(0) = '1') then
p := (a(16 downto 9));
a(16 downto 9) := (p + s);
end if;
a (15 downto 0) := a(16 downto 1);
end loop;
O (15 downto 0) <= a (16 downto 1);
end process;
end boot;

Figure 2: VHDL code for booth multiplier

1. Perform fitting (place and route ) and obtain the values for Speed and logic
Utilization.
a. Speed
The Maximum time delay T = 38.835 ns
Frequency (f) = 1/T
f = 1/ (38.835 *10^-9)
= 2574996781 Hz
= 25.75 MHz

Figure 3: Timing analyzer summary

b. Logic utilization after Fitting ( place and route)

Total logic elements = 233 out of 33216 < 1 %
Total combinational Functions = 233 out of 33216 < 1%

Figure 4: Total logic utilization of VHDL design

2. Booth Multiplier block schematic diagram

Figure 5: Block schematic diagram

Figure 5 above shows the block schematic diagram for VHDL design
as explain above. The diagram is designed to show the exact circuit of
full schematic block diagram of Booth Multiplier that has been designed
in VHDL.

3.

Summary of VHDL design specifications

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Table 2: Design specifications

Number
1
2
3
4
5
6
7
8
9
10
11

Design components
Number of inputs
Number of outputs
Length of input (X) bits
Length of input ( Y) bits
Length of output (O) bits
Number of adders used
Number of Multiplexers
Number of AND gates
Total logic elements
Maximum time delay (T)
Highest speed f (Hz)

Specificatio
2, (X,Y)
1, (Output
8 bits ( 0 to
8 bits ( 0 to
16 bits ( 0 to
15
15
14
233
38.835 ns
25.75 MH

4. Summary of Work Completed To Date

Flow chart of booth multiplier VHDL design.

Booth Multiplier design.
Booth Multiplier VHDL code.
Block schematic diagram of VHDL design.

5. Next work to be Done

Booth multiplier VHDL testbench.

Functional simulation.
Design optimization.
LCD driver design.
Testing on FPGA board and debugging.
Final Report.

11

6. References
1. Akanksha Sharma, Akriti Srivastava, Anchal Agarwal, Divya Rana and
Sonali Bansal, Design and Implementation of Booth Multiplier and Its
Application Using VHD,IJSET, vol. 3 Issue No.5, pp : 561-563, 1 May
2014.
2. Brown, S.D. and Z.G. Vranesic, Fundamentals of digital logic with VHDL
design. Vol. 70125910. 2000: McGraw-Hill New York.

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