Fast Startup CMOS Current References

Soumyajit Mandal, Scott Arfin and Rahul Sarpeshkar

Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology, Cambridge MA 02139
Email: rahuls@mit.edu
Abstract- We describe an approximately-PTAT CMOS current reference circuit that is useful for large analog systems.
An innovative capacitively-coupled startup circuit that draws no
static power is also presented. Experimental results from 0.5,um
and 0.18,um implementations are shown. Both references are
cascoded and use no resistors. The 0.18,um version operates down
to VDD= 0 5V.

sets the value of the current flowing through the mirrors; this
is mirrored out as the reference current 'ref. Assuming the
devices operate in subthreshold, 'ref is given by

Iref M=

(1 I)

where $T = kT/q is the thermal voltage. If the bulk and

I. INTRODUCTION
source terminals of the NMOS transistors are tied together,
An on-board current reference is an important part of any r1 =i, the subthreshold exponential constant. If the NMOS
analog system that has to work out in the field, since analog bulks are grounded, r1 i t.
As expected, Eqn. (1) predicts
circuits almost always require a well-defined DC bias current that aref Xo T, the absolute temperature (i.e., is PTAT). The
in order to function. In large systems, an effective biasing crut shown in Fg 1 is nominal upl inePendnt sne
strategy is to implement a single current reference and scale it as long as the transistors are saturated, the value of 'ref does
f
no don on VDD
reaty the, the
out utipeane of
using current mirrors to generate all the analog bias currents not
the
VDD.InIn reality,
depend
output impedance the
te
cip
crrets
soul
begenratd
1].Thee
on the chip [1]. These currents should be generated close reference is set by the Early voltages of the transistors and is
to the current reference and distributed across the chip. *finite
The fitevnifVDshghnohtouaneeaurin.Lg
even if VDD iS high enough to guarantee saturation. Long
alternative, distributing gate voltages which are then locally devices are used in the circuit to improve the output impedance
exponentiated (or squared) into bias currents, performs poorly as much as possible. It can also be cascoded to further increase
because the high-impedance gate lines easily pick up noise.
its output impedance if necessary. Unfortunately, cascoding
Current references where the output is proportional to abso- increases the minimum value of VDD required to guarantee
lute temperature (PTAT) are useful in bipolar and subthreshold that all transistors are saturated.
MOS design because they keep the transconductance gm c
Capacitors Cp and CN (normally implemented using MOS
qI/(kT) constant with temperature. As a result, they are often transistors to save layout area) are used to bypass the bias
known as constant-gm references. Since the temperature coef- voltages Vp and VN to VDD and ground, respectively. As a
ficients of passive elements are small, circuits using constant- result, high frequency noise on either VDD or ground is shorted
gm references for biasing have temperature-independent time out and has no effect on the output current Iref.
constants. For example, g.m - C filters with constant cut-off
It is important to note that
can vary significantly across
frequencies can be built.
different
The main reason is threshold voltage variations
chips.
In systems such as passive RFID tags and low-power sensor AVth between transistors. In order to reduce the spread in
nodes, all circuits must be ready to operate as soon as possible Iref, the W/L ratios of the transistors can be reduced so that
after power-up. The startup time of current references used in they are biased closer to strong inversion at the same current.
these systems must therefore be minimized.
This reduces the effect of AVth, since the current depends
exponentially on Vth below threshold but only in a square-law
II. CAPACITIVE STARTUP CIRCUIT
way above threshold. The disadvantage of biasing transistors in
Wefrtdsrietebscefbe
inversion is that their saturation voltage increases above
PTAT current reference. CMOS versions of this well-known
w
bipolar circuit have been periodically reported in the literature more difficult
1
[2]-[4]. A basic implementation is shown is Fig.
(for
Finally, this current reference has two possible operating
now, ignore the startup circuits inside the box). The circuit points: The desired state with the designed value of
works because the two NMOS transistors forming the current
flowing, and an undesirable condition where there is no current
mirror have different W/L ratios. The ratio of their W/L's is flowing ('ref 0). t can be proved that the sec state is
designed to be M:1, with M > 1. Because the devices carry meatbe h ici vnual lassat padge
approximately the same current (this condition is imposed by int th 'omloeaigsaebeas flaaecret
the PMOS current mirror), the larger device has a smaller ~
value of VG than the smaller device. The difference in VG
1The body effect causes 'ref to decrease by a factor of 1/,N, a significant
values is dropped across the resistor R. The value of R thus amount since K~typically has a value of about 0.7.
on

cose

'ref

sstrong

'ref

0-7803-9390-2/06/$20.00 2006 IEEE

2845

ISCAS 2006

C_START UP _

lp

l
CI-_

vp.----.

Cs-

------------

VN
1

CN-_

Lr
WCN RR~~~~~~~~~~~~~~~~

gr

__

Fig. 1. CMOS current reference with capacitively-coupled startup circuit.

passive RFID tag and needed to start up quickly so that the

read time per tag could be minimized. We used wide-swing
cascode mirrors to ensure high output resistance even at low
VDD. The cascode bias voltages VCp and VCN were set such
that the current source transistors had barely enough VDS
across them (about 100mV) to keep them saturated. For the
PMOS mirror, geometric scaling was sufficient. By making
the cascode transistors much wider than the current sources,
their VGS drop can be reduced. Thus setting VCP Vp using
a mirrored copy of the output current provides enough VDS
across the current source transistors. This approach does not
work for the NMOS mirror because of two reasons: Vs is not
at ground, and the cascode transistors have increased threshold
voltage because of body effect. The result is that extreme
geometric scaling ratios are needed to get enough VDS across
the current source transistors if VCN VN. We therefore use
an auxiliary cascoded NMOS mirror (shown on the right in
Fig. 2) to set VCN VN + 200mV.
The current reference uses the same capacitively-coupled
startup strategy as before. However, two switches are used to
ensure fast startup: One between Vp and VN, and the other
between VCp and VCN. In addition, the layout area of the
reference is reduced by replacing the large resistor R that
sets the value of the current by a string of NMOS transistors
operating in the linear (triode) region [3]. There are N1 + N2
identical devices connected in series as shown to form the
current-defining resistor. The reference current is given by

and supply voltage transients. However, this process can take

a long time. We have found that the startup time depends
strongly on VDD, the operating current 'ref and the sizes
of Cp and CN. If VDD and 'ref are low and Cp and CN
are large, the circuit can take several seconds or minutes to
start up. While this may be acceptable for some systems, it
is clearly not desirable for RFID tags, which have to power
up and respond to reader interrogation within a few hundred
,us. We have thus designed an innovative startup circuit for
the reference (shown inside the dashed lines in Fig. 1). Most
startup circuits for constant-gm references use a string of
(2)
diode-connected devices to generate a leakage current. This
Iref = Kin(T)2CoxS (In M)2
is not an elegant approach - the leakage current is VDDdependent and consumes extra static power. In contrast, our where K is a technology-independent constant that depends on
startup circuit consumes no static power and works over a N1, N2 and the current-mirror ratio R = 'triode /Iref (where
'triode is the current through the triode transistors). Analytical
wide range of power supply voltages.
Consider the initial state of the system, with the supply formulas have been found for K but are too complicated to
voltage at zero and all capacitors uncharged. When VDD is provide insight for actual design. Also, the triode devices have
switched on, Vp goes to VDD, and VN stays at ground. Thus W/L = S, gate oxide capacitance density COX and electron
no current flows. However, Cs is also uncharged, and thus the mobility ,n. In order to reduce the effect of threshold voltage
gate of the NMOS switch connected between Vp and VN is at variations while minimizing layout area, S was set to a value
VDD. The switch thus turns on, shunting charge from Vp to just low enough to place these transistors in moderate inversion
VN. This shunting lowers Vp and raises VN, so current starts at the operating current. Finally, 'ref varies with temperature
flowing and the circuit starts up. In addition, a copy of the as un (T)T2, and so is not guaranteed to be PTAT. In our
12, and the devices were
output current placed in series with Cs discharges the bottom design, R = 2, N1 = 10, N2
lOnA with M = 5. All
plate of Cs to ground. Thus the gate voltage of the startup sized to yield a current of 'ref
switch eventually goes to zero; the startup circuit, its job the important gate voltages in the circuit (Vp, VCP, VCN and
done, shuts off2. Startup time can be reduced by increasing the VN) are bypassed to VDD or ground using lpF or 2pF MIM
sizes of the startup switches. We have experimentally verified capacitors. The startup capacitor Cs was set to 2pF. The total
the operation of this startup circuit in several CMOS process static current consumption of the reference was 6lref . This can
be easily reduced to 31ref by making R = 1 and reducing
technologies.
the current through the auxiliary NMOS mirror (currently set
to Iref) to a small value <'ref.
III. O.18,IM CURRENT REFERENCE
Experimentally measured and simulated DC I-V curves for
We, designed An improved version of the, current referencel
shown in Fig. 1 in the UMC L180 O.18/um CMOS process. this circuit are shown in Fig. 3. We see that the measured
The ircut,
sownin Fg. 2 wasmeat fo useinsie a curves closely match simulation results. The circuit operates
'
~~~~~~~~~~normallydown to VDD =0.5V and, because of the cascodes,
'
rmtnciso
2Power-on reset circuits for digital logic tend to operate in a similar way. hsigh output ressac.Maueet
the same fabrication run are shown. The standard deviation
The current source is typically replaced by a resistor.
r

2846

was 7.6% of the mean current value of 10.6nA. Fig. 4 shows

0.45
measured startup transient response of the circuit when VDD iS
VN
stepped from 0 to 0.5V. Note that the steady state values of Vp
0.4
VON
and Vcp are lower than VN and VCN because VDD is so low.
0.35V
The startup circuit ensures that the circuit starts up in less than
0.3
P
600,us. This startup time decreases sharply as VDD increases.
Also, our circuit uses only normal-Vth transistors. Low-Vth
, 0.25
devices available in our process were not used. Using low-Vth
0
PMOS devices, for example, can further lower the minimum
supply voltage required for operation. However, we found
0.15 ----r
from simulations that the variation in 'ref across process
corners increases significantly when these devices were used30
0.05

____

lCs

VCP l

N2 0

Lll

VCN 1: 71

' Vs.,

N1I LF+ER

L11

C
E L1X i
i __

MA11
Vs
R f

jj

Irl
L1

I.,.,.' tI -1500

Fig. 4.

-1000

Time0

-500

(its)

500

1000

1500

8,im

Measured 0. 1
current reference voltage waveforms during startup.
The supply voltage was stepped from 0 to 0.5V at time=0.

Lll l
r

PTAT until about 40C, indicating that ,u XC 1/T. At higher

temperatures, 'ref reaches a maximum, begins to decrease and

Ir
L1

then rapidly turns off. This behavior is hysteretic, indicating

the presence of positive feedback. The problem is not
but

p,u

the fact that MOS threshold voltages decrease almost linearly

as the temperature increases. This reduces VCN, which in turn
brings the NMOS with its source at Vs out of saturation. Since
this device now needs more VGS to carry the same current,
Vs must decrease. This decreases 'ref , which further reduces
VCN and completes the feedback loop. The phenomenon can
be avoided by increasing VCN; this reduces the loop gain but
increases the minimum VDD needed for normal operation.

VN

____ i________

Fig. 2. Improved CMOS current reference circuit.

12

8~~~~~~~~~~~~~~~~~~~~~~
1
1.5

-C
0
0.5
4

<

~
2
~~~~=
~
_

...................

-- -- -- -- -- -- -- -- -- -

6 SImulated

..

..

--

Simulated
and2measured8DCI-VceSilthe
VDD (V)~
~ ~ ~

--

--

=05

~~~~~~~~~~~~~~~~~~~

-10

Fig.3.

0:8---

..

-------DD

10

20

30

40

1.2V _VD50

60

---------

~
~
~~~2
L

70

80

90

~~~~~~~~D

2~~~~~~~~~~~~~~~~~~~~~~~~~~~~~D
_O2F-

--------------

-----------------------------------H

refrece
Measuremen reut fro teIhpaeson

Fig. 5.

Fig. 5 shows measured values of 'ref versus temperature

for various values of VDD. We see that 'ref is approximately

3The Vth in these devices can be low enough that at our current level diode-

connected transistors have VDS = VGS < l00mV and are not saturated. This
makes current mirror operation unreliable, leading to large variations in 'ref.

Measured temperature sweep data of the 0.1e8,um (top) and 0.5,m

(bottom) current references for various supply voltages.

The total layout area of the reference was approximately

150,um x 150,um, most of which was occupied by the linear
bypass and startup capacitors. These can be replaced by MOS

2847

capacitors to reduce layout area.

100
|

IV. 0.51uM CURRENT REFERENCE

The same basic topology with a capacitively-coupled startup
circuit and no resistors shown in Fig. 2, but using simple
cascode mirrors, was also used to build a current reference
in the AMI 0.5,um process. High transistor threshold voltages (particularly PMOS) in this process and the absence of

10
;.;
^...-'-.g
F 10 2
;.;.;
;..
-.;...-;.-

wide-swing cascodes limited the minimum VDD needed for

saturation to 2.2V. This reference was designed to produce
5OnA. However, measured values of 'ref were about 25nA.
Inaccurate transistor models, particularly in the triode region,
are suspected. The circuit was designed to be a standard analog
cell; it was built into a corner pad in order to occupy no layout
area in the core. Each chip contained four references (one in
each corner). Deviations in output current across chips can be
significantly reduced by adding together the currents produced

by the four references on each chip. Chip-to-chip deviations

were reduced to within 10% of the mean value when this
procedure was carried out.
We define startup time as the time taken by the reference
current to reach 90% of its steady state value. Startup times
are strongly dependent on the supply voltage. Fig. 6 shows
startup time versus VDD, measured by switching on VDD
while simultaneously measuring the current flowing through
the circuit. The measured startup times spanned nearly four
orders of magnitude as VDD was varied from 1.8V to 5V.
We note three distinct startup regimes, visible in Fig. 6 as
different slopes in the startup time curve. For VDD < 3V, a
dead zone, when almost no current flows in the reference,
appears as soon as the supply is switched on. Eventually,
however, a rapid rise in the output current is observed, and
the circuit is said to have started up. The shape of this rise
is similar to that of a first-order RC circuit. The length of
the dead zone decreases exponentially with the supply voltage
until about
3V,3V,when
when it
it becomes
becomes too
too small
to be
be observable.
In
until about
small to
observable.In

this second regime (3V< VDD <4V) switching on the supply

causes the current to rise immediately while following a firstorder response. The rise time decreases weakly with VDD.
Once VDD > 4V, the rise time begins to decrease rapidly.
Overshoot and ringing in the step response can be observed
when VDD > 5V. In this regime startup is so fast that the
dynamics of parasitic poles in the circuit start affecting it.
Figure 7 shows measured startup waveforms at VDD = 2.5V.
A dead zone about 17ms long followed by a first-order rise to
steady state is visible in 'ref.
The temperature dependence of this reference was measured
from -10C to 90C; it was found to be very close to PTAT
over the entire range, again indicating that un CX I/T (see
The behavior of hole mobility lip versus temperature
Fig.
Fig. 5).
5).uidb
MO version
eso
hscrut
can be
studied by bidn
building a PMOS
off this
circuit.

--......

.............

10-

0-4
1.5
Fig. 6.

2.5

3
3.5
VDD (V)

>
5

4.5

Experimentally observed 0.5,um current reference startup time versus

supply voltage.

............-

20

10
0

- -

1C

-20

-10

0.4 ------------------

----------------------10

Time (ms)
--

20

---------

30

40

------------

> 0.2 -

-20

-10

10
20
Time (ms)

30

40

Fig.
7. Measured output current (top) stepped
NMOS
the 0.5,um current reference. VDD was and
frombias
0 tovoltage
2.5V at(bottom)
time=0. of

references in different CMOS processes. This paper summarizes our results. Some new ideas are presented, including
a capacitively-coupled startup circuit that consumes no static
power and the use of self-biased cascodes to reduce supplyvoltage requirements.

REFERENCES
[1] R. Sarpeshkar, C. Salthouse, J.-J. Sit, M. W. Baker, S. M. Zhak, T. K.-T.
Lu, L. Turicchia, and S. Balster, "An Ultra-Low-Power Programmable
Analog Bionic Ear Processor," IEEE Transactions on Biomedical Engineering, vol. 52, no. 4, pp. 711-727, Apr. 2005.
[2] H. J. Oguey and D. Aebischer, "CMOS Current Reference Without
Resistance," IEEE Journal of Solid-State Circuits, vol. 32, no. 7, pp.
32-1135, July 1997.
[3] E.11 M. Camacho-Galeano, C. Galup-Montoro, and M. C. Schneider, "A
2-nW 1.1-V Self-Biased Current Reference in CMOS Technology," IEEE

Transactions on Ciruits and Systems-II, vol. 52, no. 2, pp. 61-65, Feb.

V. CONCLUSION
We have described techniques for building reliable low-

voltage bias circuits for large analog systems. We have built

and successfully used several generations of these current

[4] F. Serra-Graells and J. L. Huertas, "Sub-1-V CMOS Proportional-to-

2848

Absolute-Temperature References," IEEE Journal of Solid-State Circuits,

vol. 38, no. 1, pp. 84-88, Jan. 2003.