Unit 4 Application of Boolean

Algebra

Department of Communication Engineering, NCTU

Logic Design Unit 4 Application of Boolean Algebra

Sau-Hsuan Wu

Three main steps in designing a single-output

combinational logic circuit
Find a switching function that specifies the desired
behavior of the circuit
Find a simplified algebraic expression for the function
Realized the simplified function using available logic
elements
Goals:
How to specify circuit behaviors
How to design a combinational logic circuit

Department of Communication Engineering, NCTU

4.1 Conversion of English

Sentences to Boolean Equations

Department of Communication Engineering, NCTU

Logic Design Unit 4 Application of Boolean Algebra

Sau-Hsuan Wu

For simple problems, go directly from a word description

of the desired circuit behavior to an algebra expression
Mary watches TV if it is Monday night and she has
finished her homework.
F = AB
The alarm will ring iff
the alarm switch is turned on
and the door is not closed,
or it is after 6 P.M.
and the window is not closed.
Z = AB' + CD'

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4.2 Combinational Logic Design

Using a Truth Table

Department of Communication Engineering, NCTU

Logic Design Unit 4 Application of Boolean Algebra

Sau-Hsuan Wu

In general, a truth table to design logic circuits

First, list a true table
E.g.

Derive an algebraic expression for f from the table

f = A'BC + AB'C' + AB'C + ABC' + ABC
= A+BC

Department of Communication Engineering, NCTU

(4-1)

Logic Design Unit 4 Application of Boolean Algebra

Sau-Hsuan Wu

In stead of writing f in terms of the 1

s of the function,
we may also write f in terms of the 0
s of the function
E.g.
f = (A+B+C)(A+B+C')(A+B'+C)
= (A+B)(A+B'+C) = A + BC

Department of Communication Engineering, NCTU

(4-3)

4.3 Minterm and Maxterm

Expansions

Department of Communication Engineering, NCTU

Logic Design Unit 4 Application of Boolean Algebra

Each term in (4-1) is referred to as a minterm

f = A'BC + AB'C' + AB'C + ABC' + ABC

Sau-Hsuan Wu

(4-1)

A function written as a sum of minterms is referred to

as a minterm expansion or a standard SOP

Each term in (4-3) is referred to as a maxterm

f = (A+B+C)(A+B+C')(A+B'+C)

(4-3)

A function written as a product of maxterms is referred

to as a maxterm expansion or a standard POS

Department of Communication Engineering, NCTU

Logic Design Unit 4 Application of Boolean Algebra

Sau-Hsuan Wu

A minterm of n variables is a product of n literals in

which each variable appears exactly once in either true or
complemented form
The decimal notation of minterm expansion
e.g.
f = m (3,4,7)

Department of Communication Engineering, NCTU

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Logic Design Unit 4 Application of Boolean Algebra

Sau-Hsuan Wu

A maxterm of n variables is a sum of n literals in which

each variable appears exactly once in either true or
complemented form
The decimal notation of maxterm expansion
E.g.
f = M(0,,2)
Given the minterm or maxterm expansions for f , the
minterm or maxterm expansions for the complement of f
are easy to obtain
E.g.
f
m0 m1 m2 m(0,1,2)

Or

f
M (3,4,5,6,7) M 3 M 4 M 5 M 6 M 7

f
( M 0 M 1M 2 )
M 0
M 1
M 2
m0 m1 m2
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Logic Design Unit 4 Application of Boolean Algebra

Sau-Hsuan Wu

A general switching expansion can be converted to a

minterm or a maxterm expansion either using a truth table
or algebraically
For algebraic method, first write the expansion as a sum
of products and then introduce the missing variables in
each term by applying the theorem X + X
=1
Example f(a,b,c,d) = a
(b
+d) + acd
1> SOP: f= a
b
+a
d+acd
Introduce missing variables
f= a
b
(c+c
)(d+d
)+a
(b+b
)(c+c
)d+ a(b+b
)cd
= a
b
c
d
+a
b
c
d+a
b
cd
+a
b
cd+a
b
c
d+a
b
cd
+ a
b
cd + a
bcd + abcd+ ab
cd
= m (0,1,2,3,5,7,10,14)

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Logic Design Unit 4 Application of Boolean Algebra

Sau-Hsuan Wu

General minterm and maxterm expansions

A general minterm expansion
f = a0m0 + a1m1+ + a7m7 = ai mi
ai = 0 or 1
mi is not present if ai = 0

A general maxterm expansion

f = (0 + M0)(1 + M1) (7 + M7) = (i + Mi)

i = 0 or 1
Mi is not present if i = 1
Equality
ai mi = (i + Mi)

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4.5 Incompletely Specified

Functions

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Logic Design Unit 4 Application of Boolean Algebra

Sau-Hsuan Wu

A large system is usually divided into many subcircuits.

The output of module 1 may not generate all possible
combinations for the input variables of module 2.
In this case, we don
t care these specific combinations
when designing the switch circuit for F

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Logic Design Unit 4 Application of Boolean Algebra

Sau-Hsuan Wu

When realizing the function, the don

t care terms can be
assigned 0
s or 1
s
If both X
s are assigned 0
F = A'B'C' + A'BC +ABC = A'B'C' + BC

If first X is assigned 1 and the second 0

F = A'B'C' + A'B'C + A'BC +ABC = A'B' + BC

If we assign 1 to both X
s
F = A'B'C' + A'B'C + A'BC + ABC' + ABC
= A'B' + BC + AB

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4.5 Examples of Truth Table

Construction

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Logic Design Unit 4 Application of Boolean Algebra

Sau-Hsuan Wu

Department of Communication Engineering, NCTU

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Logic Design Unit 4 Application of Boolean Algebra

Sau-Hsuan Wu

Error detector for 6-3-1-1 binary-coded-decimal digits

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Logic Design Unit 4 Application of Boolean Algebra

Sau-Hsuan Wu

Switching Expression

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4.5 Design of Binary Adders

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Logic Design Unit 4 Application of Boolean Algebra

Sau-Hsuan Wu

Design a 4-bit binary ripple carry adder

Approach 1:
construct a truth table

Approach 2: cascade 4 1-bit Full Adders

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Logic Design Unit 4 Application of Boolean Algebra

Construct the true table for

1-bit full adder

Find the switching expressions

Sau-Hsuan Wu

Sum X
Y Cin X
YCin
XY
Cin
XYCin
X
(Y
Cin YCin
) X (Y
Cin
YCin )
X
(Y Cin ) X (Y Cin )
X Y Cin
Cout X
YCin XY
Cin XYCin
XYCin
( X
YCin XYCin ) ( XY
Cin XYCin ) ( XYCin
XYCin )
YCin XCin XY
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Logic Design Unit 4 Application of Boolean Algebra

Sau-Hsuan Wu

Implement the functions with logic gates

Overflow occurs if adding two positive numbers gives a

negative result, or adding two negative numbers results in
a positive number

V A3
B3
S3 A3 B3 S3
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Logic Design Unit 4 Application of Boolean Algebra

Sau-Hsuan Wu

The pros and cons of ripple carry adder

Simple in concept
The carry output at stage i+1
Ci+1 = XiYi + (Xi + Yi) Ci
The carries propagate like a ripple and introduce circuit
delays : C0
C1 C2 Ci+1
Ci+1 = f (Xi,Yi, Ci) = f (Xi,Yi,Xi-1,Yi-1,Ci-1) =
Alternative: Carry lookahead adder
To avoid circuit delays due to the propagation of
carries
Express Ci+1 in terms of C0 and {X0,Yi Xi,Yi} only

Department of Communication Engineering, NCTU

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Logic Design Unit 4 Application of Boolean Algebra

Sau-Hsuan Wu

Re-write the output carry at the ith stage as

Ci+1 = gi + pi Ci
The carry-generate function: gi = XiYi
The carry-propagate function pi = Xi + Yi
Expression the carry bit in terms of gi and pi
C1 = g 0 + p 0 C0
C2 = g1 + p1 C1 = g1 + p1 g0 + p1 p0 C0
C3 = g2 + p2 C2 = g2 + p2 g1 + p2 p1 g0 + p2 p1 p0 C0

Ci = gi + pi gi-1 + pi pi-1gi-2 + + pi pi-1 pi-2 g0

+ pi pi-1 pi-2 p0C0

Department of Communication Engineering, NCTU

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Logic Design Unit 4 Application of Boolean Algebra

Sau-Hsuan Wu

The circuit implementation of 4-bit carry lookahead adder

Carry lookahead network

block

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Logic Design Unit 4 Application of Boolean Algebra

Sau-Hsuan Wu

For adders with higher number of bits, the carry

lookahead network can get quite large in terms of gates
and gate inputs. This also presents a limitation in the
realization of a large high speed adder
How to circumvent this problem?

Cascade 4-bit carry lookahead adders to form a lager adder

Department of Communication Engineering, NCTU

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Logic Design Unit 4 Application of Boolean Algebra

Sau-Hsuan Wu

Partition the operands into blocks

E.g.
C8 = g7 + p7 g6 + p7 p6g5 + p7 p6p5g4 + p7 p6p5p4g3 +
p7 p6p5p4p3g2 + p7 p6p5p4p3p2g1 + p7 p6p5p4p3p2p1g0+
p7 p6p5p4p3p2p1p0C0
= g7 + p7 g6 + p7 p6g5 + p7 p6p5g4 +
p7 p6p5p4 (g3 + p3g2 + p3p2g1 + p3p2p1g0) +
p7 p6p5p4(p3p2p1p0C0)
= G1 + P1G0 + P1P0C0
G1= g7 + p7 g6 + p7 p6g5 + p7 p6p5g4
P1 = p7 p6p5p4
G0= g3 + p3g2 + p3p2g1 + p3p2p1g0
P0 = p3p2p1p0

Department of Communication Engineering, NCTU

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Logic Design Unit 4 Application of Boolean Algebra

Sau-Hsuan Wu

Define a 4-bit carry lookahead generator as

G= g3 + p3g2 + p3p2g1 + p3p2p1g0
P = p3p2p1p0

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