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2016.06.10
CV-51001
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The Cyclone V devices are designed to simultaneously accommodate the shrinking power consumption,
cost, and time-to-market requirements; and the increasing bandwidth requirements for high-volume and
cost-sensitive applications.
Enhanced with integrated transceivers and hard memory controllers, the Cyclone V devices are suitable
for applications in the industrial, wireless and wireline, military, and automotive markets.
Related Information
Supporting Feature
Lower power consumption Built on TSMC's 28 nm low-power (28LP) process technology and
includes an abundance of hard intellectual property (IP) blocks
Up to 40% lower power consumption than the previous generation
device
Improved logic integration 8-input adaptive logic module (ALM)
and differentiation capabil Up to 13.59 megabits (Mb) of embedded memory
ities
Variable-precision digital signal processing (DSP) blocks
Increased bandwidth
capacity
2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
CV-51001
2016.06.10
Advantage
Supporting Feature
Technology
Packaging
High-performance
FPGA fabric
Internal memory
blocks
Description
Memory controller
Embedded
transceiver I/O
PCI Express (PCIe) Gen2 and Gen1 (x1, x2, or x4) hard IP
with multifunction support, endpoint, and root port
Embedded Hard IP
blocks
Clock networks
(1)
Altera Corporation
CV-51001
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Feature
Phase-locked loops
(PLLs)
FPGA Generalpurpose I/Os
(GPIOs)
Description
Precision clock synthesis, clock delay compensation, and zero delay buffering
(ZDB)
Integer mode and fractional mode
875 megabits per second (Mbps) LVDS receiver and 840 Mbps LVDS transmitter
400 MHz/800 Mbps external memory interface
On-chip termination (OCT)
3.3 V support with up to 16 mA drive strength
(2)
The SEU internal scrubbing feature is available for Cyclone V E, GX, SE, and SX devices with the "SC"
suffix in the part number. For device availability and ordering, contact your local Altera sales representa
tives.
Altera Corporation
CV-51001
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Cyclone V E
Description
Optimized for the lowest system cost and power requirement for a wide spectrum of
general logic and DSP applications
Cyclone V GX
Optimized for the lowest cost and power requirement for 614 Mbps to 3.125 Gbps
transceiver applications
Cyclone V GT
The FPGA industrys lowest cost and lowest power requirement for 6.144 Gbps
transceiver applications
Cyclone V SE
Cyclone V SX
Cyclone V ST
Cyclone V E
This section provides the available options, maximum resource counts, and package plan for the
Cyclone V E devices.
The information in this section is correct at the time of publication. For the latest information and to get
more details, refer to the Altera Product Selector.
Related Information
(3)
The partial reconfiguration feature is available for Cyclone V E, GX, SE, and SX devices with the "SC"
suffix in the part number. For device availability and ordering, contact your local Altera sales representa
tives.
Altera Corporation
CV-51001
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Available Options
Available Options
Figure 1: Sample Ordering Code and Available Options for Cyclone V E Devices
The SEU internal scrubbing feature is available for Cyclone V E, GX, SE, and SX devices with the "SC"
suffix in the part number. For device availability and ordering, contact your local Altera sales
representatives.
Package Type
F : FineLine BGA (FBGA)
U : Ultra FineLine BGA (UBGA)
M : Micro FineLine BGA (MBGA)
Operating Temperature
C : Commercial (TJ = 0 C to 85 C)
I : Industrial (TJ = -40 C to 100 C)
A : Automotive (TJ = -40 C to 125 C)
5C
A9
Family Variant
E : Enhanced logic/memory
Member Code
A2 : 25K logic elements
A4 : 49K logic elements
A5 : 77K logic elements
A7 : 150K logic elements
A9 : 301K logic elements
31
Package Code
FBGA Package Type
17 : 256 pins
23 : 484 pins
27 : 672 pins
31 : 896 pins
UBGA Package Type
15 : 324 pins
19 : 484 pins
MBGA Package Type
13 : 383 pins
15 : 484 pins
Optional Suffix
Indicates specific device
options or shipment method
N : Lead-free packaging
Contact Altera for availability
of leaded options
ES : Engineering sample
SC : Internal scrubbing support
Maximum Resources
Table 4: Maximum Resource Counts for Cyclone V E Devices
Member Code
Resource
A2
A4
A5
A7
A9
25
49
77
150
301
ALM
9,434
18,480
29,080
56,480
113,560
Register
37,736
73,920
116,320
225,920
454,240
M10K
1,760
3,080
4,460
6,860
12,200
MLAB
196
303
424
836
1,717
Variable-precision DSP
Block
25
66
150
156
342
18 x 18 Multiplier
50
132
300
312
684
PLL
Memory
(Kb)
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Package Plan
Member Code
Resource
A2
A4
A5
A7
A9
224
224
240
480
480
Transmitter
56
56
60
120
120
Receiver
56
56
60
120
120
GPIO
LVDS
Package Plan
Table 5: Package Plan for Cyclone V E Devices
M383
M484
U324
F256
U484
F484
F672
F896
(13 mm)
(15 mm)
(15 mm)
(17 mm)
(19 mm)
(23 mm)
(27 mm)
(31 mm)
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
A2
223
176
128
224
224
A4
223
176
128
224
224
A5
175
224
240
A7
240
240
240
336
480
A9
240
224
336
480
Member
Code
Cyclone V GX
This section provides the available options, maximum resource counts, and package plan for the
Cyclone V GX devices.
The information in this section is correct at the time of publication. For the latest information and to get
more details, refer to the Altera Product Selector.
Related Information
Altera Corporation
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Available Options
Available Options
Figure 2: Sample Ordering Code and Available Options for Cyclone V GX Devices
The SEU internal scrubbing feature is available for Cyclone V E, GX, SE, and SX devices with the "SC"
suffix in the part number. For device availability and ordering, contact your local Altera sales
representatives.
GX
5C
C9
Family Variant
GX : 3-Gbps transceivers
Member Code
C3 : 36K logic elements
C4 : 50K logic elements
C5 : 77K logic elements
C7 : 150K logic elements
C9 : 301K logic elements
Package Type
F : FineLine BGA (FBGA)
U : Ultra FineLine BGA (UBGA)
M : Micro FineLine BGA (MBGA)
Operating Temperature
C : Commercial (TJ = 0 C to 85 C)
I : Industrial (TJ = -40 C to 100 C)
A : Automotive (TJ = -40 C to 125 C)
Transceiver Count
B : 3
F : 4
A : 5
C : 6
D : 9
E : 12
Transceiver
Speed Grade
6 : 3.125 Gbps
7 : 2.5 Gbps
35
N
Optional Suffix
Indicates specific device
options or shipment method
N : Lead-free packaging
Contact Altera for availability
of leaded options
ES : Engineering sample
SC : Internal scrubbing support
Package Code
FBGA Package Type
23 : 484 pins
27 : 672 pins
31 : 896 pins
35 : 1,152 pins
UBGA Package Type
15 : 324 pins
19 : 484 pins
MBGA Package Type
11 : 301 pins
13 : 383 pins
15 : 484 pins
FPGA Fabric
Speed Grade
6 (fastest)
7
8
Maximum Resources
Table 6: Maximum Resource Counts for Cyclone V GX Devices
Resource
Member Code
C3
C4
C5
C7
C9
36
50
77
150
301
ALM
13,460
18,860
29,080
56,480
113,560
Register
53,840
75,440
116,320
225,920
454,240
M10K
1,350
2,500
4,460
6,860
12,200
MLAB
182
424
424
836
1,717
Variable-precision DSP
Block
57
70
150
156
342
18 x 18 Multiplier
114
140
300
312
684
Memory
(Kb)
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CV-51001
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Package Plan
Member Code
Resource
C3
C4
C5
C7
C9
PLL
3 Gbps Transceiver
12
208
336
336
480
560
Transmitter
52
84
84
120
140
Receiver
52
84
84
120
140
Hard Memory
Controller
GPIO(4)
LVDS
Related Information
Package Plan
Table 7: Package Plan for Cyclone V GX Devices
Member
Code
M301
M383
M484
U324
U484
(11 mm)
(13 mm)
(15 mm)
(15 mm)
(19 mm)
GPIO
XCVR
GPIO
XCVR
GPIO
XCVR
GPIO
XCVR
GPIO
XCVR
C3
144
208
C4
129
175
224
C5
129
175
224
C7
240
240
C9
240
Member
Code
(4)
F484
F672
F896
F1152
(23 mm)
(27 mm)
(31 mm)
(35 mm)
GPIO
XCVR
GPIO
XCVR
GPIO
XCVR
GPIO
XCVR
C3
208
C4
240
336
C5
240
336
C7
240
336
480
C9
224
336
480
12
560
12
The number of GPIOs does not include transceiver I/Os. In the Quartus Prime software, the number of
user I/Os includes transceiver I/Os.
Altera Corporation
CV-51001
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Cyclone V GT
Cyclone V GT
This section provides the available options, maximum resource counts, and package plan for the
Cyclone V GT devices.
The information in this section is correct at the time of publication. For the latest information and to get
more details, refer to the Altera Product Selector.
Related Information
Available Options
Figure 3: Sample Ordering Code and Available Options for Cyclone V GT Devices
Transceiver Count
B : 3
F : 4
A : 5
C : 6
D : 9
E : 12
5C
GT
D9
Family Variant
GT : 6-Gbps transceivers
Member Code
D5 : 77K logic elements
D7 : 150K logic elements
D9 : 301K logic elements
Package Type
F : FineLine BGA (FBGA)
U : Ultra FineLine BGA (UBGA)
M : Micro FineLine BGA (MBGA)
Operating Temperature
C : Commercial (TJ = 0 C to 85 C)
I : Industrial (TJ = -40 C to 100 C)
A : Automotive (TJ = -40 C to 125 C)
Transceiver
Speed Grade
5 : 6.144 Gbps
35
Package Code
FBGA Package Type
23 : 484 pins
27 : 672 pins
31 : 896 pins
35 : 1,152 pins
UBGA Package Type
19 : 484 pins
MBGA Package Type
11 : 301 pins
13 : 383 pins
15 : 484 pins
N
Optional Suffix
Indicates specific device
options or shipment method
N : Lead-free packaging
Contact Altera for availability
of leaded options
ES : Engineering sample
FPGA Fabric
Speed Grade
7
Maximum Resources
Table 8: Maximum Resource Counts for Cyclone V GT Devices
Resource
Member Code
D5
D7
D9
77
150
301
ALM
29,080
56,480
113,560
Register
116,320
225,920
454,240
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Package Plan
Member Code
Resource
D5
D7
D9
M10K
4,460
6,860
12,200
MLAB
424
836
1,717
150
156
342
18 x 18 Multiplier
300
312
684
PLL
6 Gbps Transceiver
12
336
480
560
Transmitter
84
120
140
Receiver
84
120
140
Memory (Kb)
GPIO(5)
LVDS
Related Information
Package Plan
Table 9: Package Plan for Cyclone V GT Devices
Transceiver counts shown are for transceiver 5 Gbps . 6 Gbps transceiver channel count support depends on the
package and channel usage. For more information about the 6 Gbps transceiver channel count, refer to the
Cyclone V Device Handbook Volume 2: Transceivers.
Member
Code
M383
M484
U484
(11 mm)
(13 mm)
(15 mm)
(19 mm)
GPIO
XCVR
GPIO
XCVR
GPIO
XCVR
GPIO
XCVR
D5
129
175
224
D7
240
240
D9
240
Member
Code
(5)
M301
F484
F672
F896
F1152
(23 mm)
(27 mm)
(31 mm)
(35 mm)
GPIO
XCVR
GPIO
XCVR
GPIO
XCVR
GPIO
XCVR
D5
240
336
D7
240
336
480
(6)
(6)
The number of GPIOs does not include transceiver I/Os. In the Quartus Prime software, the number of user
I/Os includes transceiver I/Os.
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11
Cyclone V SE
Member
Code
F484
F672
F896
F1152
(23 mm)
(27 mm)
(31 mm)
(35 mm)
GPIO
XCVR
GPIO
224
336
D9
XCVR
(6)
GPIO
480
XCVR
12
(7)
GPIO
XCVR
560
12 (7)
Related Information
Cyclone V SE
This section provides the available options, maximum resource counts, and package plan for the
Cyclone V SE devices.
The information in this section is correct at the time of publication. For the latest information and to get
more details, refer to the Altera Product Selector.
Related Information
(6)
(7)
If you require CPRI (at 6.144 Gbps) and PCIe Gen2 transmit jitter compliance, Altera recommends that you
use only up to three full-duplex transceiver channels for CPRI, and up to six full-duplex channels for PCIe
Gen2. The CMU channels are not considered full-duplex channels.
If you require CPRI (at 6.144 Gbps) and PCIe Gen2 transmit jitter compliance, Altera recommends that you
use only up to three full-duplex transceiver channels for CPRI, and up to eight full-duplex channels for PCIe
Gen2. The CMU channels are not considered full-duplex channels.
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Available Options
Available Options
Figure 4: Sample Ordering Code and Available Options for Cyclone V SE Devices
The SEU internal scrubbing feature is available for Cyclone V E, GX, SE, and SX devices with the "SC"
suffix in the part number. For device availability and ordering, contact your local Altera sales
representatives.
Package Type
F : FineLine BGA (FBGA)
U : Ultra FineLine BGA (UBGA)
Embedded Hard IPs
B : No hard PCIe or hard
memory controller
M : No hard PCIe and
1 hard memory controller
Family Signature
5C : Cyclone V
5C
SE
Family Variant
SE : SoC with enhanced logic/memory
Member Code
A2 : 25K logic elements
A4 : 40K logic elements
A5 : 85K logic elements
A6 : 110K logic elements
Altera Corporation
A6
Operating Temperature
C : Commercial (TJ = 0 C to 85 C)
I : Industrial (TJ = -40 C to 100 C)
A : Automotive (TJ = -40 C to 125 C)
Processor Cores
Omit for dual-core
S : Single-core
31
Package Code
FBGA Package Type
31 : 896 pins
UBGA Package Type
19 : 484 pins
23 : 672 pins
Optional Suffix
Indicates specific device
options or shipment method
N : Lead-free packaging
Contact Altera for availability
FPGA Fabric of leaded options
Speed Grade ES : Engineering sample
6 (fastest)
SC : Internal scrubbing support
7
8
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Maximum Resources
13
Maximum Resources
Table 10: Maximum Resource Counts for Cyclone V SE Devices
Member Code
Resource
A2
A4
A5
A6
25
40
85
110
ALM
9,434
15,094
32,075
41,509
Register
37,736
60,376
128,300
166,036
M10K
1,400
2,700
3,970
5,570
MLAB
138
231
480
621
Variable-precision DSP
Block
36
84
87
112
18 x 18 Multiplier
72
168
174
224
FPGA PLL
HPS PLL
FPGA GPIO
145
145
288
288
HPS I/O
181
181
181
181
Transmitter
32
32
72
72
Receiver
37
37
72
72
Single- or
dual-core
Single- or
dual-core
Single- or dualcore
Single- or dual-core
Memory
(Kb)
LVDS
Package Plan
Table 11: Package Plan for Cyclone V SE Devices
The HPS I/O counts are the number of I/Os in the HPS and does not correlate with the number of HPS-specific
I/O pins in the FPGA. Each HPS-specific pin in the FPGA may be mapped to several HPS I/Os.
Member
Code
U672
F896
(19 mm)
(23 mm)
(31 mm)
FPGA GPIO
HPS I/O
FPGA GPIO
HPS I/O
FPGA GPIO
HPS I/O
66
151
145
181
A2
Cyclone V Device Overview
Send Feedback
U484
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Cyclone V SX
Member
Code
U484
U672
F896
(19 mm)
(23 mm)
(31 mm)
FPGA GPIO
HPS I/O
FPGA GPIO
HPS I/O
FPGA GPIO
HPS I/O
A4
66
151
145
181
A5
66
151
145
181
288
181
A6
66
151
145
181
288
181
Cyclone V SX
This section provides the available options, maximum resource counts, and package plan for the
Cyclone V SX devices.
The information in this section is correct at the time of publication. For the latest information and to get
more details, refer to the Altera Product Selector.
Related Information
Available Options
Figure 5: Sample Ordering Code and Available Options for Cyclone V SX Devices
The SEU internal scrubbing feature is available for Cyclone V E, GX, SE, and SX devices with the "SC"
suffix in the part number. For device availability and ordering, contact your local Altera sales
representatives.
5C
Package Type
F : FineLine BGA (FBGA)
U : Ultra FineLine BGA (UBGA)
Operating Temperature
C : Commercial (TJ = 0 C to 85 C)
I : Industrial (TJ = -40 C to 100 C)
A : Automotive (TJ = -40 C to 125 C)
Transceiver Count
C : 6
D : 9
SX
C6
31
Family Variant
SX : SoC with 3-Gbps transceivers
Member Code
C2 : 25K logic elements
C4 : 40K logic elements
C5 : 85K logic elements
C6 : 110K logic elements
Altera Corporation
Transceiver
Speed Grade
6 : 3.125 Gbps
Package Code
FBGA Package Type
31 : 896 pins
UBGA Package Type
23 : 672 pins
Optional Suffix
Indicates specific device
options or shipment method
N : Lead-free packaging
Contact Altera for availability
of leaded options
ES : Engineering sample
SC : Internal scrubbing support
FPGA Fabric
Speed Grade
6 (fastest)
7
8
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Maximum Resources
15
Maximum Resources
Table 12: Maximum Resource Counts for Cyclone V SX Devices
Member Code
Resource
C2
C4
C5
C6
25
40
85
110
ALM
9,434
15,094
32,075
41,509
Register
37,736
60,376
128,300
166,036
M10K
1,400
2,700
3,970
5,570
MLAB
138
231
480
621
36
84
87
112
18 x 18 Multiplier
72
168
174
224
FPGA PLL
HPS PLL
145
145
288
288
181
181
181
181
Transmitter
32
32
72
72
Receiver
37
37
72
72
2 (9)
2 (9)
Dual-core
Dual-core
Dual-core
Dual-core
Memory
(Kb)
3 Gbps Transceiver
FPGA GPIO
(8)
HPS I/O
LVDS
(8)
(9)
The number of GPIOs does not include transceiver I/Os. In the Quartus Prime software, the number of user
I/Os includes transceiver I/Os.
1 PCIe Hard IP Block in U672 package.
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Package Plan
Package Plan
Table 13: Package Plan for Cyclone V SX Devices
The HPS I/O counts are the number of I/Os in the HPS and does not correlate with the number of HPS-specific
I/O pins in the FPGA. Each HPS-specific pin in the FPGA may be mapped to several HPS I/Os.
Member
Code
U672
F896
(23 mm)
(31 mm)
FPGA GPIO
HPS I/O
XCVR
FPGA GPIO
HPS I/O
XCVR
C2
145
181
C4
145
181
C5
145
181
288
181
C6
145
181
288
181
Cyclone V ST
This section provides the available options, maximum resource counts, and package plan for the
Cyclone V ST devices.
The information in this section is correct at the time of publication. For the latest information and to get
more details, refer to the Altera Product Selector.
Related Information
Available Options
Figure 6: Sample Ordering Code and Available Options for Cyclone V ST Devices
Package Type
F : FineLine BGA (FBGA)
Embedded Hard IPs
F : 2 hard PCIe controllers
and 1 hard memory controller
Family Signature
5C : Cyclone V
5C
ST
Transceiver Count
D : 9
D6
Family Variant
ST : SoC with 6.144-Gbps transceivers
Member Code
D5 : 85K logic elements
D6 : 110K logic elements
Altera Corporation
Operating Temperature
I : Industrial (TJ= -40 C to 100 C)
31
Package Code
31 : 896 pins
Transceiver
Speed Grade
5 : 6.144 Gbps
FPGA Fabric
Speed Grade
7
Optional Suffix
Indicates specific device
options or shipment method
N : Lead-free packaging
Contact Altera for availability
of leaded options
ES : Engineering sample
CV-51001
2016.06.10
Maximum Resources
17
Maximum Resources
Table 14: Maximum Resource Counts for Cyclone V ST Devices
Member Code
Resource
D5
D6
85
110
ALM
32,075
41,509
Register
128,300
166,036
M10K
3,970
5,570
MLAB
480
621
87
112
18 x 18 Multiplier
174
224
FPGA PLL
HPS PLL
288
288
181
181
Transmitter
72
72
Receiver
72
72
Dual-core
Dual-core
Memory (Kb)
(10)
HPS I/O
LVDS
(10)
The number of GPIOs does not include transceiver I/Os. In the Quartus Prime software, the number of user
I/Os includes transceiver I/Os.
Altera Corporation
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Package Plan
Package Plan
Table 15: Package Plan for Cyclone V ST Devices
The HPS I/O counts are the number of I/Os in the HPS and does not correlate with the number of HPSspecific I/O pins in the FPGA. Each HPS-specific pin in the FPGA may be mapped to several HPS I/Os.
Transceiver counts shown are for transceiver 5 Gbps . 6 Gbps transceiver channel count support depends on
the package and channel usage. For more information about the 6 Gbps transceiver channel count, refer to the
Cyclone V Device Handbook Volume 2: Transceivers.
F896
(31 mm)
Member Code
FPGA GPIO
HPS I/O
XCVR
D5
288
181
9 (11)
D6
288
181
9 (11)
Related Information
(11)
If you require CPRI (at 4.9152 Gbps) and PCIe Gen2 transmit jitter compliance, Altera recommends that you
use only up to seven full-duplex transceiver channels for CPRI, and up to six full-duplex channels for PCIe
Gen2. The CMU channels are not considered full-duplex channels.
Altera Corporation
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19
Variant
Cyclone V E
Cyclone V GX
Cyclone V GT
Cyclone V SE
Cyclone V SX
Cyclone V ST
Member
Code
Package
M301
M383
M484
F256
U324
U484
F484
U672
F672
F896
F1152
A2
A4
A5
A7
A9
C3
C4
C5
C7
C9
D5
D7
D9
A2
A4
A5
A6
C2
C4
C5
C6
D5
D6
You can achieve the vertical migration shaded in red if you use only up to 175 GPIOs for the M383
package, and 138 GPIOs for the U672 package. These migration paths are not shown in the Quartus
Prime software Pin Migration View.
Note: To verify the pin migration compatibility, use the Pin Migration View window in the Quartus
Prime software Pin Planner.
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FPGA Device
1
2
3
4
5
6
7
8
Reg
Full
Adder
Reg
Adaptive
LUT
Reg
Full
Adder
Reg
You can configure up to 25% of the ALMs in the Cyclone V devices as distributed memory using MLABs.
Related Information
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Three 9 x 9
Two 18 x 18
You can configure each DSP block during compilation as independent three 9 x 9, two 18 x 18, or one
27 x 27 multipliers. With a dedicated 64 bit cascade bus, you can cascade multiple variable-precision DSP
blocks to implement even higher precision DSP functions efficiently.
Table 17: Number of Multipliers in Cyclone V Devices
The table lists the variable-precision DSP resources by bit precision for each Cyclone V device.
Independent Input and Output
Variant
Member
Code
Cyclone V E
Cyclone V
GX
DSP Block
Multiplications Operator
9x9
18 x 18
27 x 27
Multiplier
Multiplier
Multiplier
18 x 18
18 x 18
Multiplier
Adder
Mode
Multiplier Adder
Summed with
36 bit Input
A2
25
75
50
25
25
25
A4
66
198
132
66
66
66
A5
150
450
300
150
150
150
A7
156
468
312
156
156
156
A9
342
1,026
684
342
342
342
C3
57
171
114
57
57
57
C4
70
210
140
70
70
70
C5
150
450
300
150
150
150
C7
156
468
312
156
156
156
C9
342
1,026
684
342
342
342
Variableprecision
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Cyclone V
GT
Cyclone V
SE
Cyclone V
SX
Cyclone V
ST
Member
Code
Variableprecision
DSP Block
Multiplications Operator
9x9
18 x 18
27 x 27
Multiplier
Multiplier
Multiplier
18 x 18
18 x 18
Multiplier
Adder
Mode
Multiplier Adder
Summed with
36 bit Input
D5
150
450
300
150
150
150
D7
156
468
312
156
156
156
D9
342
1,026
684
342
342
342
A2
36
108
72
36
36
36
A4
84
252
168
84
84
84
A5
87
261
174
87
87
87
A6
112
336
224
112
112
112
C2
36
108
72
36
36
36
C4
84
252
168
84
84
84
C5
87
261
174
87
87
87
C6
112
336
224
112
112
112
D5
87
261
174
87
87
87
D6
112
336
224
112
112
112
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Variant
Cyclone V E
Cyclone V GX
Cyclone V GT
Cyclone V SE
Cyclone V SX
Cyclone V ST
M10K
MLAB
Member
Code
Block
Block
A2
176
1,760
314
196
1,956
A4
308
3,080
485
303
3,383
A5
446
4,460
679
424
4,884
A7
686
6,860
1338
836
7,696
A9
1,220
12,200
2748
1,717
13,917
C3
135
1,350
291
182
1,532
C4
250
2,500
678
424
2,924
C5
446
4,460
678
424
4,884
C7
686
6,860
1338
836
7,696
C9
1,220
12,200
2748
1,717
13,917
D5
446
4,460
679
424
4,884
D7
686
6,860
1338
836
7,696
D9
1,220
12,200
2748
1,717
13,917
A2
140
1,400
221
138
1,538
A4
270
2,700
370
231
2,460
A5
397
3,970
768
480
4,450
A6
557
5,570
994
621
5,761
C2
140
1,400
221
138
1,538
C4
270
2,700
370
231
2,460
C5
397
3,970
768
480
4,450
C6
557
5,570
994
621
5,761
D5
397
3,970
768
480
4,450
D6
557
5,570
994
621
5,761
Depth (bits)
Programmable Width
MLAB
32
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Memory Block
M10K
Depth (bits)
Programmable Width
256
x40 or x32
512
x20 or x16
1K
x10 or x8
2K
x5 or x4
4K
x2
8K
x1
Frequency synthesis
On-chip clock deskew
Jitter attenuation
Programmable output clock duty cycles
PLL cascading
Reference clock switchover
Programmable bandwidth
User-mode reconfiguration of PLLs
Low power mode for each fractional PLL
Dynamic phase shift
Direct, source synchronous, zero delay buffer, external feedback, and LVDS compensation modes
Fractional PLL
In addition to integer PLLs, the Cyclone V devices use a fractional PLL architecture. The devices have up
to eight PLLs, each with nine output counters. You can use the output counters to reduce PLL usage in
two ways:
Reduce the number of oscillators that are required on your board by using fractional PLLs
Reduce the number of clock pins that are used in the device by synthesizing multiple clock frequencies
from a single reference clock source
If you use the fractional PLL mode, you can use the PLLs for precision fractional-N frequency synthesis
removing the need for off-chip reference clock sources in your design.
The transceiver fractional PLLs that are not used by the transceiver I/Os can be used as general purpose
fractional PLLs by the FPGA fabric.
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FPGA Device
USB
I2C
Bridge
to PCIe
ATA
GbE
CAN
Local
Local
Peripheral 1 Peripheral 2
PCIe Link
PCIe EP
Root
Complex
PCIe RP
Memory
Controller
SPI
GPIO
Host CPU
The Cyclone V PCIe hard IP operates independently from the core logic. This independent operation
allows the PCIe link to wake up and complete link training in less than 100 ms while the Cyclone V device
completes loading the programming file for the rest of the device.
In addition, the PCIe hard IP in the Cyclone V device provides improved end-to-end datapath protection
using ECC.
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Voltage
(V)
Hard Controller
Soft Controller
1.5
400
303
303
1.35
400
303
303
DDR2 SDRAM
1.8
400
300
167
LPDDR2
SDRAM
1.2
333
300
167
Interface
DDR3 SDRAM
Related Information
Voltage (V)
1.5
400
1.35
400
DDR2 SDRAM
1.8
400
LPDDR2 SDRAM
1.2
333
DDR3 SDRAM
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27
Related Information
Transceiver Channels
The transceivers are positioned on the left outer edge of the device. The transceiver channels consist of the
physical medium attachment (PMA), physical coding sublayer (PCS), and clock networks.
Figure 10: Device Chip Overview for Cyclone V GX and GT Devices
The figure shows a Cyclone V FPGA with transceivers. Different Cyclone V devices may have a different
floorplans than the one shown here.
Clock Networks
Hard
Transceiver
PCS
PMA
Hard
Transceiver
PCS
PMA
Hard
Transceiver
PCS
PMA
Transceiver
Individual Channels
Fractional PLL
Fractional PLLs
I/O, LVDS, and Memory Interface
Fractional PLLs
Hard PCS Blocks
PCIe Hard IP Blocks
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PMA Features
PMA Features
To prevent core and I/O noise from coupling into the transceivers, the PMA block is isolated from the rest
of the chipensuring optimal signal integrity. For the transceivers, you can use the channel PLL of an
unused receiver PMA as an additional transmit PLL.
Table 22: PMA Features of the Transceivers in Cyclone V Devices
Features
Capability
Backplane support
Programmable deserialization
and word alignment
PCS Features
The Cyclone V core logic connects to the PCS through an 8, 10, 16, 20, 32, or 40 bit interface, depending
on the transceiver data rate and protocol. Cyclone V devices contain PCS hard IP to support PCIe Gen1
and Gen2, Gbps Ethernet (GbE), Serial RapidIO (SRIO), and Common Public Radio Interface (CPRI).
Most of the standard and proprietary protocols from 614 Mbps to 6.144 Gbps are supported.
Table 23: Transceiver PCS Features for Cyclone V Devices
PCS Support
Altera Corporation
Data Rates
(Gbps)
0.614 to 6.144
Word aligner
Deskew FIFO
Rate-match FIFO
8B/10B decoder
Byte deserializer
Byte ordering
Receiver phase compensa
tion FIFO
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PCS Features
PCS Support
Data Rates
(Gbps)
PCIe Gen1
(x1, x2, x4)
PCIe Gen2
(14)
(15)
1.25
XAUI (13)
3.125
3.75
1.25 to 3.125
0.27(14), 1.485,
and 2.97
JESD204A
0.3125(15) to
3.125
(13)
GbE
HiGig
(12)
29
PCIe Gen2 is supported for Cyclone V GT and ST devices. The PCIe Gen2 x4 support is PCIe-compatible.
XAUI is supported through the soft PCS.
The 0.27-Gbps data rate is supported using oversampling user logic that you must implement in the FPGA
fabric.
The 0.3125-Gbps data rate is supported using oversampling user logic that you must implement in the
FPGA fabric.
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PCS Support
Data Rates
(Gbps)
CPRI 4.1(16)
OBSAI RP3
V-by-One HS
DisplayPort 1.2
Up to 3.75
(17)
Dedicated deterministic
latency PHY IP core
Receiver (RX) determin
istic latency state machine
Custom PHY IP core
Wider spread of asynchro
nous SSC
HPS Features
The HPS consists of a dual-core ARM Cortex-A9 MPCore processor, a rich set of peripherals, and a
shared multiport SDRAM memory controller, as shown in the following figure.
(16)
(17)
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HPS-to-FPGA
Lightweight
HPS-to-FPGA
FPGA Fabric
FPGA
Manager
FPGA-to-HPS SDRAM
HPS
MPU Subsystem
Debug
Access Port
ETR
(Trace)
SD/MMC
Controller
Ethernet
MAC (2x)
Level 3
Interconnect
USB
OTG (2x)
NAND Flash
Controller
Multiport
DDR SDRAM
Controller
with
Optional ECC
DMA
Controller
STM
64 KB
Boot ROM
64 KB
On-Chip RAM
Peripherals
(UART, Timer, I C, Watchdog Timer, GPIO, SPI, Clock Manager, Reset Manager, Scan Manager, System Manager, and Quad
SPI Flash Controller)
2
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Related Information
Dynamic Reconfiguration
The dynamic reconfiguration feature allows you to dynamically change the transceiver data rates, PMA
settings, or protocols of a channel, without affecting data transfer on adjacent channels. This feature is
ideal for applications that require on-the-fly multiprotocol or multirate support. You can reconfigure the
PMA and PCS blocks with dynamic reconfiguration.
Partial Reconfiguration
Note: The partial reconfiguration feature is available for Cyclone V E, GX, SE, and SX devices with the
"SC" suffix in the part number. For device availability and ordering, contact your local Altera sales
representatives.
Partial reconfiguration allows you to reconfigure part of the device while other sections of the device
remain operational. This capability is important in systems with critical uptime requirements because it
allows you to make updates or adjust functionality without disrupting services.
Apart from lowering cost and power consumption, partial reconfiguration increases the effective logic
density of the device because placing device functions that do not operate simultaneously is not necessary.
Instead, you can store these functions in external memory and load them whenever the functions are
required. This capability reduces the size of the device because it allows multiple applications on a single
devicesaving the board space and reducing the power consumption.
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Altera simplifies the time-intensive task of partial reconfiguration by building this capability on top of the
proven incremental compile and design flow in the Quartus Prime design software. With the Altera
solution, you do not need to know all the intricate device architecture details to perform a partial reconfi
guration.
Partial reconfiguration is supported through the FPP x16 configuration interface. You can seamlessly use
partial reconfiguration in tandem with dynamic reconfiguration to enable simultaneous partial reconfigu
ration of both the device core and transceivers.
Data
Width
Max
Clock
Rate
(MHz)
AS through the
EPCS and EPCQ
serial configura
tion device
1 bit, 4
bits
100
PS through
CPLD or
external
microcontroller
1 bit
125
8 bits
FPP
CvP (PCIe)
JTAG
Design
Security
Partial
Reconfigu
ration(18)
Remote System
Update
Yes
Yes
Yes
125
Yes
Yes
125
Yes
Yes
16 bits
125
Yes
Yes
Yes
x1, x2,
and x4
lanes
Yes
Yes
Yes
1 bit
33
33
Instead of using an external flash or ROM, you can configure the Cyclone V devices through PCIe using
CvP. The CvP mode offers the fastest configuration rate and flexibility with the easy-to-use PCIe hard IP
block interface. The Cyclone V CvP implementation conforms to the PCIe 100 ms power-up-to-active
time requirement.
Related Information
The partial reconfiguration feature is available for Cyclone V E, GX, SE, and SX devices with the "SC" suffix
in the part number. For device availability and ordering, contact your local Altera sales representatives.
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Power Management
35
Power Management
Leveraging the FPGA architectural features, process technology advancements, and transceivers that are
designed for power efficiency, the Cyclone V devices consume less power than previous generation
Cyclone FPGAs:
Total device core power consumptionless by up to 40%.
Transceiver channel power consumptionless by up to 50%.
Additionally, Cyclone V devices contain several hard IP blocks that reduce logic resources and deliver
substantial power savings of up to 25% less power than equivalent soft implementations.
Version
Changes
June 2016
2016.06.10
December
2015
2015.12.21
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Date
June 2015
Version
2015.06.12
Changes
March 2015
2015.03.31
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Date
Version
January 2015
2015.01.23
37
Changes
October 2014
2014.10.06
July 2014
2014.07.07
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Date
December
2013
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Version
2013.12.26
Changes
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2016.06.10
Date
May 2013
Version
2013.05.06
39
Changes
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Date
Version
Changes
2012.12.28
November
2012
2012.11.19
July 2012
2.1
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Date
Version
41
Changes
June 2012
2.0
February 2012
1.2
November
2011
1.1
Updated Table 11, Table 12, Table 13, Table 14, Table 15, and
Table 16.
Updated Figure 14, Figure 15, Figure 16, Figure 17, and Figure
18.
Updated System Peripherals on page 118, HPSFPGA AXI
Bridges on page 119, HPS SDRAM Controller Subsystem on page
119, FPGA Configuration and Processor Booting on page 119,
and Hardware and Software Development on page 120.
Minor text edits.
October 2011
1.0
Initial release.
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