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COMMUNICATIONS
ABSTRACT:
The direct digital synthesis (DDS) technique has become more and more
popular in the mobile communication arena due to the simple control procedure rather than an
analog domain phase locked loop (PLL) based signal synthesis. The front end D/A converter
(DAC) is a critical component in those systems. In high speed data links e.g. optical, radar or
satellite communication systems, medium resolution (4-8 Bits) DAC with sampling rate of
10MHz to 20 GHz and above are going to be used.
The existing method consists of Binary Weighted Resistors. This architecture
utilizes summing up op-amp circuit. Weighted resistors are used to distinguish each bit from the
most significant to the least significant and transistors are used to switch between V
ref
and
ground (bit high or low). This method is of simple construction and fast conversion but requires
large range of resistors with necessary high precision for low resistors. It is expensive and
limited to 8-bit resolution.
Hence, in this study a 6- bit low power, medium resolution DAC is designed for
high speed ultra wideband communication systems. The components used are switches,
Operational amplifier, R-2R ladder and then followed by a low pass filter to smoothen the
staircase signal. Moreover, the proposed design uses only two resistor values (R and 2R) and
does not require high precision resistors. It is easy to implement and manufacture.
: 180nm
K.Naga Kanya,
Professor
(12JG1D6802)
Department of ECE,