Graduate Research Assistant opening for PhD aspirants in Advanced Electronics

of Nano-Devices (AEON) Lab from Fall 2017 at Department of Electrical and

Computer Engineering (ECE) at University of Illinois at Chicago (UIC)

About University of Illinois at Chicago (UIC): The University of Illinois at Chicago is a public research university
located near downtown Chicago, Illinois, United States. UIC operates the largest medical school in the United
States, and serves as the principal educator for Illinois physicians, dentists, pharmacists, physical therapists,
nurses and other healthcare professionals. College of Engineering at UIC is relatively new, established in 1946.
UIC offers unique opportunities to pursue interdisciplinary research works, especially in the areas of bio-medical
applications. Location of UIC in downtown Chiacgo also offers distinct advantages for research collaboration
with industries and other universities in the area. Department of Electrical and Computer Engineering has about
30 faculty, over 450 undergraduate and over 200 graduate students. In 2014, Times Higher Education 100 Under
50 University Rankings (a comparison of universities less than 50 years old) placed UIC in the 3rd position in the
U.S. and 13th in the world.

Advanced Electronics of Nano-devices (AEON) Lab

Link: http://aeon.lab.uic.edu/index.html
AEON Lab is directed by Prof. Amit Ranjan Trivedi at the Department of Electrical and Computer Engineering.
Research thrust of the lab is in utilizing nanoscaled conventional CMOS and emerging technologies for ultralow
power (digital and analog) computing and sensing. The lab pursues innovations by bridging novel aspects of
physics of computing devices and mathematics of computing models and circuits. The lab will host state-of-theart large scale analog and digital circuit design/measurement equipment. Active collaborations are pursued
with the other faculties at UIC and Argonne National Laboratory to pursue novel nanoscaled device
fabrication/characterization while also focusing on large scale circuit and system design aspects.

Bio of the Lab Director:

Amit completed his undergraduate and graduate degree from Indian Institute of
Technology (IIT), Kanpur in 2008. Amit was awarded academic excellence award
from the institute for his standing in top 5% of his peers. Following this, he was a
research staff member at IBM Semiconductor Research and Development Center,
where he was involved in compact modeling and characterization of advanced
nanometer node transistors/processes. Since, Fall 2010, Amit pursued Ph.D. at the
Department of Electrical and Computer Engineering in Georgia Institute of
Technology. His research has been in low power energy-efficient neuromorphic
computing with emerging technologies, and particularly, with Tunneling fieldeffect-transistors. He has published more than 25 journals and major conferences during his PhD studies. Amit
was awarded IEEE Electron Device Society fellowship in 2014, where he was one of the three recipients
worldwide, and only one in Americas. Amit was also awarded Sigma Xi Best PhD Dissertation from Georgia
Tech. Amit was a research intern at IBM T J Watson research center in summer of 2012, and Intels Circuit
research lab in summer of 2014. Amit joined UIC as tenured track assistant professor in October 2015.
Gallery of Major Past Research Projects:

11

12

13

14

15

(d)
514

21

Image pixel
mapped to Tunnel
FET-CNN cell(f)
TBT region pinch-off

22

23

24

25

31

32

33

34

35

41

42

43

44

45

51

52

53

54

55

VGS = 2V

Gate induced depletion region

3.81032

Hole BTBT
generation
rate [/cm3/s]

2.51028
1.71024

Hole B

VP11

(e)

VP11

VPm1

BTBT region pinch-off

VP12

VP12

VPm2

VP1n

VP1n

VPmn

gener
Ultralow power
rate [/c
neuromorphic
(f)computing
Within source BTBT
at gate edge
with
emerging
technologies

1.11020
7.51015

Within source BTBT at gate edge

VGS = 2V

Channel

Source

514

VGS = 0.8V

BTBT region

Analog Image Input

VGS = 0.45V

Winner Take All

A. Trivedi et al. Potential of SiGe Tunneling Nanowires for Ultra-low Power Image Processing, IEEE Transaction of Nanotechnology, 2014.
A. Trivedi et al. Application of Silicon-Germanium Source Tunnel-FET to Enable Ultralow Power Cellular Neural Network-Based Associative
Memory, IEEE Transaction of Electron Devices, 2014.
A. Trivedi et al. Negative Gate Transconductance in Gate/Source Overlapped Heterojunction Tunnel FET and application to Single Transistor
Phase Encoder, IEEE Electron Device Letters, 2015.
A. Trivedi et al. Area efficient pattern matching network based on delta shaped characteristics of gate/source overlapped heterojunction
Tunnel FET, to be submitted to IEEE Transactions of Electron Devices, 2015.

Emerging variability
sources in nanoscaled
technologies

A.Trivedi et al. A Simulation study of Oxygen vacancy induced variability in high-k/metal-gate SOI FinFET, IEEE Transaction of Electron Devices,
vol. 61, no. 5, May 2014.

Blocked idle patterns due

to excessive overheads
Output PG patterns

SPI
Inverter
chain with
embedded
heaters
PGE
Learner

LVT

RVT

LVT

RVT

Centralized
calibration
unit

PG gen

PG signal
generator

Learning cycles
Learn

Adapt

Input idle patterns

Circuit techniques
for minimal
wasted power in
computing

A.Trivedi et al. In-site Power Gating Efficiency Learner for Self Adaptive Power Gating, IEEE Transaction of Circuits and Systems II, vol. 61, no.
5, May 2014.
A.Trivedi et al., Self-Adaptive Power Gating with Test Circuit for On-line Characterization of Energy Inflection Activity," IEEE VLSI Test
Symposium, 2012.

Future Research Vision:

The first task that we take at NCSL is towards enabling
Logic
Creativity
large scale and low power neuromorphic computing.
Neuromorphic computing is a set of computing
Memory
Visualization
paradigms which are inspired by the functioning of
Sequencing
Intuition
biological brain. Neuromorphic computing follows a
profoundly different approach in handling some of the
Mathematics
Imagination
critical (and increasingly prevalent) computing steps
e.g. in (supervised/unsupervised) learning and in
Neuromorphic
extracting information from vast amount of data. And,
computing unit?
the computing attempts to bring in a brain like
intelligence in electronics. Particularly, neuromorphic Pursuit of a holistic
computing at lower power can unlock opportunities computing at NCSL
to make our mobile and embedded electronics by integrating
smarter and more interactive with their user, and neuromorphic and
therefore significantly improve quality of our lives. conventional
Primary approach in our lab to explore higher energy- computing
efficiency and reliability in neuromorphic computing is
through a cohesive design of neuromorphic computing circuits/paradigm and computing devices. The lab will
be interested to pursue an integrated system comprising conventional and neuromorphic computing. Such an
integrated system operates a given computation step on the most suitable computing core, conventional or
neuromorphic, for energy efficiency. We are also interested in following a fresh perspective in the development
of neuromorphic computing. Following an alternate computing with physics approach we seamlessly bridge
physics of computing devices and mathematics of computing paradigm to develop highly energy-efficient
systems. Exploiting current state of nanotechnology, we are also interested in exploring self-assembled array of
nanostructures, such as quantum dots and nanowires, for an ultra large scale neuromorphic computing.
How to apply: I am looking for enthusiastic and creative minds for my Advanced Electronics of Nano-devices
Lab. If you have passion for state-of-the-art technologies, craving to make a dent in the research world,
attention to details, and ability to work hard, please get in touch with me. I especially welcome students with
background and experience in device physics and low power analog/digital circuits. Please send me your
detailed resume at: amitrt@uic.edu. Please also submit your admission application at UIC, Department of
Electrical and Computer Engineering.