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Documente Cultură
1 Rangkaian Kombinasi
2.3.1.1 Tabel Kebenaran Rangkaian Kombinasi
Tabel 2.1 Rangkaian Kombinasi
Input
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Outpu
t
Y
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
BABIIkombinasi.xis
Parser Errors:
e
No Errors
Module
Name:
BabIIkombinasi
Implementation State:
Programming
File Generated
Target
Device:
xc3s500e-4fg320
Errors:
No Errors
Product
Version:
ISE 13.2
Warnings:
No Warnings
Routing Results:
All Signals
Completely
Routed
Design
Strategy:
Timing
Constraints:
Xilinx Default
(unlocked)
Environment
System Settings
:
Final Timing
Score:
0 (Timing
Report)
[-]
9,312
1%
4,656
1%
100%
0%
9,312
1%
232
2%
1.00
Performance Summary
[-]
Final Timing
Score:
0 (Setup: 0, Hold: 0)
Pinout
Data:
Pinout Report
Routing Results:
Clock
Data:
Clock Report
Timing
Constraints:
Detailed Reports
[-]
Report Name
Status Generated
Error Warning
Infos
s
s
Synthesis Report
Translation Report
Map Report
2 Infos (0
new)
1 Info (0 new)
Post-PAR Static
Timing Report
5 Infos (0
new)
Bitgen Report
Power Report
Secondary Reports
Report Name
Status
Generated
Current
WebTalk Report
Current
Current
[-]
2.3.2 Multiplekser
2.3.2.1 Tabel Kebenaran Multiplekser
Tabel 2.2 Tabel Kebenaran Multiplekser
Input
S0
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
A
0
1
0
0
0
0
0
0
B
0
0
0
1
0
0
0
0
C
0
0
0
0
0
1
0
0
D
0
0
0
0
0
0
0
1
Output
Y
0
1
0
1
0
1
0
1
begin
Y <= ( A and B ( not S0) and ( not S1) ) or ( B and s1 and ( not S0 )) or ( C and S0
and ( not S1)) or ( D and S0 and S1 );
end Behavioral;
babmultiplekserII.xis
Parser Errors:
e
No Errors
Module
Name:
Multiplekser
Implementation State:
Placed and
Routed
Target
Device:
xc3s500e-4fg320
Errors:
No Errors
Product
Version:
ISE 13.2
Warnings:
No Warnings
Routing Results:
All Signals
Completely
Routed
Design
Strategy:
Timing
Constraints:
Xilinx Default
(unlocked)
Final Timing
Score:
0 (Timing
Report)
[-]
Logic Utilization
Number of 4 input LUTs
9,312
1%
4,656
1%
100%
0%
9,312
1%
232
3%
1.14
Performance Summary
[-]
Final Timing
Score:
0 (Setup: 0, Hold: 0)
Pinout
Data:
Pinout Report
Routing Results:
Clock
Data:
Clock Report
Timing
Constraints:
Detailed Reports
[-]
Report Name
Status
Generated
Error Warning
Infos
s
s
Synthesis Report
Current
Sat Oct 24
16:15:30 2015
Sat Oct 24
16:16:27 2015
Map Report
Current
Sat Oct 24
16:16:33 2015
2 Infos (0
new)
Current
Sat Oct 24
1 Info (0 new)
Report
16:16:47 2015
Power Report
Post-PAR Static
Timing Report
Current
Sat Oct 24
16:16:53 2015
5 Infos (0
new)
Bitgen Report
Out of
Date
Sat Oct 24
13:57:40 2015
Secondary Reports
[-]
Report Name
Status
Generated
Current
WebTalk Report
Out of Date
Out of Date
2.3.3 Demultiplekser
2.3.3.1 Tabel Kebenaran Demultiplexer
Tabel 2.3 Tabel Kebenaran Demultiplexer
S0
0
0
0
0
1
1
1
1
Input
S1
0
0
1
1
0
0
1
1
Output
Z
0
1
0
1
0
1
0
1
A
0
1
0
0
0
0
0
0
B
0
0
0
1
0
0
0
0
C
0
0
0
0
0
1
0
0
D
0
0
0
0
0
0
0
1
begin
A <= Z and ( not S0 ) and ( not S1 );
B <= Z and S1 and ( not S0 );
C <= Z and S) and ( not S1 );
D <= Z and S0 and S1;
end Behavioral;
DemultiplexerBABII.xis
Parser Errors:
e
No Errors
Module
Name:
DemultiplexerBABII
Implementation State:
Placed and
Routed
Target
Device:
xc3s500e-4fg320
Errors:
No Errors
Product
Version:
ISE 13.2
Warnings:
No Warnings
All Signals
Routing Results: Completely
Routed
Design
Strategy:
Timing
Constraints:
Xilinx Default
(unlocked)
Final Timing
0 (Timing
Report)
Score:
[-]
Logic Utilization
Number of 4 input LUTs
9,312
1%
4,656
1%
100%
0%
9,312
1%
232
3%
2.29
Performance Summary
[-]
Final Timing
Score:
0 (Setup: 0, Hold: 0)
Pinout
Data:
Pinout Report
Routing Results:
Clock
Data:
Clock Report
Timing
Constraints:
Detailed Reports
[-]
Report Name
Status Generated
Error Warning
Infos
s
s
Synthesis Report
Translation Report
Map Report
2 Infos (0
new)
1 Info (0 new)
5 Infos (0
new)
Power Report
Post-PAR Static
Timing Report
Bitgen Report
Secondary Reports
[-]
Report Name
Status
Generated
Current
2.3.4.Dekoder 3 to 8
2.3.4.1 Tabel Kebenaran Dekoder 3 to 8
Tabel 2.4 Tabel Kebenaran Dekoder 3 to 8
Input
A
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Q
0
1
0
0
0
0
0
0
Q1
0
1
0
0
0
0
0
Q
2
0
0
1
0
0
0
0
Output
Q
Q
3
4
0
0
0
0
0
0
1
0
0
1
0
0
0
0
Q5
Q6
Q7
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Q3 : out STD_LOGIC;
Q4 : out STD_LOGIC;
Q5 : out STD_LOGIC;
Q6 : out STD_LOGIC;
Q7 : out STD_LOGIC);
end dekoder3to8;
architecture Behavioral of dekoder3to8 is
begin
Q0 <= ( not A ) and ( not B ) and ( not C );
Q1 <= ( not A ) and ( not B ) and C ;
Q2 <= ( not A ) and B and ( not C );
Q3 <= ( not A ) and B and C;
Q4 <= A and ( not B ) and ( not C );
Q5 <= A and ( not B ) and C;
Q6 <= A and B and 9 not C );
Q7 <= A and B and C;
end Behavioral;
Dekoder3to8.xise
Parser Errors:
No Errors
Module
Name:
Dekoder3to8
Implementation State:
Placed and
Routed
Target
Device:
xc3s500e-4fg320
Errors:
No Errors
Product
Version:
ISE 13.2
Warnings:
No Warnings
Design Goal:
Balanced
Routing Results:
All Signals
Completely
Routed
Design
Strategy:
Xilinx Default
(unlocked)
Timing
Constraints:
Final Timing
0 (Timing
Report)
Score:
[-]
Logic Utilization
Number of 4 input LUTs
9,312
1%
4,656
1%
100%
0%
9,312
1%
11
232
4%
2.91
Performance Summary
[-]
Final Timing
Score:
0 (Setup: 0, Hold: 0)
Pinout
Data:
Pinout Report
Routing Results:
Clock
Data:
Clock Report
Timing
Constraints:
Detailed Reports
[-]
Report Name
Status Generated
Error Warning
Infos
s
s
Synthesis Report
Translation Report
Map Report
2 Infos (2
new)
1 Info (1 new)
5 Infos (5
new)
Power Report
Post-PAR Static
Timing Report
Bitgen Report
Secondary Reports
Report Name
Status
Generated
Current
[-]