Chengzhou Wang

UNIVERSITY OF CALIFORNIA, SAN DIEGO
CMOS Power Amplifiers for Wireless Communications
A dissertation submitted in partial satisfaction of the

requirements for the degree Doctor of Philosophy
in
Electrical Engineering (Electronic Circuits & Systems)
by
Chengzhou Wang
Committee in charge:
Professor Lawrence E. Larson, Chair
Professor Peter M. Asbeck
Professor Walter H. Ku
Professor Chung-Kuan Cheng
Professor Bill Hodgkiss
2003
Copyright
Chengzhou Wang, 2003
All rights reserved.
The dissertation of Chengzhou Wang is approved, and it is

acceptable in quality and form for publication on microfilm:
Chair
University of California, San Diego
2003
iii
To my parents and sisters
iv
TABLE OF CONTENTS
Signature Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

Dedication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii
Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
Vita, Publications, and Fields of Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvi
I
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I.1.1 Power Amplifiers in Wireless Communication Systems . . . . . . . . . . .
I.1.2 Power Amplifier Classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I.2 Limitations of Sub-micron CMOS Technology . . . . . . . . . . . . . . . . . . . . . . . .
I.2.1 Low Breakdown Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I.2.2 Low Transconductance-to-current Ratio . . . . . . . . . . . . . . . . . . . . . . .
I.2.3 Low Substrate Resistivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I.3 Dissertation Motivations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I.4 Dissertation Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1
1
3
4
4
5
6
6
7
II
Class-E Power Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

II.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
II.2 Improved Class-E Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
II.2.1 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
II.2.2 Circuit Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
II.2.3 Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
II.2.4 Component Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
II.3 A Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
II.4 Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
9
11
11
13
15
18
19
22
II.4.1 Validity of Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

II.4.2 Choice of Device Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
II.4.3 Relationship between Pout and VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . .
II.4.4 Comparison with Previous Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
II.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
III
22
25
26
27
29
Linear CMOS Class-AB Power Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

III.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
III.2 Distortion Effects of the Gate-Source Capacitance . . . . . . . . . . . . . . . . . . . . . 31
III.2.1 Simplified Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
III.2.2 Capacitance Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
III.2.3 Impact on Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
III.3 Compensation Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
III.3.1 Basic Idea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
III.3.2 Volterra Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
III.4 Schematic Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
III.4.1 Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
III.4.2 Driver Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
III.4.3 Strategy for Ground Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
III.4.4 Final PA Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
III.5 Layout Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
III.5.1 IBM SiGe5AM Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
III.5.2 Basic Transistor Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
III.5.3 On-chip Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
III.5.4 Current Handling Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
III.5.5 Substrate Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
III.5.6 Final PA layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
III.6 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
III.6.1 Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
III.6.2 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
III.6.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
III.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
IV Dynamic Biasing Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

IV.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
IV.2 Dynamic biasing Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
vi
IV.3
IV.4
IV.5
IV.6
V
IV.2.1 Basic concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

IV.2.2 Response of Envelope Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Efficiency Improvement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
IV.3.1 Drain Efficiency for Single-tone Input . . . . . . . . . . . . . . . . . . . . . . . . . 117
IV.3.2 Average Efficiency for Varying-envelope Signals . . . . . . . . . . . . . . . . 120
Distortion Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
IV.4.1 IM3 Expression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
IV.4.2 Estimation of g2 and g3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
IV.4.3 Final IM3 Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
IV.5.1 IC Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
IV.5.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vii
LIST OF FIGURES
II.1
II.2
II.3
II.4
II.5
III.1
III.2
III.3
III.4
III.5
III.6
III.7
III.8
III.9
III.10
III.11
III.12
III.13
III.14
III.15
Schematic and improved model of CMOS class-E power amplifier. . . . . . . .

Comparison of the current and voltage waveforms between the calculation
and simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output power and the drain efficiency versus NMOS width. . . . . . . . . . . . . .
Simplified NMOS small-signal model in triode region and cut-off region. .
Simulated output power and drain efficiency versus NMOS width for the
design approaches developed by Ewing, Sokal, Li, and this work. . . . . . . . .
12
Simplified models of CMOS class-AB power amplifiers. . . . . . . . . . . . . . . . .

Plots of the simulated NMOS device capacitances as a function of gatesource voltage, for a fixed drain-source voltage of 3.3 V. . . . . . . . . . . . . . . . .
Simplified schematics of class-AB amplifiers used to illustrate the impact
of the gate-source capacitance on linearity. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Third-order, intermodulation distortion at 21 2 versus peak-envelope
output power, at various gate bias voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Third-order, intermodulation distortion at 21 2 versus peak-envelope
output power, at various gate bias voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Plots of the device capacitances of a PMOS transistor as a function of its
gate-source voltage, with its drain-source voltage held at zero. . . . . . . . . . . .
Plots of simulated Cggn , Cggp , and the sum Cggn + Cggp for the NMOS and
PMOS devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPECTRE simulated and MATLAB fitted curves for (a) Ceff and (b) idsn
as functions of the NMOS gate-source voltage. . . . . . . . . . . . . . . . . . . . . . . . .
Nonlinear capacitor circuit for Volterra analysis. . . . . . . . . . . . . . . . . . . . . . . .
Simplified nonlinear model of the PA output stage. . . . . . . . . . . . . . . . . . . . .
Circuit for the Volterra calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calculated contributions to the drain IM3 from the Ceff and idsn nonlinearities for both the basic and linearized amplifiers. . . . . . . . . . . . . . . . . . . . . . . .
Simplified block diagram of designed two-stage CMOS class-AB power
amplifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schematic and simplified model of the output stage for the first-order analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Load line of the output stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
viii
21
22
24
28
33
35
37
38
39
41
45
46
49
50
53
54
56
56
III.16 Plots of Id versus VGS for an ideal class-B operation, and a short-channel
device biased near the threshold voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
III.17 Schematic and equivalent circuit of a high-pass, L-match network . . . . . . . .
III.18 Cascade of two lossy L-match networks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
III.19 Output matching networks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
III.20 Circuit and equivalent model of the interstage matching network. . . . . . . . .
III.21 Schematic and linear model of the two-stage CMOS class-AB power amplifier for illustrating ground connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
III.22 Two-stage CMOS class-AB PAs for illustrating the impact of ground connections on gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
III.23 Power gain of the two-stage CMOS class-AB power amplifiers versus total ground bondwire inductance for the two ground configurations shown
in Fig. III.22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
III.24 Two-stage CMOS class-AB power amplifier for one-chip-ground and twochip-ground configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
III.25 Small-signal equivalent model of the two-stage CMOS class-AB power
amplifier for one-chip-ground and two-chip-ground configurations. . . . . . . .
III.26 Maximum stable ground bondwire inductance of the two-stage CMOS
class-AB PA for the ground configurations in Table III.2. . . . . . . . . . . . . . . .
III.27 Schematic of the fully matched two-stage CMOS class-AB power amplifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
III.28 Layout of a basic transistor cell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
III.29 Schematic modelling and sideview of device layouts regarding the effect
of substrate coupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
III.30 Layout structure employing both large substrate guardrings and deep trench
blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
III.31 Final Layout of the fully integrated and compensated two-stage CMOS
PA (PA2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
III.32 Die microphotograph of the fully integrated and compensated two-stage
CMOS PA (PA2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
III.33 Photograph and cross section drawing of the MLF package. . . . . . . . . . . . . .
III.34 Output and input off-chip matching network for PA3. . . . . . . . . . . . . . . . . . .
III.35 ADS schematic and simulated impedance of off-chip output matching network for PA3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
III.36 Application schematic of PA3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ix
58
61
63
64
67
71
73
74
76
77
80
81
84
87
88
89
90
91
93
95
97
III.37 Photograph of the PCB implementation of PA3. . . . . . . . . . . . . . . . . . . . . . . . 97

III.38 Test setup for evaluating the PAs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
III.39 Measured gain and power-added efficiency versus output power of the
three PAs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
III.40 Simulated and measured gain and power-added efficiency versus output
power for the three PAs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
III.41 Measured IM3 , adjacent-channel leakage power, and alternate-channel
power versus peak-envelope output power for the three PAs. . . . . . . . . . . . . . 102
III.42 Measured WCDMA spectra of PA1 and PA2 at a carrier output power of
nearly 20 dBm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
IV.1
IV.2
IV.3
IV.4
IV.5
IV.6
IV.7
IV.8
IV.9
IV.10
IV.11
IV.12
IV.13
IV.14
Conceptual block diagram and actual implementation of the dynamic biasing technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Schematic and equivalent large-signal model of the envelope detection
and gate-bias-control circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Source-drain current of Mp as a function of time. . . . . . . . . . . . . . . . . . . . . . . 111
SPECTRE simulated and MATLAB fitted PMOS source-drain current versus gate voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Schematic of the designed two-stage CMOS power amplifier. . . . . . . . . . . . 115
Approximate time-domain waveforms of the input gate voltage, sourcedrain current of Mp , and output voltage of the envelope detector for a
two-tone test signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Circuit for the Volterra calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
IDS versus VGS for a long-channel class-A device and an ideal class-B device.126
Ratio of g2 and g3 to g1 for the four gate bias voltages (0.75 - 0.90 V) of
the implemented class-AB device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Comparison of the calculated and simulated IM3 of the load voltage at
21 2 versus peak-envelope output power. . . . . . . . . . . . . . . . . . . . . . . . . . 129
Contributions to the load-voltage IM3 from the g2 , g3 , and Ceff nonlinearities.130
Die microphotograph of the highly integrated and compensated two-stage
CMOS PA (PA3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Calculated, simulated, and measured Venv versus output power for a singletone input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Measured gain and power-added efficiency versus output power for PA3
with the dynamic biasing technique, and PA3 when the envelope detector
is disabled and the gate is biased at VGG0 = 0.85 V, respectively. . . . . . . . . . 133
IV.15 Measured power consumption improvement versus the PA output power. . . 134
IV.16 Measured IM3 , adjacent-channel leakage power, and alternate-channel
power versus peak-envelope output power for the three PAs. . . . . . . . . . . . . . 135
IV.17 Comparison between the calculated and measured load-voltage IM3 versus output power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
xi
LIST OF TABLES
I.1
I.2
II.1
II.2
III.1
III.2
III.3
III.4
III.5
Characteristics of digital wireless systems relevant to power amplifier performance in mobile station [1]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Comparison of efficiency and linearity for different classes of power amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
4
Comparison of Pout and Peff between theoretical prediction and HSPICE

simulation for the designed CMOS class-E power amplifier. . . . . . . . . . . . . . 20
Assumptions for the analysis by Ewing, Sokal, Li, and this work. . . . . . . . . 27
Estimated model parameters of driver and output stages. . . . . . . . . . . . . . . . . 69
Ground configurations for the two-stage CMOS class-AB PAs in Fig. III.24. 78
Properties of metal layers in IBM SiGe5AM technology. . . . . . . . . . . . . . . . 83
Comparison between maximum allowable layout currents and corresponding maximum designed currents of all critical components in PA2. . . . . . . . 86
Performance comparison of recently reported linear power amplifiers for
handset applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
xii
ACKNOWLEDGEMENTS
Pursuing the doctoral degree begins with a great deal of excitement and expectations.
However, after years of endeavors, the initial love and devotions to the research topic gradually become frustrations by the overwhelming obstacle and adversity, and I start to realize
that this journey would never be fulfilled without the support of many people.
First and foremost, I would like to express my sincere gratitude and appreciation to
my advisor Professor Lawrence E. Larson. Without his continuous guidance and encouragement, my research work towards this thesis would never be possible. I would also like
to thank Professor Peter M. Asbeck for his assistance throughout the years, as his knowledge and experience were also valuable. Furthermore, I am indebted to Professor Walter
H. Ku, Professor Chung-Kuan Cheng, and Professor Bill Hodgkiss, for their patience and
efforts of being my dissertation committee.
This work has benefited from the contributions of many other individuals. Special
thanks to Mani Vaidyanathan and Liwei Sheng for their invaluable suggestions and ideas
to my research projects. I would also like to thank John Fairbanks, Matt Wetzel, Jonathan
Jensen, and Masaya Iwamoto for their assiduous assistance in solving the laboratory and
CAD problems I experienced. In addition, Xuejun Zhang, Junxiong Deng, Vincent Leung,
Don Kimball, Robert Wang and other brilliant colleagues deserve my sincere thanks for
their enthusiastic help and encouragement.
Finally, I am grateful to my family (my parents and my sisters Judy and Fang) and
my dear friends Changchun Shi, Yong Wang, Wei Lin, Jian Ma and others. Without their
xiii
continuous support, this Ph.D work would have been much more difficult.
This research was supported by the UCSD Center for Wireless Communications and
its member companies. Their supports are greatly acknowledged.
xiv
VITA
1992-1997
B.S., Electronics, Beijing University, China
1997-1999
M.S., Electrical Engineering (Electronic Circuits & Systems),

University of California, San Diego, United States
1999-2003
Ph.D., Electrical Engineering (Electronic Circuits & Systems), University of California, San Diego, United States
PUBLICATIONS
C. Wang and L.E. Larson, Analysis of a Microwave CMOS Class-E Power Amplifier
with Finite Switching On-resistance, 1999 IEEE Topical Workshop on Power Amplifier
for Wireless Communications, La Jolla, CA, Sept. 1999.
C. Wang and L.E. Larson, Highly Integrated Linear Class-AB CMOS Power Amplifier
with Nonlinear Capacitor Compensation, 1999 IEEE Topical Workshop on Power Amplifier for Wireless Communications, La Jolla, CA, Sept. 2000.
C. Wang, L.E. Larson, and P.M. Asbeck, A Nonlinear Capacitance Cancellation Technique
and its Application to a CMOS Class-AB Power Amplifier, presented at 2001 IEEE International Microwave Symposium (RFIC), Phoenix, AZ, May 2001.
C. Wang, L.E. Larson, and P.M. Asbeck, Improved Design Technique of a Microwave
Class-E Power Amplifier with Finite Switching On-Resistance, presented at 2002 IEEE
Radio and Wireless Conference, Boston, MA, Aug 2002.
C. Wang, M. Vaidyanathan and L.E. Larson, A Capacitance-Compensation Technique for
Improved Linearity in CMOS Class-AB Power Amplifiers, submitted to IEEE Journal of
Solid-State Circuits.
C. Wang, and L.E. Larson, A Dynamic Biasing Technique for Efficiency Improvement in
CMOS Class-AB Power Amplifiers , in preparation to IEEE Transactions on Microwave
Theory and Techniques.
FIELDS OF STUDY
Major Field: Electrical and Computer Engineering
Studies in Radio Frequency Integrated Circuit Design.
Professor Lawrence E. Larson
xv
ABSTRACT OF THE DISSERTATION
CMOS Power Amplifiers for Wireless Communications
by
Chengzhou Wang
Doctor of Philosophy in Electrical Engineering (Electronic Circuits & Systems)
University of California, San Diego, 2003
Professor Lawrence E. Larson, Chair
Linearity and efficiency are the two most important characteristics of power amplifiers (PAs) for wireless applications. In this dissertation, we investigate three topics on
CMOS power amplifiers: class-E, class-AB, and dynamic biasing technique.
Previous analytical efforts on class-E power amplifiers assumed either zero switch
resistance and/or infinite drain inductance, leading to less optimized design. In this dissertation, we developed an improved design technique by accounting for both finite drain
inductance and finite on resistance for a CMOS device. A design example based on the
developed algorithm achieves an output power of 0.25 W and a drain efficiency of 87% for
a 3.5 mm NMOS class-E device with VDD = 2 V and fc = 1.90 GHz.
The intrinsic linearity obtained in a CMOS class-AB operation is often insufficient
to meet the stringent linearity requirement imposed by modern wireless standards. In this
dissertation, we propose a capacitance compensation technique to improve PA linearity.
xvi
Experiments show that the compensation technique can improve both the two-tone, thirdorder intermodulation (IM3 ) and adjacent-channel leakage power (ACP) by approximately
8 dB. While meeting the 3GPP-WCDMA ACP requirements, the linearized two-stage amplifier is capable of delivering an output power of 24 dBm with a small-signal gain of nearly
24 dB and an overall power-added efficiency of 29 %.
The designed two-stage CMOS class-AB power amplifier suffers serious efficiency
degradation when operated at low output power levels. In this dissertation, it was demonstrated that a dynamic biasing technique can improve the average efficiency of a CMOS
class-AB power amplifier by controlling the gate bias voltage with the envelope of input
RF signal. However, the envelope signal introduced by the dynamic biasing technique can
significantly limit the overall linearity of the CMOS class-AB PA. Both analysis and experiments show that the dynamic biasing technique can significantly degrade the IM3 and
ACP performances of the designed two-stage CMOS class-AB power amplifier.
xvii
Chapter I
Introduction
I.1 Background
I.1.1 Power Amplifiers in Wireless Communication Systems
Recent years have witnessed a tremendous growth of wireless communication products. Consumer electronics, such as cellular phones, wireless local area networks, and
wireless computer peripherals, are just a few examples of the wireless devices that become part of our everyday lives. This constantly growing market drives an intense effort
to develop improved wireless standards and transceiver architectures, as well as reduce
implementation costs by using low-cost technologies and higher integration solutions.
Current implementation of wireless communication devices, such as cellular phones,
employ several chips implemented in different semiconductor technologies in order to realize high performance digital, analog, and RF circuit building blocks. Different technologies
are suited for different functions. For example, CMOS models an ideal switch very well,
thus is very suitable for digital functions and switch-capacitor circuits, but it is a poor technology for high-frequency, high performance analog functions for its low transconductance
and large parasitics; on the contrary, bipolar is well suited for high-frequency, high perfor-
2
mance analog functions, but not ideal for realizing digital functions and switch-capacitor
circuits due to its finite base current and other non-ideal switching characteristics.
The multi-chip solution limits the minimum cost and size of the final device. In
addition, the interface matching between different chips also adds cost, size, and time-tomarket to the final products. Thus, a single-chip solution is highly desirable.
With the advance of CMOS technology, many RF front-end functions, such as lownoise amplifier, mixer, and voltage-controlled oscillator can be implemented in a low-cost,
high-volume CMOS technology. However, a fully integration of CMOS power amplifier
(PA) still remains a design challenge because, as described later in this section, the limitations of the CMOS technology is especially severe for PA implementations.
Another reason for the reluctance of implementing PA in CMOS technology is the
high performance requirements imposed by modern wireless standards. With the growing
emphasis on channel capacity, more and more wireless communication systems employ
spectrally efficient modulation schemes, such as QPSK and QAM. These schemes results
in signals with highly time-varying envelopes, thus imposes a stringent linearity requirement of the power amplifiers to preserve modulation accuracy and limit spectral regrowth.
Meanwhile, to prolong battery life, a reasonable efficiency is also required for the power
amplifiers in such systems. Table 1 lists features pertinent to power amplifier design for
several digital wireless standards.
Table I.1: Characteristics of digital wireless systems relevant to power amplifier performance in mobile station [1].
CELLULAR
CORDLESS
Standard
GSM
NADC
IS-95
PDC
PHS
Uplink frequency
890-915
825-849
825-849
940-956
1895-1907
Channel BW (kHz)
200
32.81
1223
31.5
288
Multiple access
TDMA
TDMA
CDMA
TDMA
TDMA
Modulation
GMSK
/4-QPSK
/4-QPSK
Duplex mode
FDD
FDD
FDD
FDD
TDD
Max. TX power (dBm)
30
27.8
27.8
30.0
19.0
Long-term mean
21.0
23.0
10.0
N/A
10.0
TX duty ratio (%)
12.5
33.3
Variable
33.3
33.3
PA voltage (V)
3.56.0
3.56.0
3.56.0
3.54.8
3.13.6
ACPR (dBc)
N/A
-26
-26
-48
-50
Peak-ave. ratio (dB)
3.2
5.1
2.6
2.6
Typical PA quies-
20
180
200
150
100
> 50
> 40
> 30
> 50
> 50
band (MHz)
/4-QPSK O-QPSK
power (dBm)
cent current (mA)

Typical efficiency (%)
I.1.2 Power Amplifier Classifications

Power amplifiers are historically categorized to: A, AB, B, C, D, E, F, and S. While
the first four classes are distinguished primarily by their bias conditions, the others are
categorized based on the signal operations of the amplifier.
With respect to linearity performance, power amplifiers can be divided into linear
(A, AB, B) and nonlinear amplifiers (C, D, E, F, S). In general, efficiency and linearity are
4
two conflicting parameters in PA design. Table 2 shows the comparison of efficiency and
linearity among these power amplifiers.
Table I.2: Comparison of efficiency and linearity for different classes of power amplifiers
Classification
AB
Maximum Efficiency(%)
50
50-78
78
100
100
100
100
Typical Efficiency(%)
35
35-60
60
70
75
80
75
Linearity
Excellent
Good
Good
Bad
Bad
Bad
Bad
Vpeak(V)
2VDD
2VDD
2VDD
2VDD
2VDD
3.6VDD
2VDD
I.2 Limitations of Sub-micron CMOS Technology

In order to design a CMOS PA, one must first understand the limitations of submicron CMOS technology with respect to PA implementations. The major limitations are
low breakdown voltages, low transconductance-to-current ratio, and low substrate resistivity, as will be discussed successively.
I.2.1 Low Breakdown Voltages

The gate oxide breakdown occurs when the electric field in the oxide exceeds a cer in silicon dioxide). This process is destructive to the transistor
tain value (about 0.07 V/A
because it results in a permanent short circuit between the gate and the channel. As the gate
length in a CMOS technology shrinks, so does the thickness of gate oxide to avoid shortchannel effects [2]. Thus, the maximum allowable gate voltage for a sub-micron CMOS
5
device is greatly limited.
In addition to gate oxide breakdown, the drain-substrate pn junction will conduct a
large current if the reverse bias applied to it exceeds a certain value [2]. This breakdown is
nondestructive, but limits the maximum PA voltage swing at the drain of the device.
I.2.2 Low Transconductance-to-current Ratio

When the velocity saturates, the ratio of the transconductance to the current for a
short-channel MOS device is [3]
gm
1
1
=
=
.
I
VGS Vt
Vov
(I.1)
For a bipolar device, this ratio is 1/VT , where the thermal voltage VT is 26 mV. In contrast,
the overdrive Vov for MOS transistors is typically chosen as several hundred mV. Thus,
the transconductance per given current is much lower for MOS devices than for bipolar
devices.
To accommodate this small transconductance, either the input signal amplitude or
the device size of the PA output stage have to be increased. However, either approach will
increase the loading for the driving stage, thus resulting in higher power consumption of
the driver stage. Increasing the input signal amplitude can also dramatically degrade the PA
linearity because the third-order nonlinearity of the device current is directly proportional
to the cube of the input voltage amplitude. Thus, higher nonlinearity will be expected for
MOS devices than for bipolar devices.
I.2.3 Low Substrate Resistivity

In an integrated implementation, a PA resides on the same substrate as other circuit
blocks, some of which may be very sensitive. Since many CMOS processes use lowresistivity substrates, PA signals can be easily conducted across long chip distance to corrupt adjacent circuit blocks. Thus, substrate isolation is a crucial design issue for integrated
PA implementations.
In addition, a low-resistivity substrate has a detrimental effect on spiral inductors
built above it [4]. This is because the low resistivity allows for creation of eddy currents,
which reduce the effective magnetic field, thus the quality factor of the spiral inductor.
I.3 Dissertation Motivations

Class-E power amplifier is a promising candidate for realizing high efficiency. Previous analytical efforts on class-E power amplifiers assumed either zero switch resistance
and/or infinite drain inductance, leading to less optimized design. In this dissertation, we
attempt to achieve a more optimized design by accounting for both finite drain inductance
and finite on resistance for a NMOS device.
The intrinsic linearity obtained in a class-AB operation is often insufficient to meet
the stringent linearity requirement imposed by modern wireless standards. This is especially true for a MOS device due to its low transconductance. We attempt to linearize the
intrinsic linearity of a CMOS class-AB power amplifier and prove its feasibility for wireless
7
communications.
Although the designed two-stage CMOS class-AB PA exhibits good linearity and
maximum efficiency, it still suffers significant efficiency reductions when operated at low
power levels. Thus, we would like to explore the possibilities to improve the efficiency of
the CMOS class-AB PA at low output power levels.
I.4 Dissertation Organization

This dissertation consists of five chapters:
Chapter I is the introduction of power amplifiers in wireless communication systems,
the limitations of sub-micron CMOS technologies, and the motivations of this dissertation.
Chapter II presents an improved class-E analytical approach to account for both finite
drain inductance and finite on resistance of the NMOS device. A design example based
on the developed algorithm is described and verified by SPICE simulations. Key design
issues of this approach are highlighted in the end.
In Chapter III, we first identify the nonlinearity sources of a NMOS class-AB device.
Then a capacitance compensation technique is introduced, followed by the verification of
this technique using Volterra analysis. Key design issues regarding the schematic, layout,
and implementation of a two-stage CMOS class-AB power amplifier are described, and the
experimental results of prototype power amplifiers are presented and compared with simulations. It is shown that the capacitance compensation technique leads to a much better
linearity performance without seriously degrading the efficiency of the PA. This chapter
8
also proves the feasibility of linear CMOS class-AB PAs for wireless communication systems.
Chapter IV describes a dynamic biasing technique to improve PA efficiency at low
output power levels. The transient response of the envelope detector and the average efficiency for a CMOS class-AB PA are analyzed. The impact of the technique on PA linearity
is verified using both Volterra analysis and SPECTRE simulations. Finally, the experimental results of a prototype amplifier is presented.
Chapter V concludes the whole dissertation.
Chapter II
Class-E Power Amplifiers
II.1 Introduction
The class-E amplifier was first introduced by Ewing [5] in his doctoral thesis, and
then was further elaborated by many other researchers [6]-[11]. As one of the switchingmode amplifiers, the class-E amplifier realizes very high efficiency (theoretically 100%) by
operating the device as a switch, i.e.,
1. The device sustains zero voltage when it carries current.
2. The device carries zero current when it sustains a finite voltage.
3. There is no transition time between the on and off states of the device.
This is also referred as the non-overlapping-current-and-voltage condition and underlies
all switching-mode amplifiers. One unique feature, which distinguishes the class-E amplifier from other switching-mode amplifiers, is that it requires zero slope of the drain (or
collector) voltage at the moment when the device turns on. This requirement substantially
lowers the sensitivity of the amplifiers efficiency as a function of the component variations
and other non-ideal effects in practical implementations [12][13].
10
Ewings original development of the class-E amplifier assumed an infinite collector
inductance, but a finite saturation resistance of the transistor. In 1975, Sokal [6] derived a method to analyze class-E amplifiers in optimum performance, where he assumed
both an infinite choke inductor and zero switching-on resistance. In Lis analysis [8], a
finite choke inductor was introduced, but with an ideal switching-on condition. Recently
published class-E literatures [9]-[11] relied on the previously reported analysis and concentrated mostly on the implementation details. In practice, however, both the switching-on
resistance of the active device and the choke inductance are finite. The latter is especially
true if MOS devices are used; as will be shown in this chapter, the large shunt parasitic
capacitance of MOS devices requires relatively small drain inductance to achieve the optimum class-E operation at gigahertz-range frequencies. Therefore, an improved analytical
method which takes into account both the finite drain inductance and finite switching-on
resistance is necessary. In this chapter, this optimum is established under the constraint of a
given Rswitch-on Cswitch-off product, which is a more realistic estimate of typical MOS devices.
This new technique expresses the circuit parameters in terms of the device width and the
design specifications, such as the output power and operating frequency. The agreement
obtained between the analytical and simulated results is outstanding, verifying the utility
of the technique.
This chapter begins with a brief class-E circuit description, followed by a detailed
presentation of the improved analytical method. Then, a design example based on the
developed algorithm is described and SPICE simulation results are compared with the the-
11
oretical calculations. Finally, key design issues, such as the validity of assumptions and the
choice of device width, are discussed and conclusions are summarized.
II.2 Improved Class-E Analysis

II.2.1 Circuit Description
The simplified schematic for a CMOS class-E amplifier is shown in Fig. II.1(a). Here,
M0 is an NMOS device, L1 is the finite drain (choke) inductor, and L2 and C2 provides the
output matching. The following assumptions were made to simplify the analysis:
Ron , the switching-on resistance of the NMOS transistor, is constant and dominates
the total output impedance of the device during the on period.
C1 , the switching-off capacitance of the NMOS transistor, dominates the total output
impedance of the device during the off period and is independent of the switch
voltage Vd (t).
The quality factor Q of the output matching network is large enough to allow a sinusoidal output only.
Based on these assumptions, the transistor is considered to be a constant resistor Ron when
it is switched on, and a constant capacitor C1 when it is off, as shown in Fig. II.1(b). The
output matching network, L2 and C2 , can be divided into two parts: the ideal resonant
circuit at the operation frequency fc and the excessive reactance jX. The latter is for
12
VDD
L1
L2
C2
Vo
M0
RL
Vs
(a)
VDD
L1
i L(t)
i d(t)
on
R on
off
vd (t)
v2 (t)
i o (t)
resonator at
jX
vo (t)
C1
RL
(b)
Figure II.1: CMOS class-E power amplifier. Part (a) shows the simplified schematic, and
part (b) shows the model accounting for both finite on resistance and finite drain inductance.
13
shaping the current and voltage waveforms for the optimum class-E operation.
II.2.2 Circuit Equations

Output voltage and current
The amplifier is driven by a large, periodic square-wave voltage signal to obtain the
switching performance. Consequently, the steady-state output current is also periodic and
can be approximated as a sinusoidal waveform due to the high Q of the output matching
network. Let the signal period be T and the angular frequency be c = 2/T , the output
current is
io (t) = Io sin(c t + o )
(II.1)
where Io is the amplitude of the output current, and o is the phase shift constant.
The voltage at node 2 is also sinusoidal but with an extra phase shift by jX:
v2 (t) = V sin(c t + 1 )
(II.2)
where
s
V
1
X2
= Io RL
1+ 2
RL

X
= o + tan1
RL
(II.3a)
(II.3b)
14
Drain inductor current and drain voltage
To evaluate the current flowing through the finite drain inductor L1 , we apply KCL
at node 1:
iL (t) = id (t) + Io sin(c t + o ).
(II.4)
From the inductor characteristics, iL (t) is related to the drain voltage vd (t) by
VDD vd (t) = L1
diL (t)
.
dt
(II.5)
Since the device is switched between on and off states, the operation of the amplifier
can be divided into two parts:
Off state (nT t (n + 12 )T ): When the active device is off, vdoff (t) and idoff (t) are
governed by the characteristics of the capacitance C1 , i.e.,
idoff (t) = C1
dvdoff (t)
.
dt
(II.6)
Substituting (II.6) and (II.5) into (II.4) results in the following second-order differential equation:
L1 C1
d2 iLoff (t)
+ iLoff (t) = Io sin(c t + o ).
dt2
(II.7)
Solving this equation gives

iLoff (t) = A cos(o t) + B sin(o t) +
Io
sin(c t + o )
1 2
(II.8)
where
o =
1
L1 C1
= c /o
(II.9a)
(II.9b)
15
and the coefficients A and B are two constants to be determined.
On state ((n + 12 )T t (n + 1)T ): When the active device is on, it is modelled
as a small resistor, thus
vdon (t) = idon (t)Ron .
(II.10)
Substituting (II.10) and (II.4) into (II.5) gives a first-order differential equation:
VDD iLon (t)Ron + Io Ron sin(c t + o ) = L1
diLon (t)
.
dt
(II.11)
Solving this equation yields

iLon (t) =
Io
VDD
+ Cet (II.12)
[ sin(c t + o ) c cos(c t + o )] +
2
+ c
Ron
where the coefficient C is a constant to be determined, and is defined as

=
Ron
.
L1
(II.13)
II.2.3 Conditions
To evaluate the constants A, B, C, Io and o , we need to apply the periodic, boundary,
and class-E conditions to the above circuit equations. Those conditions are:
Periodic conditions: According to the characteristics of the inductance and capacitance, the current of L1 and the drain voltage (also the voltage of C1 ) satisfy
iLon (t) t=(n+1)T
= iLoff (t) |t=nT
(II.14a)
vdon (t) t=(n+1)T
= vdoff (t) |t=nT .
(II.14b)
16
Boundary condition: iLon (t) must be continuous, i.e.,
iLon (t) t=(n+1/2)T = iLoff (t) t=(n+1/2)T .
(II.15)
class-E conditions: The optimum class-E conditions are:
vdoff (t) t=(n+1/2)T
= 0
(II.16a)
dvdoff (t)
t=(n+1/2)T
dt
= 0.
(II.16b)
Substituting (II.6), (II.8), (II.10), and (II.12) into (II.14)-(II.16) gives the following equation array:
VDD
Io
Io sin o
+ CeT + 2
(II.17a)
(
sin
cos
)
=
A
+
o
c
o
Ron
( + c2 )
(1 2 )
Io
B Io cos o
CeT 2
(II.17b)
(
cos
sin
)
=
o
c
o
c
( + c2 )
(1 2 )
VDD
Io
+ CeT /2 2
+
B
sin
(
sin
cos
)
=
A
cos
o
c
o
Ron
( + c2 )
Io sin o
(II.17c)
(1 2 )
Io c
VDD
Ao sin Bo cos +
cos
(II.17d)
=
(1 2 )
Ron
Io c
VDD
CeT /2 + 2
(II.17e)
(
cos
sin
)
=
o
c
o
( + c2 )
Ron
Here, VDD , T , and c are fixed by the design specifications; and are functions of L1 and
C1 ; Ron and C1 are determined by the choice of device size.
17
DC Power Dissipation and Output Power
The total dc power Pdc is defined as the product of the power supply voltage VDD and
the dc current Idc drawn from the power supply:
Pdc = VDD Idc
(II.18)
where
1
Idc =
T
=
1
T
(n+1)T
iL (t) dt
nT
Z
(n+1/2)T
iLoff (t) dt +
nT
(n+1)T
iLon (t) dt .
(II.19)
(n+1/2)T
Meanwhile, Pdc is the sum of the power consumed by the load and the power dissipated in
the active device, i.e.,
Pdc = Pout + Pd .
(II.20)
During the switching-off period, only capacitive current flows into the device, implying no dc power dissipation in the device; during the switching-on period, Ron is the only
source of power consumption. Thus, the total power dissipation in the device, during one
period, is
1
Pd =
T
(n+1)T
(n+1/2)T
i2don (t)Ron dt.
(II.21)
Substituting (II.18), (II.19), and (II.21) into (II.20), we have

VDD
T
(n+1/2)T
iLoff (t) dt +
nT
(n+1)T
iLon (t) dt
(n+1/2)T
1
= Pout +
T
(n+1)T
(n+1/2)T
i2don (t)Ron dt
(II.22)
18
where iLoff (t) and iLon (t) are expressed in (II.8) and (II.12), respectively, and idon (t) is
related with iLon (t) by (II.4).
II.2.4 Component Evaluation

To evaluate the components of L1 , L2 , C2 , and RL , we need to first solve the major
current and voltage expressions: id (t), iL (t), io (t), and vd (t). As shown in (II.1), (II.8), and
(II.12), io (t) and iL (t) will be obtained if A, B, C, o , Io , , and are given. Once iL (t)
is solved, id (t) and vd (t) will be derived from (II.4) and (II.5), respectively. Therefore, our
first goal is to solve the above seven variables.
Since VDD , c , and Pout are fixed by the design specifications, the six independent
equations, (II.17a)-(II.17e) and (II.22), have a total of eight unknowns: A, B, C, o , Io , ,
, and Ron , among which and are functions of L1 , C1 , and Ron , as illustrated in (II.9b)
and (II.13), respectively. If both the technology and width of the active device are chosen,
Ron and C1 will be fixed. Then, the remaining six independent unknowns A, B, C, o ,
Io , and L1 can be solved.
With our assumption of the sinusoidal output, the resistive load RL is found from
Pout =
Io2
RL .
2
(II.23)
As shown in (II.3a), V the amplitude of v2 (t) is a function of Io , X, and RL ; in addition,

it is also the fundamental component of vd (t). Therefore, we have
2
V =
T
(n+1)T
vd (t) sin(c t + 1 ) dt.

nT
(II.24)
19
Substituting (II.3a) into (II.24) results in
s
Io RL
X2
1+ 2
RL
2
=
T
(n+1)T
vd (t) sin(c t + 1 ) dt
(II.25)
nT
thus the excessive reactance X is evaluated. There is no specific requirements for the
loaded Q of the output matching network, as long as it is large enough to allow a sinusoidal
output only. In practice, a Q of 5 is enough. Once Q is chosen, L2 is evaluated by
Q=
c L2
.
RL
(II.26)
and C2 is solved by
jc L2 +
1
= jX.
jc C2
(II.27)
Based on (II.23)-(II.27), the design algorithm of a CMOS class-E amplifiers in optimum performance is straightforward. MATHEMATICA scripts were developed to perform
the calculations.
II.3 A Design Example

As an example of this design technique, a CMOS class-E power amplifier was analyzed with the following design specifications:
Output power Pout : 0.25 W.
Power supply voltage VDD : 2 V.
Operating frequency fc : 1.9 GHz.
20
The device parameters are those of a 0.6 m digital CMOS technology, in which Ron is
approximately 3 and C1 is roughly 1 pF for a 1 mm device.
We first picked the NMOS width (WN ) as 3.5 mm, so the values of Ron and C1
were obtained. Following the component-evaluation procedure described in Section II.2.4,
we were able to compute L1 , L2 , C2 , and RL , as well as the expressions of id (t), iL (t),
io (t), and vd (t). Then, HSPICE netlists were constructed and simulated, and the results
were compared with the theoretical calculations. Table II.1 shows such comparison for the
amplifiers output power Pout and drain efficiency Peff ; also shown are the employed component values. As can be seen, less than 5% difference between the theoretical prediction
and simulation was achieved, verifying the utility of the technique.
The calculated and simulated current and voltage waveforms are compared in Fig. II.2.
Note that the pike in vd (t) comes from the sharp transition of the input square-wave signal.
Table II.1: Comparison of Pout and Peff between theoretical prediction and HSPICE simulation for the designed CMOS class-E power amplifier.
WN (mm)
L1 (nH) L2 (nH) C2 (pF)
RL ()
Pout (W)
Peff (%)
Theory
3.5
7.1
17
0.248
85
Simulation
3.5
7.1
17
0.25
87
Since we have the freedom in choosing the NMOS width WN , further calculations
and simulations were performed by sweeping WN from 2.5 mm to 5 mm. The resulting
Pout and Peff are shown in Fig. II.3.
21
0.5
0.4
0.3
CURRENT (A)
i (t)
L
0.2
0.1
i (t)
d
0.1
Calculation
Simulation
0.2
0.3
7.8
7.9
8.1
8.2
8.3
8.4
8.5
TIME (ns)
(a)
8
Calculation
Simulation
VOLTAGE (V)
6
vd(t)
4
vo(t)
2
0
2
4
7.8
7.9
8.1
8.2
8.3
8.4
8.5
TIME (ns)
(b)
Figure II.2: Comparison of the current and voltage waveforms between the calculation and
simulation. Part (a) shows the drain inductor current iL (t) and the drain current id (t); part
(b) shows the drain voltage vd (t) and the load voltage vo (t).
0.25
95
0.2
90
0.15
85
0.1
80
0.05
2.5
Calculation
Simulation
3
3.5
4.5
DRAIN EFFICIENCY (%)
OUTPUT POWER (W)
22
75
DEVICE WIDTH (mm)
Figure II.3: Output power and the drain efficiency versus NMOS width.
II.4 Discussions
II.4.1 Validity of Assumptions
As described in Section II.2.1, the following assumptions were made for our analysis:
Ron , the switching-on resistance of the NMOS transistor, is constant and dominates
the total output impedance of the device during the on period.
C1 , the switching-off capacitance of the NMOS transistor, dominates the total output
impedance of the device and is independent of the switch voltage Vd (t) during the
off period.
The loaded quality factor (Q) of the output circuit is high enough to allow a sinusoidal
output only.
Since the third assumption can be easily met by a proper choice of Q, we will only investigate the first two assumptions.
23
When the NMOS transistor turns on, it is in the triode region. Since the VDS is small,
the simplified model shown in Fig. II.4(a) is often used [14]. Here, rds corresponds to Ron ,
and is given by
rds =
n Cox
W
L
(II.28)
(VGS VTn )
The gate-to-channel capacitance is evenly divided between the source and drain nodes,
Cgs = Cgd =
W LCox
.
2
(II.29)
The channel-to-substrate capacitance is divided in half and shared between the source and
drain junctions. At the drain node, this channel capacitor, together with the junction-tosubstrate capacitance and the junction-sidewall capacitance, consists of the drain-bulk capacitance:
Cdb = Cj0 (Ad +
Ach
) + Cj-sw0 Pd .
2
(II.30)
For typical CMOS processes, Cdb and Cgd are in the range of 1 pF/mm. The quantity rds
depends on the gate-source voltage VGS , but has typical values of 2-4 /mm. At 1.90 GHz,
the impedance of Cdb and Cgd are much higher than the on resistance, thus verifying our
utilization of the first assumption.
When the transistor turns off, the model changes dramatically. A reasonable model
is shown in Fig. II.4(b). Since the channel has disappeared, Cgs and Cgd are now due to
only overlap and fringing capacitances:
Cgs = Cgd =
W Lov Cox
.
2
(II.31)
24
Vg
Cgs
Vs
rds
Csb
Cgd
Vd
Cdb
(a)
Vg
Cgd
Cgs
Vs
Vd
Cgb
Csb
Cdb
(b)
Figure II.4: Simplified NMOS small-signal model (a) in triode region and (b) in cut-off
region.
25
The capacitor Cdb , which is also smaller when the channel is not present, is
Cj0 Ad
.
VDB
1+
0
Cdb = r
(II.32)
The total drain capacitance, if the input is treated as ac ground, is the sum of Cgd and Cdb .
Thus, we have
C1 =
Cj0 Ad
W Lov Cox
.
+r
2
VDB
1+
0
(II.33)
As shown in (II.33), C1 is a nonlinear function of its own voltage VDB , as opposed to the
constant switching-off capacitance of the second assumption. The simulations, however,
showed that this nonlinear capacitance does not introduce significant errors, as illustrated
in Fig II.2 and II.3.
II.4.2 Choice of Device Width

As shown in Fig. II.3, the drain efficiency is improved with an increase of the device
width. This can be seen in (II.21): the power dissipated in the device is proportional to the
switching-on resistance Ron , and the wider the device is, the smaller Ron . Therefore, it is
not surprising that the efficiency is improved when a wider device is employed.
As the NMOS width increases, several practical issues arises. First, designing the
driving stage becomes more and more difficult because of the increase of the gate capacitance. Second, the optimum drain inductance becomes very small, resulting in difficulties
in practical implementation. Therefore, trade-offs have to be made in choosing the optimum NMOS width.
26
II.4.3 Relationship between Pout and VDD

As illustrated in (II.17a)-(II.17e) and (II.22), all the variables have linear relationship
with VDD . In other words, if
0
VDD
= kVDD
(II.34)
Io0 = kIo
(II.35)
A0 = kA
(II.36)
B 0 = kB
(II.37)
C 0 = kC
(II.38)
and
all the equations will be reduced to their original forms. Therefore, all the component
values L1 , L2 , C2 , and RL are unchanged, and all the current and voltages id (t), iL (t),
io (t), and vd (t) are k times their original values. The output power becomes
0
Pout
= k 2 Pout .
(II.39)
This implies a perfect application of class-E power amplifiers in envelope elimination and
restoration (EER) systems, where the envelope variation of the modulated signal is imposed
to the switching power amplifier through the power supply.
It is important to mention, however, that our analysis assumed the constant switchingoff capacitance C1 . For the actual devices, as described in Section II.4.1, C1 is nonlinear
and varies with the drain-voltage swing; this may introduce some errors.
27
Some papers [15][16] claimed that the nonlinear parasitic capacitor does not influence the class-E performance. This conclusion, however, is made based on the ideal
switching-on condition (Ron =0) and infinite drain inductance. In addition, the resulted operation, due to the nonlinear capacitance, does not predict the linear relationship with VDD ,
as opposed to our above conclusion. The details can be seen in (4.1)-(4.5) of [15].
II.4.4 Comparison with Previous Works

To show this technique leads to improved designs, simulations were performed based
on the different design approaches developed by Ewing [5], Sokal [6], Li [8], and our results, respectively. Ewing assumed an infinite drain choke inductance but a finite switchingon resistance; Sokal assumed an infinite drain choke inductance with an ideal switching
condition, i.e., zero switching-on resistance; Li took the finite drain inductance into account
and assumed an ideal switching condition. These assumptions are shown in Table II.2.
Table II.2: Assumptions for the analysis by Ewing, Sokal, Li, and this work.
Ewing [64]
Sokal [75]
Li [94]
This work
Switching-on resistance
finite
zero
zero
finite
Drain inductance
infinite
infinite
finite
finite
To make the comparison fair, we employed the same devices and set the same design
specifications of Pout = 0.25 W and fc = 1.9 GHz. Since both Ewing and Sokal assumed
an infinite choke inductance, their designs have one degree less freedom than Lis and ours.
To achieve the design specifications and make the comparison possible, VDD was varied for
28
Ewings and Sokals designs and was fixed as 2 V for Lis and our designs.
Figure II.5 shows the simulated output power and drain efficiency versus the device
width by the four design approaches. As can be seen, Ewings approach has good output
power performance but poor drain efficiency, while both Sokals and Lis works achieve
good efficiency but predict poor output power. Our design technique, however, not only
achieves the designed output powers, but also obtains the optimized drain efficiency.
0.3
Design goal
OUTPUT POWER (W)
0.25
0.2
0.15
Ewing [64]
Sokal [75]
Li [94]
This work
0.1
0.05
2.5
3.5
4.5
DEVICE WIDTH (mm)
(a)
DRAIN EFFICIENCY (%)
100
80
60
Ewing [64]
Sokal [75]
Li [94]
This work
40
2.5
3.5
4.5
DEVICE WIDTH (mm)
(b)
Figure II.5: Simulated (a) output power and (b) drain efficiency versus NMOS width for
the design approaches developed by Ewing, Sokal, Li, and this work.
29
II.5 Conclusions
An improved design technique is developed to derive the optimum performance of a
CMOS class-E power amplifier. Compared with other theoretical approaches, this design
approach models not only the finite drain inductance, but also the switching-on resistance
of the transistor, thus it leads to a more optimized design. With this design technique,
optimum circuit parameters, as well as the voltage and current waveforms, are derived and
numerically computed.
The design algorithm we developed is applicable not only for bulk MOS devices, but
also for other active devices, such as bipolar transistors, as long as they are operated as
switches.
The disadvantage of this technique is the analytical complexity rising from the inclusion of both the finite choke inductance and the finite switching-on resistance. Although
the analysis leads to more accurate and optimized designs, it does not provide intuitive and
straightforward expressions.
Chapter III
Linear CMOS Class-AB Power
Amplifiers
III.1 Introduction
As described in the first chapter, to meet the simultaneous requirements of high linearity and reasonable efficiency, power amplifiers in non-constant-envelope systems are
often operated in a class-AB mode. Although more linear than a class-B or higher amplifier, the intrinsic linearity obtained in class-AB operation is often still insufficient to meet
required specifications. This is especially true if a MOS device is employed because the
low transconductance associated with the MOS device requires a relatively large input voltage signal, and since the third-order nonlinearity (e.g., IM3) is directly proportional to the
cube of the input signal amplitude, this large signal amplitude will yield significant nonlinearity at the output. While many external linearization techniques are known [12], they
are complex and inconvenient for handset applications, and it is thus important that the
intrinsic amplifier linearity be made as high as possible. In this chapter, it is shown that the
gate-source capacitance of a MOS device is a major source of nonlinearity that can limit
the performance of a CMOS class-AB power amplifier. A simple technique to compensate
30
31
the nonlinearity is suggested, and simulations and experiments on a prototype amplifier are
used to demonstrate its effectiveness.
This chapter will begin with a description of distortion effects of the gate-source
capacitance. Then a capacitance compensation technique will be introduced, followed by
the verification of this technique using Volterra analysis. The detailed schematic and layout
designs will be presented, along with the implementation issues and experimental results
of the prototype power amplifiers. Finally, the conclusions will be summarized.
III.2 Distortion Effects of the Gate-Source Capacitance

III.2.1 Simplified Model
Figure III.1(a) shows a highly simplified model for an NMOS device working as a
class-AB amplifier. Here, the input signal current is is , the input-matching network (which
includes the source admittance) is I, the output-matching network is O, and the load resistance is RL . The transistor itself is modeled using the quasi-static, drain-source signal
current idsn (vgs , vds ), which is a function of both the gate-source and drain-source signal
voltages, vgs and vds , and the following device capacitances: the gate-body capacitance
Cgbn , the gate-source capacitance Cgsn , and the gate-drain capacitance Cgdn . This model
assumes that the intrinsic source and body (substrate) are connected together, and omits a
number of elements, including the gate, drain, and source resistances, a substrate network,
and the capacitance between drain and source (although the linear parts of some of these
32
elements could be absorbed into I and O). These simplifications are justified, since the purpose of the model is merely to illustrate the main sources of nonlinearity under class-AB
operation. For accurate simulation results needed in final designs, however, it should be
noted that radio-frequency (RF) MOS models should include the omitted elements [17]
[21].
Cgdn
is
Cgbn
Cgsn
i dsn
RL
RL
s
(a)
Cgdn
is
Cgbn
Cgsn
i dsn
Cgdp
Cgbp
Cgsp
i dsp
(b)
Figure III.1: Simplified models of CMOS class-AB power amplifiers. Part (a) shows an
NMOS device working alone, and part (b) shows an NMOS device along with a PMOS
device used to provide a compensating input capacitance.
33
III.2.2 Capacitance Components

Shown in Fig. III.2 are plots of the simulated NMOS device capacitances as a function of gate-source voltage, for a fixed drain-source voltage. The variation of the capacitances with drain-source voltage can be neglected as long as the device remains in saturation [2, Ch. 8]; this is typically ensured in power-amplifier design, since appreciable
distortion would otherwise occur when the device transits across the knee that exists in
the current-voltage characteristics between the saturation and triode regions. The device is
Cggn (ac simulation)

Cgsn+Cgbn+Cgdn
Cgsn
Cgbn
Cgdn
CAPACITANCE (pF)
16
12
0.5
1.5
GATESOURCE VOLTAGE (V)
Figure III.2: Plots of the simulated NMOS device capacitances as a function of gate-source
voltage, for a fixed drain-source voltage of 3.3 V. The device length and width are 0.5 m
and 3 mm, respectively, and the device threshold voltage is VTn = 0.66 V.
from IBMs SiGe5AM technology, and the plots were obtained using SPECTRE circuit
simulator and the associated commercial MOS model released by IBM; the model employs BSIM3v3.2 as an intrinsic subcircuit, along with extrinsic parasitics to account for
RF effects [22, p. 53].
Figure III.2 confirms that the total capacitance seen looking into the gate, as found
34
from an ac simulation at each gate-source voltage, Cggn Im {y11 }/, where y11 is the
short-circuit, common-source input admittance and = 2(2 GHz) is the radian frequency, is equal to the sum of the individual capacitance components mentioned earlier:
Cggn = Cgsn + Cgbn + Cgdn . This is to be expected when the devices parasitic resistances
are negligible [19, eq. (9)], and helps to validate the simplified model of Fig. III.1(a). More
importantly, Fig. III.2 shows that while Cgdn and Cgbn are relatively constant, Cgsn varies
substantially as the device transits from an off (below threshold) to an on (above threshold) state. While Cgsn as plotted includes both intrinsic and extrinsic parts, almost all of this
variation can be traced to a change in the intrinsic part [19, Fig. 3(a)]. This variation is particularly germane for class-AB operation, because the transition in the capacitance occurs
at the devices threshold voltage, close to where it is typically biased. As will be shown,
the change in capacitance leads to substantial distortion at the gate, and can subsequently
limit overall amplifier linearity.
III.2.3 Impact on Linearity

In order to illustrate the impact of the gate-source capacitance on the linearity of a
class-AB amplifier, the simplified circuits of Fig. III.3 will be used; the circuit in Fig. III.3(a)
is a basic class-AB amplifier, and the circuit in Fig. III.3(b) includes additional circuitry to
compensate or linearize the nonlinear capacitance between the gate and source that
will be explained in Section III.3 A.
In addition to providing appropriate matches at the fundamental frequency, the input
35
V GG
is
V DD
Input
matching
network
Output
matching
network
RL
Output
matching
network
RL
(a)
V GG
is
V DD
Input
matching
network
V PP
(b)
Figure III.3: Simplified schematics of class-AB amplifiers used to illustrate the impact of
the gate-source capacitance on linearity. The basic amplifier is in (a), and the linearized version is in (b). The NMOS and PMOS devices are the same as those in Figs. III.2 and III.6,
respectively.
36
and output matching networks include short-circuit terminations at the harmonic frequencies, which we found helped overall linearity1 ; they also helped to boost the fundamental
output power [23, p. 384]. The input network includes the source admittance, chosen in
this case to represent the output admittance of a driving class-A stage. In fact, the circuits
in Fig. III.3 are simplified versions of actual two-stage, class-AB amplifiers that were built
and tested, and which will be described in Section III.6.
Figures III.4 and III.5 show SPECTRE simulations of the third-order, intermodulation distortion (IM3) at 21 2 for a two-tone input at frequencies 1 = 2(1.96 GHz)
and 2 = 2(1.94 GHz), at the gate and drain, respectively; note that the drain IM3 is
equivalent to the load IM3, since O and RL are linear and 21 2 1 .
As shown, the basic amplifier of Fig. III.3(a) incurs substantial distortion at both
the gate and drain; it will be proven in Section III.3 B that most of this distortion is due
to the change in gate-source capacitance as the device turns on and off during class-AB
operation. On the other hand, Figs. III.4 and III.5 show that much better performance can
be obtained by employing the scheme illustrated in Fig. III.3(b), where a compensating
nonlinear capacitance is added at the input.
The details are described in the out-of-band termination part of Section III.4.
37
VGG = 0.75V
VGG = 0.80V
20
basic
40
60
linearized
SPECTRE (basic)
SPECTRE (linearized)
Volterra (basic)
Volterra (linearized)
80
0
10
20
GATEVOLTAGE IM3 (dBc)
20
basic
40
linearized
60
80
30
OUTPUT POWER (dBm)
linearized
80
10
20
OUTPUT POWER (dBm)
30
VGG = 0.90V
40
30
20
basic
60
20
OUTPUT POWER (dBm)
VGG = 0.85V
20
10
basic
40
60
linearized
80
0
10
20
30
OUTPUT POWER (dBm)
Figure III.4: Third-order, intermodulation distortion at 21 2 versus peak-envelope

output power, at various gate bias voltages. The circuits are the basic and linearized classAB amplifiers in Figs. III.3(a) and III.3(b), respectively. These plots are for the distortion
in the gate voltage. Values from both simulation (using SPECTRE) and Volterra theory
[using (III.22)(III.28)] are shown.
38
VGG = 0.75V
VGG = 0.80V
20
basic
40
linearized
60
SPECTRE (basic)
SPECTRE (linearized)
Volterra (basic)
Volterra (linearized)
80
0
10
20
DRAINVOLTAGE IM3 (dBc)
20
basic
40
linearized
60
80
30
OUTPUT POWER (dBm)
linearized
80
10
20
OUTPUT POWER (dBm)
30
VGG = 0.90V
40
30
20
basic
60
20
OUTPUT POWER (dBm)
VGG = 0.85V
20
10
basic
40
linearized
60
80
0
10
20
30
OUTPUT POWER (dBm)
Figure III.5: Third-order, intermodulation distortion at 21 2 versus peak-envelope

output power, at various gate bias voltages. The circuits are the basic and linearized classAB amplifiers in Figs. III.3(a) and III.3(b), respectively. These plots are for the distortion
in the drain voltage. Values from both simulation (using SPECTRE) and Volterra theory
[using (III.22)(III.28)] are shown.
39
III.3 Compensation Technique

III.3.1 Basic Idea
Shown in Fig. III.6 are plots of the device capacitances of a PMOS transistor as a
function of its gate-source voltage, with the drain-source voltage held at zero.
CAPACITANCE (pF)
12
Cgsp+Cgbp+Cgdp
C
gsp
Cgbp
Cgdp
0.5
0.5
GATESOURCE VOLTAGE (V)
Figure III.6: Plots of the device capacitances of a PMOS transistor as a function of its gatesource voltage, with its drain-source voltage held at zero. The device length and width are
0.5 m and 2 mm, respectively, and the device threshold voltage is VTp = 0.49 V.
As can be seen, while Cgbp is relatively constant, Cgdp and Cgsp change2 from a high
to a low value as the device transits from an on to an off state. This behavior is exactly
complementary to that of Cgsn in Fig. III.2. Therefore, it should be possible to linearize
or compensate Cgsn with the aid of a PMOS device. The basic idea is simply to place a
PMOS device alongside the NMOS device as illustrated in Fig. III.3(b); the model for the
situation is shown in Fig. III.1(b). When the PMOS device is properly biased and sized,
2
Since the drain-source voltage is zero, Cgdp should equal Cgsp ; the small discrepancy occurs due to an
implementation limit in BSIM3v3 [24, Ch. 4].
40
the total capacitance Cggn + Cggp seen at the NMOS gate will be a constant, which reduces
the distortion generated at the gate, and subsequently at the drain.
Since the change in the NMOS and PMOS capacitances occurs at their respective
threshold voltages, it is clear that the PMOS bias voltage VPP in Fig. III.3(b) should be
VPP = VTn VTp .
(III.1)
Neglecting Cgbn and Cgbp and extrinsic contributions to the capacitances, an appropriate
figure for the sizing of the PMOS device can be obtained by noting that the NMOS device
switches between weak and strong inversion, and the PMOS device works in the triode
region. Therefore [2, Sec. 8.3.2], the changes in NMOS and PMOS capacitances are approximately
2
Cggn Cgsn Wn Ln Cox n
3
(III.2)
and
Cggp
Wp Lp Cox p
(Cgsp + Cgdp ) 2
= Wp Lp Cox p
2
(III.3)
where Wn and Ln , and Wp and Lp , are the widths and lengths of the NMOS and PMOS devices, and Cox n and Cox p are their oxide capacitances, respectively. Assuming the changes
in the capacitances are abrupt, we then require
Cggn
2 Wn Ln Cox n
1
Cggp
3 Wp Lp Cox p
which can be used as a guide to size the PMOS device.
(III.4)
41
Cggn+Cggp
C
ggn
Cggp
CAPACITANCE (pF)
20
16
12
0.5
1.5
NMOS GATESOURCE VOLTAGE (V)
Figure III.7: Plots of simulated Cggn , Cggp , and the sum Cggn + Cggp for the NMOS and
PMOS devices of Figs. III.2 and III.6.
Figure III.7 shows plots of Cggn and Cggp , found from Im {y11 }/, and of the sum
Cggn + Cggp , for the NMOS and PMOS devices of Figs. III.2 and III.6. As shown, while
both Cggn and Cggp vary with the NMOS gate-source voltage, the sum Cggn + Cggp remains
roughly constant. The small ripple that occurs in the sum at the transition point arises
because the capacitances do not change abruptly; the slope of the Cggn curve is not exactly
equal (in magnitude) to that of the Cggp curve. The ripple can be minimized by adjusting
the bias and size of the PMOS device from the nominal values given by (III.1) and (III.4).
The impact of linearizing or compensating the input capacitance can be understood
with the aid of Volterra analysis.
III.3.2 Volterra Analysis

Usually, Volterra analysis assumes each nonlinear element in a circuit can be described by a third-order, power-series expansion in which the series coefficients depend
42
only on the circuits bias point. Such analysis cannot be used to describe a highly nonlinear
circuit, such as a class-AB power amplifier. However, we will attempt to alleviate this problem by employing power-series expansions of order greater than three, and by allowing the
series coefficients to depend on both the bias point and the RF signal power.
Characterization of Ceff and ids

Defining an effective gate-source capacitance Ceff , and referring to Figs. III.1(a)
and III.1(b), the values of Ceff in the uncompensated and compensated cases are, respectively, as follows:
Ceff = Cgbn + Cgsn
(III.5)
Ceff = Cgbn + Cgsn + Cgbp + Cgsp + Cgdp .
(III.6)
and
At each bias point, the RF signal power determines the range of excursion of the NMOS
gate-source voltage; for simplicity, this range can be approximated to be the peak-to-peak
excursion of the two-tone envelope (i.e., the envelope arising from the fundamental signal
components at 1 and 2 , and neglecting the much smaller harmonic and intermodulation
components). With knowledge from SPECTRE of the behavior of the individual components of Ceff versus this voltage, Ceff can then be modelled as a power series. We found that
a fifth-order power series would work well for all bias points and for all RF signal powers
43
considered, i.e., Ceff could always be written as follows:
2
3
4
Ceff = c1 + c2 vgs + c3 vgs
+ c4 vgs
+ c5 vgs
.
(III.7)
It is important to emphasize that when the bias point or RF signal power changes, the
coefficients c1 through c5 also change, such that the expansion in (III.7) always traces out
the appropriate Ceff versus vgs curve.
The behavior of the large-signal, quasi-static, drain-source current iDSN (vGS , vDS ) for
the NMOS transistor as a function of vGS and vDS can be simulated with SPECTRE, and
the results can be used to expand the corresponding signal current idsn in Figs. III.1(a)
and III.1(b) as a power series. In performing the expansion, for simplicity, the dependence
on the drain-source voltage is first eliminated. Referring to Figs. III.3(a) and III.3(b), this
is done by approximating vDS to be a superposition of the dc bias and the purely linear part
of the output signal:
vDS VDD gm vgs RO
(III.8)
where gm is the short-circuit transconductance, given by gm iDSN /vGS with vDS

VDD , and RO is the equivalent resistance (at the fundamental frequency) seen looking into
the output matching network from the NMOS drain. This approximation is used solely
for the purpose of simplifying the power-series expansion of idsn ; once the expansion is
established, the true nonlinear relationship between the drain and gate voltages will be
taken into account by the Volterra analysis. At each NMOS bias point (VGG , VDD ), a given
RF signal power defines the range of excursion of vgs , which is again approximated to be
the peak-to-peak excursion of the two-tone envelope, and for each such excursion, the locus
44
of points traced out by iDSN (VGG + vgs , VDD gm vgs RO ) can be used to find a power series
for idsn in terms of vgs . In this case, we found a series of order three sufficed, i.e., idsn could
be written as follows:
2
3
idsn = g1 vgs + g2 vgs
+ g3 vgs
(III.9)
where, as before, the coefficients g1 through g3 change with both the bias point and the RF
signal power, such that (III.9) always traces out the appropriate idsn versus vgs curve.
Figure III.8 shows the SPECTRE simulated and MATLAB fitted curves for Ceff and
idsn as functions of the NMOS gate-source voltage. The fitted curves shown are for the gate
bias of VGG = 0.8 V, and the input voltage amplitude vgs of 0.2 and 0.6 V, respectively. As
can be seen, the third-order current and fifth-order capacitance polynomials can fit idsn and
the compensated Ceff very well at all signal levels we are interested; for the uncompensated
Ceff , however, the fifth-order polynomial can fit well only at low power levels. This is not
surprising considering the strong nonlinear relationship between the uncompensated Ceff
and the NMOS gate-source voltage. It can be shown that a higher order polynomial will
yield a better fit but a much more complicated analysis. Thus, the choice of a fifth-order
polynomial fit for the capacitance is a compromise between accuracy and complexity.
Terminations at Sub- and Second Harmonics

In order to understand the impact of the matching-network impedances at the suband second harmonics ( and 2) on the linearity of the amplifier, it is instructive to
derive the voltage response vC of a nonlinear capacitor shown in Fig. III.9. From the
GATESOURCE CAPACITANCE (pF)
45
20
SPECTRE data
Curvefit (vgs=0.2 V)
16
12
0
0
0.2
0.4
0.6
0.8
1.2
1.4
(a)
DRAIN CURRENT (A)
0.6
SPECTRE data
0.4
0.2
0
0
0.2
0.4
0.6
0.8
1.2
1.4
1.6
(b)
Figure III.8: SPECTRE simulated and MATLAB fitted curves for (a) Ceff and (b) idsn as
functions of the NMOS gate-source voltage. The fitted curves shown are for the gate bias
of VGG = 0.8 V, and the input voltage amplitude vgs of 0.2 and 0.6 V, respectively.
46
iC
is
Ys
vC
Figure III.9: Nonlinear capacitor circuit for Volterra analysis.
definition of capacitance,
C=
dQ
dQ dt
dt
=
= iC
dvC
dt dvC
dvC
(III.10)
Substituting (III.7) into (III.10) and rearranging gives the current in the capacitor as
iC = c1
dvC c2 dvC2
c3 dvC3
+
+
.
dt
2 dt
3 dt
(III.11)
Here, for illustration purposes, only the first three terms in (III.7) were used. Let vC be
vC = H1 (ja ) is + H2 (ja , jb ) i2s + H3 (ja , jb , jc ) i3s .
(III.12)
Applying KCL gives

is = vC Ys + iC .
(III.13)
Substituting (III.11) and (III.12) into (III.13) and equating the first-order terms gives
is = Ys (ja )H1 (ja ) is + ja c1 H1 (ja ) is .
(III.14)
47
Rearranging (III.14) yields
H1 (ja ) =
1
.
ja c1 + Ys (ja )
(III.15)
The same procedure can be applied for the second and third order terms, and we obtain
H2 (ja , jb ) =
j(a + b )c2 H1 (ja )H1 (jb )

.
2[j(a + b )c1 + Ys (ja + jb )]
(III.16)
and
H3 (ja , jb , jc ) =
j(a + b + c )
3[j(a + b + c )c1 + Ys (ja + jb + jc )]
[c3 H1 (ja )H1 (jb )H1 (jc ) + 3c2 H1 (ja )H2 (jb , jc )]
(III.17)
where
1
H1 (ja )H2 (jb , jc ) = [H1 (ja )H2 (jb , jc ) + H1 (jb )H2 (ja , jc )
3
+ H1 (jc )H2 (ja , jb )].
(III.18)
The IM3 of vC at 22 1 is
IM3 =
3|H3 (j2 , j2 , j1 )|i2s

.
4|H1 (j1 )|
(III.19)
Since the tone spacing 2 1 is generally much smaller than 1 and 2 , let = 2 1
and 2 1 . Then (III.17) reduces to
H3 (j2 ,j2 , j1 ) =
j
3[jc1 + Ys (j)]
[c3 H12 (j)H1 (j) + c2 (2H1 (j)H2 (j) + H1 (j)H2 (j2))] (III.20)
48
where
jc2 |H1 (j)|2
2[jc1 + Ys (j)]
j2c2 H1 (j)2
H2 (j2) =
.
2[j2c1 + Ys (j2)]
H2 (j) =
(III.21a)
(III.21b)
Special attention should be paid to the terms in the second bracket of (III.20). The
first term comes from the intrinsic third-order nonlinearity c3 ; the second term comes
from the second-order nonlinearity c2 , which yields third-order products by first generating second-order products and then mixing them with the fundamental signals. (III.21)
shows that H2 (j) and H2 (j2) are greatly influenced by the source conductance Ys at
the sub- and second harmonic frequencies. For example, H2 (j) and H2 (j2) can be
set to zero by letting Ys (j) and Ys (j2) be infinity, which is equivalent to shorting the
impedance at and 2.
The same conclusions can be drawn for the simplified nonlinear model of the PA
output stage shown in Fig. III.10. Note that after compensation, Ceff can be approximated
as a linear capacitor, which has no second-order nonlinearity. However, the sub- and second
harmonics can still appear at vgs through the Cgdn feedback.
The impact of out-of-band (in particular, the sub- and second-harmonic) impedances
on circuits linearity are also described in [25][27]. For weakly nonlinear circuits like
LNA, Volterra analysis can be applied to derive the output linearity as a function of the
out-of-band impedances, and it was shown that if the out-of-band terminations are properly
chosen, the circuits linearity can be improved dramatically [27]. However, this optimization technique is not applicable for strong nonlinear circuits such as class-AB PAs, because
49
Cgdn
i ds1
ZI
v gs
Ceff
i dsn
Cdsn
ZL
Figure III.10: Simplified nonlinear model of the PA output stage.
the strong nonlinearity sources associated with the class-AB operation do not generally
have constant second and third order coefficients for the entire signal range, as exemplified in Fig. III.5. Optimizing the linearity at one signal level could worsen the linearity at
other signal levels. In addition, varying the input second harmonic of a strong nonlinear
source can also influence the generation of its intrinsic third-order term, thus making the
optimization untractable.
However, leaving the out-of-band impedances unattended is not a good strategy either. Our calculations and simulations for the PA output stage show that while the subharmonic impedances of the initially designed input and output matching networks have
slight effects on the load linearity, the second-harmonic impedance of the output matching network can deteriorate the load IM3 4 5 dB for a wide signal range. Thus, on-chip
second-harmonic short circuits are included in the final amplifier.
50
IM3 Calculation
With the power series in (III.7) and (III.9) established and the out-of-band short circuitry applied, the circuit for the Volterra calculation, based on the method of nonlinear
currents [23, pp. 190-207], is shown in Fig. III.11. Here, ZI represents the impedance
Cgdn
+
ZI
~
v gs, 21 2
c1
Ceff, 21 2
~
g1 v
gs, 21 2
dsn, 21 2
ZO
Figure III.11: Circuit for the Volterra calculation.
seen looking into the input matching network from the NMOS gate, and ZO represents the
impedance seen looking into the output matching network from the NMOS drain. Since ZI
presents a short circuit at even-order frequencies (see Section III.2), the distortion currents
generated by idsn and Ceff have the following phasor amplitudes:
3 2
dsn,21 2 = g3 vgs,
v
1 gs,2
4
(III.22)
and
Ceff ,21 2
1 2
1 3
2
2
= j(21 2 ) c3 vgs,1 vgs,2 + c5 2
vgs,1 vgs,1 vgs,2 + 3
vgs,1 vgs,2 vgs,2
4
8
(III.23)
where vgs,1 and vgs,2 are the phasor amplitudes of the gate-source voltage at the fundamental frequencies, and denotes complex conjugation. The distortion voltages that
51
result at the gate and drain can then be computed using the circuit of Fig. III.11:
vgs,21 2 =
ZI0 {dsn,21 2 [j(21 2 )Cgdn ZO ] + Ceff ,21 2 [1 + j(21 2 )Cgdn ZO ]}

1 + j(21 2 )Cgdn (ZI0 + ZO + g1 ZI0 ZO )
(III.24)
vds,21 2 =
ZO {dsn,21 2 [1 + j(21 2 )Cgdn ZI0 ] Ceff ,21 2 [g1 j(21 2 )Cgdn ]ZI0 }
1 + j(21 2 )Cgdn (ZI0 + ZO + g1 ZI0 ZO )
(III.25)
where ZI0 ZI k c1 , and the impedances ZI0 and ZO should be evaluated at the intermodulation frequency 21 2 . The drain voltage at the fundamental frequency is also easily
found to be
vds,1 =
g1 ZO + j1 Cgdn ZO
vgs,1
1 + j1 Cgdn ZO
(III.26)
where, in this case, ZO should be evaluated at the fundamental frequency 1 . The IM3 at
the gate and drain are then simply
vgs,21 2
IM3G = 20 log
vgs,1
(III.27)
vds,21 2
.
IM3D = 20 log
vds,1
(III.28)
and
IM3 Contributions from Ceff and ids

Superimposed on the SPECTRE simulation results in Figs. III.4 and III.5 are values
for the gate and drain IM3 found from (III.22)(III.28), with vgs,1 vgs,2 obtained from
the terminal gate-source voltage of the NMOS device in SPECTRE. As shown, the Volterra
52
expressions are able to predict the main trends in IM3 as a function of both bias and power
level. Of course, since the power-series coefficients in (III.7) and (III.9), and the values of
vgs,1 vgs,2 , were all found from SPECTRE, this agreement may not be too surprising.
However, the real utility of the Volterra expressions lies in their ability to isolate the impact
of the individual nonlinearities.
Figure III.12 shows the contributions to the drain IM3 arising from the Ceff and idsn
nonlinearities, as computed from (III.25), (III.26), and (III.28). The contribution from Ceff
is found by setting dsn,21 2 0 in the expressions, and the contribution from idsn is
found by setting Ceff ,21 2 0. The Ceff contributions are shown for both the basic and
linearized amplifiers; the idsn contributions do not change, so only one curve is shown.
As illustrated, in the basic amplifier, the Ceff nonlinearity limits the drain IM3 over
most power levels; only at very high power levels does the idsn nonlinearity become important, which is simply a result of increased clipping in class-AB mode. On the other
hand, in the linearized amplifier, the impact of the Ceff nonlinearity is greatly reduced,
and correspondingly, except at high power levels where the idsn nonlinearity dominates, the
compensation scheme leads to the improved performance originally seen in Fig. III.5. Similar analysis could be undertaken and comments made for the gate IM3 in Fig. III.4. (Again,
there is no improvement at very high power levels due to the idsn nonlinearity, which can
impact the gate IM3 by way of feedback through Cgdn .)
53
VGG = 0.75V
VGG = 0.80V
40
20
C eff
(basic)
i dsn
60
C eff
(linearized)
80
0
10
20
IM3 CONTRIBUTION (dBc)
20
C eff
(basic)
40
i dsn
60
C eff
(linearized)
80
30
OUTPUT POWER (dBm)
20
30
OUTPUT POWER (dBm)
VGG = 0.85V
VGG = 0.90V
20
C eff
(basic)
40
i dsn
60
C eff
(linearized)
80
0
10
20
OUTPUT POWER (dBm)
30
20
10
C eff
(basic)
40
i dsn
60
C eff
(linearized)
80
0
10
20
30
OUTPUT POWER (dBm)
Figure III.12: Calculated contributions to the drain IM3 from the Ceff and idsn nonlinearities
for both the basic and linearized amplifiers in Figs. III.3(a) and III.3(b), respectively. The
values are computed from the Volterra expressions (III.22)(III.28), as described in the text.
54
III.4 Schematic Design

The PA schematic design involves many considerations and tradeoffs among cost,
ease of integration, and performances. In our design, a single-ended, two-stage configuration was employed. The benefit of a single-ended topology is that it avoids the use of
baluns, thus making the PA more cost-effective and easier to integrate. Meanwhile, the
two-stage design enables us to achieve a power gain higher than 20 dB. Figure III.13 shows
the simplified block diagram of the designed two-stage CMOS class-AB power amplifiers.
VDD
V GG0
VDD
VGG1
RF
choke
RF
choke
Rs
Vs
Input
matching
network
M1
Interstage
matching
network
M0
Output
matching
network
R50
V PP
Mp
Driver stage
Output stage
Figure III.13: Simplified block diagram of designed two-stage CMOS class-AB power
amplifiers.
This section will begin with the design of the output and driver stages. Then the
influence of out-of-band impedances on the amplifier linearity will be discussed, followed
by the study of the impact of ground connections on the amplifier gain and stability. Finally, the schematic of a fully matched two-stage CMOS class-AB power amplifier will be
55
presented.
III.4.1 Output Stage

Circuit Topology
A cascode topology is commonly used in analog and RF circuits since it provides
high gain and good reverse isolation. For PA applications, it also relaxes the breakdown
voltage concerns for each individual transistor. However, two disadvantages associated
with the cascode structure make it less attractive for RF linear power amplifier applications. First, the cascode structure limits the maximum drain voltage swing of the output
device, thus significantly degrading the drain efficiency. Second, due to the introduction
of another nonlinear device, the cascode power amplifier will generally exhibit worse linearity than its single-transistor counterpart. It is also worth mentioning that the inclusion
of an extra transistor greatly complicates the circuit analysis at high frequencies where all
the transistor parasitics need to be taken into account. Thus, a single-transistor, commonsource configuration is chosen, as shown in Figure III.14 (a).
Choice of Load Impedance

Figure III.15 shows the load line of the output stage. For linearity considerations, the
transistor is only operated in saturation and cut-off regions. The load-line theory requires
the following equation to be met
RL =
2
vds0
2Pout
(III.29)
56
VDD
VGG0
v out
v d0
v g0
M0
ZL
Output
matching
network
R50
V PP
Mp
(a)
Output
matching network
v g0
v d0
v out
gm0eqv vgs0
Cg0tot
Rds0
RL
R50
Cd0tot
(b)
Figure III.14: Output stage. (a) Schematic. (b) Simplified linear model for first-order
analysis. The Miller effects of Cgd0 are included in Cg0tot and Cd0tot .
ID
Saturation Region
Vg0max
VGG
Vd0min
VDD
VDS
Figure III.15: Load line of the output stage.
57
where Pout is the output power delivered to the load and vds0 is the amplitude of the drainsource voltage signal. vds0 is related with the supply voltage VDD by
vds0 = VDD Vds0min .
(III.30)
Here, Vds0min is the minimum drain voltage. Since Vds0min is on the boundary between the
triode and saturation region, as shown in Fig. III.15, we have
Vds0min = Vgs0max VTn
= VGG0 VTn + vgs0
(III.31)
where VGG0 is the gate bias voltage and vgs0 is the amplitude of the gate voltage signal.
Substituting (III.31) and (III.30) into (III.29) gives
RL =
(VDD (VGG0 VTn ) vgs0 ))2

.
2Pout
(III.32)
In the actual design, Vds0min is chosen to be slightly larger than (III.31) to include a
small margin voltage Vm . In other words,
Vds0min = VGG0 VTn + vgs0 + Vm .
(III.33)
Thus, the final expression for RL is

(VDD vgs0 V )2
RL =
2Pout
(III.34)
V = VGG0 VTn + Vm .
(III.35)
where
58
Choice of Device Width
It can be shown as follows that the choice of device width, W0 , is equivalent to the
choice of vgs0 . As illustrated in Fig. III.14 (b), the equivalent transconductance of the output
stage is defined as
gm0eqv =
vds0
.
vgs0 RL
(III.36)
Here, Rds0 is much larger than RL , thus ignored. For a general class-AB operation, gm0eqv is
a complicated function of the gate bias, VGG0 , and the signal amplitude, vgs0 ; but for an ideal
class-B operation, as illustrated in Fig. III.16 (a), gm0eqv is one half of the transconductance
because the signal conducts exactly a half period. Thus, we have
gm0eqv =
Id
gm0
.
2
(III.37)
Id
VGG
VT
0
VGS
vgs
(a)
VGS
vgs
(b)
Figure III.16: Plots of Id versus VGS for (a) an ideal class-B operation, and (b) a shortchannel device biased near the threshold voltage.
59
For hand calculation purposes, the short-channel device that is biased near the threshold voltage can be approximately treated as the ideal class-B case, as shown in Fig. III.16 (b).
When the gate voltage signal is large enough, the carrier velocity is saturated and the
transconductance of a short-channel MOS device is
gm0 = W0 Cox vscl
(III.38)
where W0 is the device width, Cox is the oxide capacitance per unit area, and vscl is a
constant called the scattering-limited velocity [3]. Substituting (III.36) and (III.38) into
(III.37) and rearranging gives
W0 =
2vds0
.
Cox vscl vgs0 RL
(III.39)
Substituting (III.34) into (III.39), we have

W0 =
4Pout
Cox vscl vgs0 (VDD vgs0 V )
(III.40)
Here, Cox and vscl are constants; Pout and VDD are fixed by the design specifications; V is
a function of VGG0 and defined in (III.35). Thus, (III.40) shows that if the gate bias VGG0 is
fixed, W0 is only a function of vgs0 , proving our claim that the choice of W0 is equivalent
to the choice of vgs0 .
It is worth mentioning that (III.40) is highly simplified and only for hand calculations.
The actual design should take all non-ideal effects into account and use simulations for final
verifications.
The choice of vgs0 (or W0 ) involves a variety of tradeoffs. With respect to linearity,
small vgs0 is preferred because the third-order nonlinearity is proportional to the cube of
60
input signal amplitude. But as shown in (III.40), small vgs0 corresponds to a large device
width, which causes the increase of all the device parasitics, thus making the design of the
matching networks more challenging. Large vgs0 can alleviate the parasitic problems, but
will deteriorate the linearity. In our design, we found that the choice of a vgs0 of 0.6 V and
device width of 6 mm is a good compromise among all these tradeoffs.
On-chip Output Matching Network

The lack of high Q inductors is a major limitation in the design of an on-chip matching network. It is illustrative to first derive the power loss of a simple L-match network
with respect to the finite inductor quality factor, QL . Figure III.17 shows the schematic and
equivalent circuit of a simple on-chip, high-pass, L-match network, where RLs models the
parasitic resistance of the on-chip inductor. The goal of the matching network is to match
Rp to Rs .
Let Qt represent the total Q of the network, and assuming Q2t 1, we have
Q2t =
Rp kRLp
1
=
1
1
Rs
+
Rs
Rp QL L
1
1
1
+
2
Qt0 QL Qt
(III.41)
where Qt0 is the total Q of the network when the inductor is lossless, i.e.,
r
Qt0 = Qt |QL =
Rp
.
Rs
(III.42)
61
L
Rp
Rs
RLs
(a)
C
Rs
RLp
Rp
(b)
Figure III.17: High-pass, L-match network. (a) Schematic. (b) Equivalent circuit.
62
Rearranging and solving (III.41) gives
Qt =
Q2t0 +
p
Q4t0 + 4Q2L Q2t0
.
2QL
Assuming Qt0 2QL , (III.43) is then simplified to
Qt0
Qt Qt0 1
.
2QL
(III.43)
(III.44)
Define loss as the ratio of the power dissipated in the on-chip inductor to the power
delivered to Rp , i.e.,
loss =
Rp
Rp
Rp
Q2t0
=
=
.
=
RLp
QL L
QL Qt Rs
QL Qt
(III.45)
Substituting (III.44) into (III.45) gives

loss
Qt0
t0
=
Qt0
QL
QL 1
2QL
Qt0
1+
.
2QL
(III.46)
Again, we assume Qt0 2QL . For a matching network of Qt0 = 3 and QL of 10, (III.46)
gives 0.35, which implies that the power loss in the on-chip inductor is approximately 35 %
of the power dissipated at the load. The same conclusion can be obtained for a low-pass,
L-match network as well.
Note that if two matching networks are cascaded together, as shown in Fig. III.18,
the total power loss ratio is
loss, cascade =
PL1 + PL2
PL1 PL2
+
= loss, 1 + loss, 2
PRp
PRi
PRp
(III.47)
Here, we assume that PRi PRp , and Q2t0,1 and Q2t0,1 are much larger than one. The total
Qt0 for a cascade structure is
r
Qt0 =
Rp
=
Rs
Rp
Ri
Ri
= Qt0,1 Qt0,2 .
Rs
(III.48)
63
Lossy
L-match
network
1
Rs
Lossy
L-match
network
2
Rp
Figure III.18: Cascade of two lossy L-match networks.

Substituting (III.48) into (III.47) and rearranging gives
loss, cascade
1
=
QL
Qt0
1
Q2t0
2
Qt0,1 +
+
Qt0,1 + 2
.
Qt0,1
2Q2L
Qt0,1
(III.49)
(III.49) implies that the total power loss is minimized when

Qt0,1 = Qt0,2 =
Qt0
(III.50)
and the resulting minimum total power loss ratio of a cascaded structure is

Qt0
2 Qt0
min(loss, cascade ) =
1+
.
QL
2QL
(III.51)
The same approach can be applied to a cascade structure of more than two matching networks, and the same conclusion can be drawn, as long as the Q2t0 for each stage is much
larger than one. Comparing (III.51) with (III.46), we conclude that a cascade structure of
two on-chip matching networks can reduce the total inductor loss when the total Qt0 is
larger than four.
Let us return to the design of output matching network. The output impedance of
M0 is approximately Rds0 in parallel with Cd0tot , as shown in Fig. III.14 (b). The output
64
RL
Cd0tot
RL
R50
Cd0tot
(a)
R50
(b)
Cb0
RL
Lo1
RLo1s
L0
Cd0tot
Co2
RL0s
R50
C0
(c)
Figure III.19: Output matching networks. (a) High-pass L-match. (b) Low-pass L-match.
(c) Actual implementation.
65
matching network is required to match 50 to an impedance of RL in parallel with an
inductive impedance (to cancel Cd0tot ). In this case, RL = 8 and Cd0tot = 9.6 pF, so the
load impedance to be matched is RL k( sC1d0tot ), which results 4.3 + 4j.
Since the total Qt0 of the output matching network is less than 4, there is no benefits
to cascade more than one L-match networks. If the on-chip inductors have a constant QL of
10, the matching topologies in Fig. III.19 (a) and (b) yield power loss ratios (with respect
to the load power) of 38 % and 56 %, respectively, which are close to the 38 % predicted
by (III.46). The final output matching network is chosen as Fig. III.19 (c), where Lo1 and
Co1 match 50 to 8 , and L0 and C0 cancels Cd0tot . The power and efficiency loss ratio
associated with this matching network is approximately 36 %, slightly better than the 38 %
of the matching network in Fig. III.19 (a).
III.4.2 Driver Stage

Roles of Driver Stage
In a linear two-stage PA shown in Fig. III.13, the driver stage plays two roles. First,
it provides a linear voltage drive with the desired signal magnitude to the output stage.
Second, it exhibits an input impedance of 50 to the signal source. The first role of the
driver stage is very crucial for not only the gain but also the linearity of the power amplifier. This can be seen as follows: assuming that, for some reasons (e.g., mismatch in the
interstage matching network), the driver stage can not provide enough signal to the output
stage, then M1 has to be overdriven to reach the desired signal magnitude. Consequently,
66
this overdrive can enforce M1 into nonlinear regions and degrade the linearity of the PA.
Design of Interstage Matching Network

The input impedance exhibited by the output stage can be approximately modelled
as a small resistor in series with a large capacitor, as shown in Fig. III.20 (a), where Rg0tot
models the total parasitic gate resistance and Cg0tot models the total gate capacitance, which
includes the PMOS gate capacitance and the Miller capacitance contributed by Cgd0 . The
output impedance of the driver stage is modelled as the channel-length-modulation resistance, Rds1 , in parallel with the total drain capacitance, Cd1tot . According to the maximum
power transfer theorem, the input impedance of the output stage should be matched to the
complex conjugate of the output impedance of the drive stage to achieve a maximum power
dissipation at Rg0 , thus the largest voltage swing at Cg0tot . However, this theorem is established based on the assumption that the matching network is lossless, which is not valid for
on-chip matching. In fact, the loss of on-chip inductors is a major limitation in designing
an on-chip interstage matching network.
Since on-chip inductors occupy a large amount of chip area3 , the minimum number
of inductors is preferred; in this case, only one inductor is employed. It can be shown that
the inductor should be connected in a parallel configuration, as shown in Fig. III.20 (a),
where Cb1 is a dc blocking capacitor for separating the gate bias of the output stage from
the drain bias of the driver stage.
3
The SiGe5AM design guide recommends a minimum distance of 80 m between any on-chip inductors
and adjacent conductors, thus a large amount of chip area is consumed.
67
Cb1
Rg0tot
L1
g m1 vgs1
Rds1
Cd1tot
Cg0tot
RL1s
Lossy interstage
matching network
Driver stage
Output stage
(a)
g m1v gs1
Rds1
R L1p
L1
C tot
QC R g0tot
(b)
Figure III.20: Interstage matching network. (a) Circuit implementation. (b) Equivalent
model. Here, Cd1tot is ignored, and Ctot represents the total capacitance of Cb1 in series with
Cg0tot .
68
Our goal is to find the optimum values of L1 and Cb1 to achieve the maximum power
transfer to Rg0tot under the constraint of a finite QL of L1 . Let Ctot represent the total
capacitance of Cb1 in series with Cg0tot ,
Ctot =
1
1
+
Cb1 Cg0tot
1
(III.52)
and QC be the quality factors of Ctot , i.e.,

1
QC =
Rg0tot Ctot
(III.53)
Assuming that QL and QC are much larger than one and Cd1tot is much smaller than Cg0tot ,
thus ignored, Fig. III.20 (a) can then be simplified to (b), where
RL1p = QL L1 .
(III.54)
The power transferred to Rg0tot is

PRg0tot =
1
1
1
Rds1 + QL L1 + Q2 Rg0tot
C
2
2
gm1
vgs1
+j
. (III.55)
2
1
1 2
Q Rg0tot
QC Rg0tot L1 C
To minimize the denominator of (III.55), we first partially differentiate it with respect to

L1 , it can be shown that L1 should approximately satisfy
L1
QC Rg0tot
.
(III.56)
Thus, (III.55) reduces to

2
2
gm1
vgs1
.
PRg0tot =
2
QC
1
1
Rds1 + QL Rg0tot + QC Rg0tot Rg0tot
(III.57)
69
Then let the derivative of the denominator in (III.55) with respect to QC be zero, the optimum QC is calculated as
s
QC =
Rds1
.
Rg0tot
(III.58)
Note that (III.58) gives us the same conclusion as in the lossless matching case. Cb1 and
L1 can then be calculated from (III.53) and (III.56), respectively.
If Cd1tot is not ignored, it can be shown that (III.53) and (III.56) will be changed to
QC Rg0tot
(1 + QC Rg0tot Cd1tot )
v
u
1
u
QC = u
1
Cd1tot
t
Rg0tot
+
Rds1
QL
L1
(III.59)
(III.60)
The estimated model parameters of the driver and output stages are shown in Table III.1, where M1 is biased at VGG1 = 0.9 V and has a width of 3 mm. If QL is 15,
(III.59) and (III.60) gives L1 = 0.26 nH and Cb1 = 300 pF. Due to the parasitic inductance
of large on-chip capacitors, at 1.95 GHz, the maximum allowable on-chip capacitor (50 pF
calculated by size) exhibits the same impedance as an ideal 200 pF, thus used for Cb1 . L1
is implemented using a microstrip line, which does provide a Q of 15.
Driver stage
gm1 ( ) Rds1 () Cd1tot (pF)
0.28
76
4.2
1
Output stage
Rg0tot () Cg0tot (pF)
0.25
22.6
Table III.1: Estimated model parameters of driver and output stages.
70
III.4.3 Strategy for Ground Connections

Figure III.21 shows the simplified schematic and linear model of a two-stage CMOS
class-AB power amplifier. In the initial design phases, all the ground nodes (A, B, C, D, s1 ,
and s0 ) of the PA are assumed to be ideal ground. In practice, however, these nodes have
to be connected through bonding wires to an external ground (e.g., the bottom plane of a
two-layer printed circuit board). Although bonding wires exhibit only nanohenry inductances, they can significantly influence the gain and stability of a power amplifier at radio
frequencies, as shown later in this section. Thus, a good strategy for ground connections is
crucial.
Impact on Gain
It is illustrative to examine the impact of the ground bondwire inductor on the gain of
output stage in Fig. III.21. When biased at VGG0 = 0.85 V, M0 has the estimated device parameters of gm0 = 0.43, Rg0tot = 0.25, Cg0tot = 22.6 pF, and Cd0tot = 9.6 pF. At 1.95 GHz,
the transconductance and input and output impedances of M0 are
gm0 = 0.43
zg0 = Rg0 +
zd0 =
(III.61a)
1
= 0.25 3.7 j
jCg0
1
= 8.5 j.
jCd0tot
(III.61b)
(III.61c)
As implied in [3], the bondwire inductor Ls0 at the source node of M0 behaves as a seriesseries feedback. Assuming Ls0 is 0.1 nH and ignoring the effect of Cgd0 , the Ls0 feedback
71
VDD
VDD
RF
choke
RF
choke
Cb0
L o1
Vout
L1
C f1
Cb2
Co1
M0
R f1
L i1
Vin
M1
C i1
C0
Rb0
C1
On-chip
2f termination
s0
Rb1
VGG0
VGG1
C
Cdc
V PP
s1
On-chip
2f termination
L0
Cb1
L s1
L s0
Mp
Compensation
circuitry
(a)
C f1
R f1
Cb2
Vin
Rs
C i1
L i1
C gd1
Cgs1
Cb1
L1
Cds1
s1
A
On-chip
2f termination
Cgs0
C1
L s1
Cb0 L o1
C gd0
Cds0
L0
Co1
RL
C0
s0
Vout
L s0
On-chip
2f termination
(b)
Figure III.21: Two-stage CMOS class-AB power amplifier for illustrating ground connections. Part (a) shows the schematic, and part (b) shows the simplified linear model.
Here, the bias resistance and channel-length-modulation resistances of the transistors are
not shown.
72
transforms the transconductance and input and output impedances to
0
gm0
gm0
= 0.34 0.18 j
1 + gm0 jLs0
(III.62a)
0
zg0
zg0 (1 + gm0 jLs0 ) = 2.2 3.5 j
(III.62b)
0
zd0
zd0 (1 + gm0 jLs0 ) = 4.5 8.4 j.
(III.62c)
Here, the prime represents the feedback operation.

Special attentions need to be paid to the increased real parts of both the input and
output impedances in (III.62). As described in the design of driver and output stages, the
real parts of zg0 and zd0 play crucial roles in the interstage and output matching networks
and should be minimized to avoid significant gain and efficiency losses. Thus, (III.62)
implies huge losses in the matching networks even the ground bondwire inductance is as
small as 0.1 nH. The same conclusions can be drawn for the driver stage as well.
To alleviate this problem, we can connect all the critical ground nodes internally before connecting them to the external ground, as shown in Fig. III.22 (a). The benefit of this
connection is that the internal matching networks are less affected by the ground impedance
since they share the same internal ground node. Fig. III.23 shows the simulated power
gain of the two-stage CMOS class-AB PA versus the total ground bondwire inductance for
the two ground configurations shown in Fig. III.22 (a) and (b), respectively. As can be seen,
connecting the ground nodes internally can make the gain of the PA much more tolerant to
the ground bondwire inductance.
It is worth mentioning that 0.1 nH is a reasonable estimation for ground bondwire
inductance. Assuming 20 bonding wires are equally used for the grounding at s1 and s0 in
73
VDD
VDD
RF
choke
RF
choke
Cb0
L o1
Vout
L1
C f1
Cb2
L i1
L0
Cb1
Vin
M1
C1
Rb1
C i1
Co1
M0
R f1
C0
Rb0
On-chip
2f termination
VGG0
VGG1
Cdc
s0
On-chip
2f termination
V PP
Mp
L s0
Compensation
circuitry
(a)
VDD
VDD
RF
choke
RF
choke
Cb0
L o1
Vout
L1
C f1
Cb2
L i1
L0
Cb1
R f1
Vin
M1
Rb1
C i1
Co1
M0
C1
C0
Rb0
s0
On-chip
2f termination
VGG0
Cdc
VGG1
On-chip
2f termination
V PP
s1
L s1
L s0
Mp
Compensation
circuitry
(b)
Figure III.22: Two-stage CMOS class-AB PAs for illustrating the impact of ground connections on gain. (a) Ground nodes are connected internally together. (b) Ground nodes
are connected separately.
74
30
POWER GAIN (dB)
25
20
15
10
5
0
Ground configuration (a)

Ground configuration (b)
0
0.05
0.1
0.15
0.2
TOTAL GROUND BONDWIRE INDUCTANCE (nH)
Figure III.23: Power gain of the two-stage CMOS class-AB power amplifiers versus total
ground bondwire inductance for the two ground configurations shown in Fig. III.22 (a)
and (b), respectively.
Fig. III.21 and each bonding wire is 0.5-1 nH, if mutual inductances among the bondwire
inductors are ignored, both Ls0 and Ls1 will be 0.05-0.1 nH, which is consistent with our
0.1 nH estimation.
Impact on Stability
In addition to the impact on gain, ground connections also play an important role in
power amplifier stability. Two techniques gain their popularity in stability analysis. The
first is the root-locus technique, which involves calculation of the poles and zeros of the
amplifier and of their movement in the s plane as the low-frequency, loop-gain magnitude
is changed. This technique is widely used in analog circuit designs in solving feedbackinduced stability problems. At microwave frequencies, however, it is often difficult to
identify the feedback loops that cause the circuit to become unstable. Under this circum-
75
stance, the second technique Stern stability factor K is usually employed. K is defined
as
K=
1 + ||2 |S11 | |S22 |2

2|S21 ||S12 |
(III.63)
where = S11 S22 S12 S21 . If K > 1 and < 1, the circuit is unconditionally stable, i.e.,
it does not oscillate with any combination of source and load impedances as long as their
real parts are positive. However, a disadvantage of using K factor is that the S parameters
of the circuit must be calculated (or measured) for a wide frequency range to ensure that
K remains greater than unity at all frequencies. Thus, a great deal of effort is involved,
and most importantly, little insight can be obtained. It is also worth noting that K is a
pessimistic measure of stability since it allows arbitrary source and load impedances.
In our investigation of PA stability, the following criterion [28] is examined. If the
determinant of a linear network contains any zeros in the right half plane (RHP), the
network will be unstable, otherwise the network is stable. This criterion is equivalent
to the pole analysis of a linear network [28].
The ground configurations are divided into two categories: one-chip-ground and twochip-ground, as shown in Fig. III.24. The first is defined as the configurations where s1 and
s0 are joined together before connecting to the external ground; the latter is defined as those
where s1 and s0 are connected independently to the external ground. Table III.2 lists all the
possible ground configurations.
Since oscillations start from noise, the small-signal equivalent models in Fig. III.25
were used for the one-chip-ground and two-chip-ground configurations, respectively. Nodal
76
VDD
VDD
RF
choke
RF
choke
Cb0
L o1
Vout
L1
C f1
Cb2
L i1
R f1
M1
C0
Rb0
C1
On-chip
2f termination
Rb1
C i1
Co1
M0
Vin
VGG0
VGG1
C
Cdc
s0
On-chip
2f termination
L0
Cb1
V PP
Mp
L s0
Compensation
circuitry
(a)
VDD
VDD
RF
choke
RF
choke
Cb0
L o1
Vout
L1
C f1
Cb2
L i1
M1
C1
Rb1
C i1
C0
Rb0
s0
On-chip
2f termination
VGG0
VGG1
On-chip
2f termination
Co1
M0
R f1
Vin
L0
Cb1
C
Cdc
V PP
s1
L s1
L s0
Mp
Compensation
circuitry
(b)
Figure III.24: Two-stage CMOS class-AB power amplifier for (a) one-chip-ground and (b)
two-chip-ground configurations.
77
C f1
R f1
Cb2
Vin
Rs
L i1
C gd1
Cb1
Cgs1
C i1
L1
Cds1
C1
On-chip
2f termination
Cb0 L o1
C gd0
Cgs0
Cds0
L0
Co1
RL
C0
s0
Vout
On-chip
2f termination
L s0
(a)
C f1
R f1
Cb2
Vin
Rs
C i1
L i1
C gd1
Cgs1
Cb1
L1
Cds1
s1
A
On-chip
2f termination
Cgs0
C1
L s1
Cb0 L o1
C gd0
Cds0
L0
Co1
RL
C0
s0
Vout
L s0
On-chip
2f termination
(b)
Figure III.25: Small-signal equivalent model of the two-stage CMOS class-AB power amplifier for (a) one-chip-ground and (b) two-chip-ground configurations.
78
Ground
One-chip-ground Two-chip-ground
configuration
configurations
configurations
index
A B C D
A B C D
0
0 0 0
0
0 0 0
0
1
0 0 0 s0
0 0 0 s0
2
0 0 s0 0
0 0 s0 0
3
0 0 s0 s0
0 0 s0 s0
4
0 s0 0
0
0 s1 0
0
5
0 s0 0 s0
0 s1 0 s0
6
0 s0 s0 0
0 s1 s0 0
7
0 s0 s0 s0
0 s1 s0 s0
8
s0 0 0
0
s1 0 0
0
9
s0 0 0 s0 s1 0 0 s0
10
s0 0 s0 0
s1 0 s0 0
11
s0 0 s0 s0 s1 0 s0 s0
12
s0 s0 0
0
s1 s1 0
0
13
s0 s0 0 s0 s1 s1 0 s0
14
s0 s0 s0 0
s1 s1 s0 0
15
s0 s0 s0 s0 s1 s1 s0 s0
0 represents the external ground.
Table III.2: Ground configurations for the two-stage CMOS class-AB PAs in Fig. III.24.
79
analysis [28] was employed to calculate the determinant of each ground configuration in
Table III.2, and the resulting determinant is a high-order polynomial with coefficients expressed by the circuit parameters, including the total ground bondwire inductance Lstot . It
is apparent that Lstot is equal to Ls0 for one-chip-ground configurations and 12 Ls0 for twochip-ground configurations if we let Ls1 = Ls0 . Then Lstot was swept from zero to 4 nH4
to find its maximum that is capable of keeping all the roots of the determinant polynomial
in the left half s plane. This value, as defined by the stability criterion, sets the upper
limit of the ground bondwire inductance to avoid oscillation. Figure III.26 shows the calculated maximum stable ground bondwire inductance of the two-stage CMOS class-AB
PA for the ground configurations in Table III.2. As can be seen, the stability of the twostage power amplifier is strongly dependent on how the ground nodes were connected: one
unappropriate connection could make a stable PA oscillate. It is also shown that, for our
case, most of one-chip-ground configurations have better stability performance than their
two-chip-ground counterparts.
To verify our analysis, transient simulations based on the schematic in Fig. III.21 (a)
were carried out using SPECTRE. Again, for each ground configuration, the total ground
bondwire inductance was swept to find the value that began to make the transient waveforms unstable. Then it was recorded and compared with the value predicted by the calculation. Less than 10 % difference between the calculated and simulated Lstot were obtained
for all ground configurations, proving the validity of our analysis.
4
The value of 4 nH is arbitrarily chosen. In fact, any value can be chosen as long as it is much larger than
the typical ground bondwire inductance.
80
MAXIMUM STABLE INDUCTANCE (nH)
4
One chip ground
Two chip grounds
3
10
15
GROUND CONFIGURATION INDEX
Figure III.26: Maximum stable ground bondwire inductance of the two-stage CMOS classAB PA for the ground configurations in Table III.2. The plot does not show the data points
exceeding 4 nH.
III.4.4 Final PA Schematic

In order to make the gain and stability of the power amplifier less sensitive to the
ground bondwire inductance, our analysis in the previous section suggests that the ground
configurations with index numbers of 12 and 15 in Table III.2 should be used.
For comparison purposes, three PAs were fabricated: PA1 is the uncompensated and
fully integrated version, which means that all the matching (input, interstage, and output)
is on-chip; PA2 is also fully integrated but with the compensation circuitry applied; PA3
is the same as PA2 except that its output matching was off-chip. Figure III.27 shows the
schematic of the three PAs that were designed and implemented.
81
V DD
V DD
RF
Choke
Onchip
interstage
matching
Cb2
L i1
Cb0
L o1
V out
L1
Cf1
Onchip
input matching
Onchip
output matching
(PA1 and PA2 only)
RF
Choke
L0
Cb1
Co1
M0
Rf1
C0
V in
M1
C1
Rb0
Rb1
V GG0
V GG1
s0
Ci1
Onchip
2f termination
Onchip
2f termination
Cdc
V PP
Mp
L s0
Compensation
circuitry
(PA2 and PA3 only)
Equivalent
bondwire inductance
Figure III.27: Schematic of the fully matched two-stage CMOS class-AB power amplifiers.
82
III.5 Layout Design

As CMOS circuits evolves to low-voltage, high-speed, high-complexity systems, it
is well recognized that layout could heavily influence and limit the circuits performance.
Crosstalk, parasitics, and substrate coupling are just a few examples of such issues that arise
from the layout design. Tradeoffs are usually necessary under these circumstances. For example, increasing the width of an interconnection metal can reduce its parasitic resistance,
but will inevitably raise its crosstalks with other signal paths.
RF power amplifiers, especially those for medium or high power applications, require
special attentions in layout designs due to their involvements with both high frequencies
and large currents. First, layout parasitics, which are usually ignored at low frequencies,
can play important roles at high frequencies and significantly influence the PA performance.
Second, the widths of metals that flow large dc or/and ac currents should be carefully
determined to avoid current overloads. Finally, due to large voltage swings and low coupling impedances, an integrated PA can inject large noise currents into the substrate and
corrupt adjacent circuit blocks, thus methods for reducing substrate coupling are necessary.
In this section, the IBM SiGe5AM technology is first briefly described, followed by
the key layout issues of basic transistor cells and on-chip inductors. Then the choices of
routing metals are discussed and the current handling capability of the critical components
is examined. Finally, methods for reducing substrate coupling are discussed and our strategy for the substrate connections is presented.
83
III.5.1 IBM SiGe5AM Technology

The IBM SiGe5AM is a high-performance SiGe BiCMOS process. The CMOS part
is developed based on an existing high-yield, 0.5 m digital CMOS technology5 , but includes analog components such as polysilicon resistors, metal-insulator-metal (mim) capacitors, and on-chip inductors. One characteristic of SiGe5AM technology is its thick
Analog Metal (AM) layer, which significantly improves the Q of on-chip inductors by reducing the associated series resistances.
Table III.3 shows the properties of all metal layers provided by the IBMs SiGe5AM
technology (4 metal option), where tox represents the dielectric thicknesses between metal
layers and the substrate/N-well. As can be seen, AM layer has best parasitic and currenthandling performances.
Table III.3: Properties of metal layers in IBM SiGe5AM technology.
Metal layer Thickness Rsheet a
tox
Idc b
Irms b
ID
(m)
(/) (m)
(mA)
(mA)
p
M1
0.63
0.076
2.34 0.74 W p51.2 W (W + 1.6)
M2
0.85
0.045
4.17 1.23 W p41.6 W (W + 3.6)
MT
0.85
0.045
6.22 1.23 W p 41.6 W (W + 3.6)
AM
4.00
0.00725 10.05 6.17 W
69.0 W (W + 10.9)
a
b
sheet resistances at 25 C.
current limits at 100 C.
III.5.2 Basic Transistor Cell

For power amplifier applications, power transistors have to be laid out to reduce
not only their parasitic resistances but also their parasitic capacitance at both gate and
5
The details are described in the SiGe5AM design guide.
84
Drain
Gate
Substrate

Diffusion
Polysilicon
M1 & M2
AM
Contact
Source
Figure III.28: Layout (not scaled) of a basic transistor cell. The fingers are 20 m long.
drain nodes. Figure III.28 shows our layout of a basic transistor cell. First, the two ends
of gate fingers were connected together to reduce the gate resistance by a factor of four.
Second, M1 and M2 were combined to connect both drain and source not only to reduce
their parasitic resistances but also to increase their current handling capabilities. Third, the
substrate were connected to the source for each transistor cell, thus keeping the substrate
voltage equally distributed in the whole transistor. To reduce the parasitic resistance and
capacitance, both the gate and drain were routed through the top metal layer AM.
III.5.3 On-chip Inductor

The SiGe5AM design guide recommends all on-chip inductors be placed at least
80 m away from substrate contacts to avoid coupling of inductor energy into the substrate.
It is shown through measurements that large substrate contacts adjacent to an inductor
85
may result in a 10-15 % degradation of the inductors quality factor Q. The disadvantage
associated with this design rule is an enormous waste of chip area. Therefore, it is advised
that inductors should be used as little as possible during the initial design phase.
Since an on-chip inductor has a maximum width of 25 m, it should not be used for
passing through a large amount of current. The initial design should be carried out with
this in mind.
III.5.4 Current Handling Capability

Since a large amount of current flows through a power amplifier, and each metal layer
has a different current handling capability for a certain width, it is necessary to determine
which metal(s) is to be used for routing and its (their) minimum width(s). If chip area is
not a concern, the ground buses can be made as wide as possible since they contribute no
parasitic capacitances; the width of the signal paths, on the other hand, need to be properly
chosen for tradeoffs between parasitic shunt capacitance and parasitic series resistance. In
our design, the combination of M1 and M2 was used for all the ground routings, and AM
was chosen for most crucial signal paths. Table III.4 shows the comparison between the
maximum allowable layout currents and the corresponding maximum designed currents of
all critical components in PA2. Note that since every component has more than one node,
and each node is routed through multiple metal layers, the maximum allowable layout
currents were considered for all critical metal layers.
86
Table III.4: Comparison between maximum allowable layout currents and corresponding
maximum designed currents of all critical components in PA2.
Critical
Layout
Design
components Metal ID Metal width Idc
Irms
Idc
Irms
(m)
(A) (A)
(A) (A)
M1&M2
160
0.32 2.22
D
0.26 0.45
AM
75
0.46 0.67
M0
G
AM
40
N/A 0.37 N/A 0.09
S M1&M2
160
0.32 2.22 0.26 0.45
MT
40
N/A 0.22
L0
N/A 0.19
AM
20
N/A 0.21
MT
40
N/A 0.22
Lo1
N/A 0.18
AM
20
N/A 0.21
MT
50
N/A 0.27
Co1
N/A 0.20
AM
20
N/A 0.21
III.5.5 Substrate Coupling

In integrated implementations, a PA resides on the same substrate as other circuit
blocks (some of them may be very sensitive), as shown in Fig. III.29, where M0 represents
the PA transistor. Due to large voltage swings at the drain node, M0 will inject a large
amount of current into the substrate via the drain-bulk capacitance Cdb0 , thus corrupting
the adjacent sensitive circuit blocks.
Various methods, such as differential topology, ground shielding, guardrings, and
deep trench, were developed to reduce the substrate coupling. Among these approaches,
differential topology requires an off-chip balun, which makes the PA not only less costeffective but also more difficult to integrate. The ground shielding method reduces substrate
noise, but increases both parasitic capacitance and layout complexity; the latter is due to the
extra routing of the shielding planes. Therefore, only the last two methods were employed
87
VDD
L d0
M0
VDD
Cdb0
M2
PA
Distributed
Substrate
Model
M1
Sensitive
Circuits
Lb
(a)
L d0
PA
p+
n+
M0
M1
n+
n+
Cdb0
Sensitive
Circuits
n+
Cdb1
p - substrate
(b)
Figure III.29: Effect of substrate coupling. (a) Schematic modelling. (b) Sideview of
device layouts.
88
Large Substrate
Guardrings
L s0
PA
p+
Small
Bondwires
M0
n+
M1
n+
p+
Cdb0
p+
n+
Sensitive
Circuits
n+
Cdb1
p - substrate
Deep Trench
Blocks
Figure III.30: Layout structure employing both large substrate guardrings and deep trench
blocks.
in our design. First, large areas of substrate guardrings were used to encompass all the
power transistors since they are the primary sources of substrate noise. Second, multiple
deep trench blocks were placed at the boundary of the power amplifier to further increase
the isolation between the PA and other circuit blocks. The layout structure employing these
two methods is illustrated in Fig. III.30.
III.5.6 Final PA layout

Figure III.31 shows the final layout of PA2. To be consistent, the components are
labelled using the same names as in Fig. III.27. Due to its small value (0.26 nH), L1 is
implemented using a microstrip line and modelled as a small inductor. To minimize ground
impedance, multiple ground pads were used.
89
Figure III.31: Final Layout of the fully integrated and compensated two-stage CMOS PA
(PA2). The components are labelled using the same names as in Fig. III.27.
90
III.6 Experimental Results

This section begins with a detailed description of some important PA implementation
issues such as the choice of package and the design of off-chip matching networks. Then
the test setup for evaluating the PAs is presented. Finally, the measurement results are
shown and the PA performance is summarized.
III.6.1 Implementation Details

IC Implementation
Figures III.32 shows the die microphotograph of PA2. Including bonding pads, the
chip occupies an area of 2.0 1.6 mm2 .
Figure III.32: Die microphotograph of the fully integrated and compensated two-stage
CMOS PA (PA2).
91
Package Choice
The Amkor MicroLeadFrame (MLF) package was chosen primarily for its enhanced
thermal and electrical characteristics. It is a plastic encapsulated and leadless package
where electrical contact to the PCB is made by soldering the lands on the bottom surface of
the package to the PCB. The enhanced thermal and electrical properties of the MLF package is achieved by incorporating an exposed die paddle on the bottom, which efficiently
conducts heat to the PCB and provides a stable ground through down bonds and electrical
connections through conductive die attach material. Figure III.33 shows the photograph
and cross section drawing of the MLF package.
(a)
(b)
Figure III.33: MLF package (a) photograph and (b) cross section drawing.
There is a variety of options in choosing the size and lead numbers of the MLF
package. In order to relax the handling and soldering issues, the final package was chosen
to have a large profile of 6 6 mm2 and a total of 20 leads (5 on each side).
92
Printed Circuit Board Choice
The PA evaluation board utilizes a two-layer RO4350 with a dielectric constant of
3.48 and a dielectric thickness of 20 mil. In addition to good dimensional stability and low
processing and assembly costs, RO4350 provides excellent high-frequency performance
due to its low dielectric loss and stable electrical properties over frequency. The low thermal
coefficient of the dielectric constant of RO4350 also makes it suitable for PA applications.
Off-chip Matching Networks

Before discussing the details of the off-chip matching networks, a note should be
made regarding the interstage matching of the two-stage CMOS PAs. As described in
Sec III.4, the total gate capacitance of the output stage of compensated PAs is approximately 22.6 pF and at 1.95 GHz, the corresponding matching inductor is roughly 0.26nH.
To achieve a high Q, this small inductor was implemented using a long microstrip line,
as shown in Fig. III.31. Due to the long routing of this inductor line, the interconnection
yields a parasitic inductance of more than 0.05 nH, which shifts the resonating frequency
of the interstage LC matching network from 1.95 GHz to approximately 1.75 GHz. In order to acquire the designed gain and efficiency performance, both off-chip input and output
matching networks were employed for all three PAs and the measurements were carried
out at 1.75 GHz instead of 1.95 GHz. However, this slight modification does not impact
our conclusions or the generality of our results.
The off-chip output matching network for PA3 was implemented using L-match
93
L bw
TL 1
C1
TL 2
TL 3
ZL
L1
R50
(a)
TL 1
TL 2
C1
TL 3
L bw
Zs
Z in
C2
(b)
Figure III.34: Hybrid off-chip matching network for PA3. (a) Output. (b) Input.
94
topology, as shown in Fig. III.34 (a). Here, Lbw models the output bondwire inductance,
TL1, TL2, and TL3 model the transmission line effects of the connection traces. Since
ZL is very small (approximately 4 + 4j), any slight imperfections in the matching network
could influence the value of ZL and consequently degrade the gain and efficiency of the
output stage. It can be shown that, for the output matching network in Fig. III.34, the imaginary part of ZL is most sensitive to the variations of the matching components. Thus, it
is very desirable to design the matching network to be capable of continuously tuning the
imaginary part of ZL . If TL1 and TL2 is short enough, adjusting the length of TL1 or TL2
can achieve the continuous tuning of the imaginary part of ZL , while keeping the real part
of ZL approximately unchanged. Since changing the length of TL1 involves physically
cutting the TL1 trace, tuning the length of TL2 is preferable, and this is accomplished by
designing the impedances of TL2 and TL3 as 50 and sliding L1 along the trace of TL2
and TL3.
The values of the matching components were first calculated in MATHEMATICA and
further verified and tuned using Agilent ADS. Figure III.35 shows the ADS schematic and
simulated ZL of the output matching network for PA3. Due to the large size of the package, the output bonding wire has a length of more than 1.5 mm and exhibits approximately
1.8 nH.
Considering the uncertainty of the bondwire inductance and the variations of the actual values of chip capacitors and inductors, it is necessary to tune the output matching
networks in conjunction with the exhibited testing phenomena. Since the output matching
95
(a)
(b)
Figure III.35: Off-chip output matching network for PA3 in ADS. (a) Schematic. (b) Simulated ZL .
96
is the load-line matching instead of maximum power matching, optimizing the gain (|s21 |)
does not necessarily imply optimized load matching. To still achieve the optimum load
matching, the gain and dc current for various output power levels were observed and compared with the SPECTRE simulations, and corresponding adjustments were made in the
output matching network until good agreement was obtained. Since we only need to tune
the value and position of L1 , few iterations were needed before the optimum output match
was achieved.
After the output matching network was implemented, the input matching network
can be designed by first measuring the input impedance and then matching it with any
matching structure. Figure III.34 (b) shows our input matching network for PA3. Again,
Lbw models the input bondwire inductance, TL1, TL2, and TL3 model the transmission
line effects of the connection traces.
The final application schematic is shown in Fig. III.36, where the 47 F capacitors at
VDD1 and VDD0 are for bypassing the ac signals to ground. This is very important not only
for stability considerations, but also for linearity concerns. As illustrated in Section III.3.2,
the out-of-band (the sub-harmonic frequencies, in this case) impedance can dramatically
impact the PA linearity. As expected, the measurements showed that the inclusion of these
two capacitors can significantly improve both linearity and stability of the PA. Any value
can be chosen for these two capacitors as long as they provide good ac short at the subharmonic frequencies. The photograph of the PCB implementation of PA3 is shown in
Fig. III.37.
97
VDD1
47uF
VDD0
47uF
10nH
10nH
MLF
5.6nH
Die
RF in
2.0pF
1.3pF
RF out
1.3pF
Bias
circuit
VGG1 VGG0 V B1 V B2 VPP
Figure III.36: Application schematic of PA3.
Figure III.37: Photograph of the PCB implementation of PA3.
1.5nH
98
III.6.2 Test Setup

The test setup for evaluating the PAs is shown in Fig. III.38. The grounds of all the
test equipments and the PA were connected together. Since all the matching networks have
been implemented on the PC board, the input was directly connected to an Agilent E4438C
vector signal generator, and the output was directly fed to an Agilent E4440A PSA series
spectrum analyzer. The input and output signals are connected via two 50 SMA RF
cables, each of which has a loss of 0.3 dB. Two Agilent 6612C DC power supplies were
used for VDD1 and VDD0 to monitor the independent current consumptions by the driver
and output stages. To obtain direct access to the bias voltages, all the biases were directly
connected to power supplies.
Power supplies
Agilent 6612C
Spectrum analyzer
Agilent 6612C
Agilent E4440A
Signal generator
Agilent E4438C
VDD1
VDD0
PA
HP E3610A
...
...
HP E3610A
Power supplies
Figure III.38: Test setup for evaluating the PAs. The ground connections of the test equipments and the PA are not shown.
99
III.6.3 Measurement Results

The power amplifiers were operated at a VDD of 3.3 V and drew a total quiescent
current of 97 mA (46 mA for the driver stage and 51 mA for the output stage) when the
output stages were biased at 0.8 V.
Gain and Efficiency

Figure III.39 shows the measured gain and power-added efficiency (PAE) of the three
PAs. As can be seen, the uncompensated and fully integrated PA (PA1) achieves a smallsignal gain of 24.3 dB and a peak PAE of 23 % at the designed output power of 24 dBm.
PA2 achieves similar PAE performance but with a gain of 3 dB lower than PA1. PA3 has
better gain and efficiency performance than PA2 because of the low-loss, off-chip output
matching. It achieves a small-signal gain of 23.9 dB and a PAE of 29 % at the output power
of 24 dBm.
35
35
PA1
PA2
PA3
30
25
25
20
20
15
15
10
10
0
5
10
15
20
25
PAE (%)
GAIN (dB)
30
0
30
OUTPUT POWER (dBm)
Figure III.39: Measured gain and power-added efficiency versus output power of the three
PAs. The output stages of the PAs are all biased at 0.8 V.
100
The measured results were compared with those from SPECTRE simulations and
good agreement was obtained. Figure III.40 shows the simulate and measured gain and
power-added efficiency (PAE) for for the three PAs.
Linearity
To verify their linearity performances, the PAs were tested under various bias and
power levels using both two-tone and WCDMA signals. Figures III.41 show the measured third-order intermodulation, adjacent-channel leakage power (ACP1), and alternatechannel power (ACP2) for the three PAs. As can be seen, the compensated PAs (PA2 and
PA3) have much better linearity than the uncompensated PA (PA1) for various gate biases
and a wide range of output power; in addition, the IM3 measurements show similar trends
as those shown in Fig. III.5 of Section III.2 C.
PA3 achieves an ACP1 of -35 dBc and ACP2 of -55 dBc at a carrier output power of
24 dBm, which is compliant with the 3GPP-WCDMA ACP requirements of -33 dBc and
-43 dBc [29], respectively. Due to the loss of on-chip output matching, PA1 and PA2 can
only meet the WCDMA ACP requirements at output powers of 22 and 23 dBm, respectively. Figure III.42 shows the measured WCDMA spectra of PA1 and PA2 at a carrier
output power of nearly 20 dBm.
It is worth mentioning that all the bias voltages utilized in our measurements are
almost exactly the designed values; in addition, no oscillation was observed during the
entire measurement procedure, even when both the source and load were disconnected.
101
40
40
Simulation
Measurement
35
30
30
25
25
20
20
15
15
10
10
0
5
10
15
20
25
PAE (%)
GAIN (dB)
35
0
30
OUTPUT POWER (dBm)
(a)
40
40
Simulation
Measurement
35
30
30
25
25
20
20
15
15
10
10
0
5
10
15
20
25
PAE (%)
GAIN (dB)
35
0
30
OUTPUT POWER (dBm)
(b)
40
40
Simulation
Measurement
35
30
30
25
25
20
20
15
15
10
10
0
5
10
15
20
25
PAE (%)
GAIN (dB)
35
0
30
OUTPUT POWER (dBm)
(c)
Figure III.40: Simulated and measured gain and power-added efficiency versus output
power for (a) PA1, (b) PA2, and (c) PA3. The output stages of the PAs are biased at 0.8 V.
102
PA1
PA2
PA3
MEASURED IM3 (dBc)
20
30
40
50
5
10
15
20
25
30
25
30
25
30
OUTPUT POWER (dBm)
(a)
MEASURED ACP1 (dBc)
20
PA1
PA2
PA3
30
40
50
10
15
20
OUTPUT POWER (dBm)
(b)
MEASURED ACP2 (dBc)
40
PA1
PA2
PA3
50
60
70
5
10
15
20
OUTPUT POWER (dBm)
(c)
Figure III.41: Measured (a) IM3 , (b) adjacent-channel leakage power, and (c) alternatechannel power versus peak-envelope output power for the three PAs. The output stages of
the PAs are all biased at 0.8 V.
103
Figure III.42: Measured WCDMA spectra of PA1 and PA2 at a carrier output power of
nearly 20 dBm. The output stages of the PAs are both biased at 0.8 V.
Table III.5 compares the performance of recently reported linear power amplifiers
for handset applications. As can be seen, although a CMOS PAs peak efficiency is generally lower than its GaAs HBT (FET) counterpart, if properly linearized, it can effectively
be used as a low-cost alternative, especially for low-supply voltage and medium-power
applications.
III.7 Summary
The nonlinear gate-source capacitance is a dominant source of distortion that may
limit the linearity of CMOS class-AB power amplifiers. Improved performance can be
obtained by using a compensating nonlinearity, provided by the gate-source capacitance of
an appropriately biased and sized PMOS device placed alongside the NMOS device that
provides the class-AB amplification. Simulations and experiments show that the method
can improve both the two-tone, third-order intermodulation and adjacent-channel leakage
104
Table III.5: Performance comparison of recently reported linear power amplifiers for handset applications.
Ref.
Technology
Pout
PAE
(dBm)
Su 98
CMOS
[30]
0.8 m
Giry 00
CMOS
[31]
0.35 m
Yen 03
CMOS
[32]
0.25 m
This work
CMOS
(PA3)
0.5 m
Vintola 01
AlGaAs/GaAs
[33]
HBT
Jager 02
InGaP/GaAs
[34]
HBT
Srirattana 03
GaAs
[35]
FET
28
33 %
Gain
[Signal]
VDD
Freq.
Operating
(dB)
ACPR @ Pout
(V)
(MHz)
class
[NADC]
836
N/A
-30 dBc @ 28 dBm

23.5
35 %
24.6
20
28 %
11.2
[PDC]
AB
(linearized)
2.5
1910
AB
2.5
2450
AB
-55 dBc @ 21.5 dBm

[/4 DQPSK]
-28 dBc @ 18 dBm
24
29 %
23.9
[WCDMA]
(linearized)
3.3
1750
-35 dBc @ 24 dBm

>24
>27 %
>30
[WCDMA]
AB
(linearized)
3.5
1950
AB
N/A
1950
AB
N/A
1950
Doherty
-36 dBc @ 26 dBm

27
38 %
22.6
29.7
46 %
8.5
[WCDMA]
-37 dBc @ 27 dBm
[WCDMA]
-38 dBc @ 28.6 dBm
3-stage
power by approximately 8 dB. While meeting the 3GPP-WCDMA ACP requirements, the
linearized two-stage amplifier is capable of delivering an output power of 24 dBm with a
small-signal gain of nearly 24 dB and a power-added efficiency of 29 %.
Chapter IV
Dynamic Biasing Technique
IV.1 Introduction
Efficient power amplifiers are highly desirable in mobile wireless communication
systems to prolong battery life. Meanwhile, spectrally efficient modulation schemes in
many wireless standards result in signals with highly time-varying envelopes, thus imposing a stringent linearity requirement on the employed power amplifiers to preserve modulation accuracy and limit spectral regrowth.
To achieve the linearity requirement, PAs are generally operated in class-A or classAB modes. Although class-A and AB power amplifiers have reasonable maximum efficiencies (theoretical 50% for A and 50-78.5% for AB), they suffer significant efficiency
degradation if operated at low power levels. For example, the efficiency of a class-A amplifier is in proportion to the output power, Pout , and this results in a maximum of only
0.5 % when Pout is backed off 20 dB. This efficiency degeneration at low power levels
deserves special attentions, if taking into account the statistical nature of power usage in
wireless communication systems. As exemplified in [36], despite the maximum of 0.5 W,
the output power in a IS-95-CDMA system has the most probable value of only 1 mW,
105
106
yielding an extremely low PA efficiency.
Various techniques [36]-[37] were developed to improve PA efficiency at low power
levels. The dynamic biasing technique described in [37] is most appropriate for IC implementation. This technique uses the envelope of the input signal to dynamically control the
gate dc bias voltage of the power amplifier, thus reducing the current consumption of the
amplifier at low power levels. Since the previously designed two-stage CMOS class-AB
power amplifier exhibits good linearity and maximum efficiency, we would like to explore
the utility of the dynamic biasing technique on our class-AB PA.
This chapter will begin with a brief description of the dynamic biasing technique.
Then it will be followed by the detailed analysis of the envelope detector circuit. The
average efficiency improvement and distortion impact of the technique will be discussed
successively. Finally, the experimental results of a prototype amplifier will be presented
and conclusions will be drawn.
IV.2 Dynamic biasing Technique

IV.2.1 Basic concept
Figure IV.1 (a) shows the block diagram of the dynamic biasing technique proposed
by Saleh [37]. The envelope of a sample of the input RF signal is first detected, and then
is used to dynamically control the gate bias voltage. This is done such that the bias voltage
is forced to be proportional to the signal envelope. To realize an IC implementation, the
107
schematic in Figure IV.1 (b) is used. Here, the envelope detector is directly connected to
the with the input of the output stage. Since the input impedance of the output stage of the
PA is much larger than that of the envelope detector (ED), the inclusion of the ED does not
influence the RF signal performance.
VDD
RF in
Directional
coupler
FET
Envelope
detector
RF out
Gate bias
control
(a)
VDD
RF in
VDD
Driver
Gate bias
control
Output
Envelope
detector
RF out
Gate bias
control
(b)
Figure IV.1: (a) Conceptual block diagram and (b) actual implementation of the dynamic
biasing technique.
108
IV.2.2 Response of Envelope Detector

The input of the envelope detector is a narrow-band RF voltage signal with a timevarying envelope. Since the signal itself contains no envelope-frequency components, nonlinear operation is necessary to yield the envelope signal. This is accomplished by feeding
the RF signal to a nonlinear device, such as a diode. Since the output contains not only the
envelope, but also the RF components, a low-pass filter should be included at the output.
The simplified schematic of the designed envelope detector is shown in Fig. IV.2 (a).
Here, Cbp provides the dc block; VGGP controls the gate bias for the PMOS device Mp ;
the large capacitor C1 is used to remove the RF signals at the envelope-detector output.
The gate-bias-control circuit for the output stage consists of a voltage divider, R1 and R2 ,
and an isolation resistor, R3 . The equivalent large-signal model of the envelope detector
is shown in Fig. IV.2 (b). Here, Cgp models the total gate capacitance of Mp ; Isdp (t) is the
source-drain current of Mp , where the subscript sdp represents that the direction of the
PMOS current is from source to drain. The PA input can be approximately modelled as a
capacitor, as shown later in this section. The calculation procedure of the envelope-detector
response for a two-tone input signal is described as follows.
First, the voltage signal at the gate of Mp is
Vgp (t) = VGGP + A(cos 1 t + cos 2 t)

d
t cos c t
= VGGP + 2A cos
2
(IV.1)
109
V B0
VDD
C bp
Vgp(t)
R1
Mp
R3
Venv (t)
Rb1
Vin(t)
C1
VGGP
R2
Envelope
detector
PA input
Z PA
Gate bias
control
PA input
(a)
C bp
Vin(t)
PA input
R3
Vgp(t)
Cgp
Isdp (t)
C1
R1
Low-pass filter
R2
Venv (t)
C PA
PA input
(b)
Figure IV.2: Envelope detection and gate-bias-control circuit. (a) Schematic. (b) Equivalent large-signal model.
110
where d and c represent the angle frequencies of the envelope and carrier, i.e.,
d = 1 2
(IV.2)
1 + 2
2
(IV.3)
c =
and A is the tone amplitude.
To obtain the transient response of the envelope detector, Fourier transform of Isdp (t)
should be first calculated. However, Isdp as a function of Vgp depends on the current characteristics of Mp . In the following calculations, we will derive the Fourier transform of Isdp (t)
for a long-channel device and an ideal linear device, respectively. Then we will show that
the implemented device exhibits approximately long-channel current characteristics for the
gate-voltage range we are interested. In the analysis, all the devices are assumed at ideal
class-B biases.
Fourier Transform of Isdp (t)

a) Ideal long-channel device
The source-drain current as a function of VSG for a long-channel PMOS device is
kp (VSG + VTp )2
VSG > VTp
ISDP =
(IV.4)
0
VSG VTp
where
p Cox p
kp =
2
W
L
(IV.5)
p
111
and the channel-length modulation effect is ignored because only a small envelope
voltage amplitude will appear at the drain of the PMOS device.
To simplify our analysis, the envelope period (Td ) is chosen as a multiple of the
carrier period (Tc ), i.e., Td = (2M + 1)Tc , where M is an integer and much larger
than one. This is shown in Fig. IV.3.
Isdp(t)
T
- __d
2
...
t -m-1
t -m
...
Tc
__
2
...
tm
tm+1
...
Tc
__
2
time
Td
__
2
Figure IV.3: Source-drain current of Mp as a function of time.
Assuming an ideal class-B bias, we have

VDD VGGP = VTp .
(IV.6)
Substituting (IV.1) and (IV.6) to (IV.4) and since c is much larger than d , we have
the drain current for one carrier period as
4kp A2 cos2
tm cos2 c t
2
Isdp (t)
(tm
Tc
)
4
t<
(tm +
Tc
)
4
t < (tm+1
(tm +
Tc
)
4
Tc
)
4
(IV.7)
112
Since Isdp (t) is conveniently chosen as an even function with the period of Td , it can
be expanded to the following Fourier series:
a0 X
Isdp (t) =
+
an cos(nwd t)
2
n=1
(IV.8)
where
Z
2
an =
Td
Td
2
Td
2
Isdp (t) cos(nd t) dt.
(IV.9)
Among all the frequency components, we are only interested in those near the envelope frequency (including some of the envelope harmonics) because all the RF
frequency components will be removed by the low-pass filter. The calculation of a1
is shown here:
2
a1 =
Td
Td
2
Td
2
Isdp (t) cos(d t) dt
Z
!
M
tm + T4c
2 X
4kp A2 cos2 ( tm ) cos(d tm ) cos2 (c t) dt

Tc
Td m=M
2
tm 4
Z Td
2
d
2kp A2
cos2 ( t) cos(d t) dt
=
T
Td
2
2d
=
kp A2
.
2
(IV.10)
a0 can be calculated as
a0 = kp A2 .
(IV.11)
For the rest of envelope harmonics,

2kp A2
an
Td
Td
2
Td
2
cos2 (
d
t) cos(nd t) dt = 0
2
(IV.12)
113
where n = 2, 3, ..., and
nd c .
(IV.13)
It can be shown from (IV.10) to (IV.12) that the envelope component of the longchannel PMOS current for a two-tone input signal is
isdp (t) =
kp A2
(1 + cos d t).
2
(IV.14)
b) Ideal Linear Device

The source-drain current for an ideal linear PMOS device is
kp0 (VSG + VTp )

VSG > VTp
ISD =
0
VSG VTp
(IV.15)
where kp is a constant. The same approach can be applied, and it can be shown that
the current envelope component of the ideal linear PMOS device is directly proportional to the input envelope signal amplitude, i.e.,
0
2kp A
d
cos t.
idsp (t) =
(IV.16)
c) Actual Device
The gate length of the PMOS device for the envelope detector is chosen as 0.5 m,
thus it is possible that the device current exhibits short-channel characteristics. At
low gate-bias voltages, such as in the class-B case, a short-channel device still exhibits long-channel characteristics. To verify this claim, we fitted the SPECTRE
114
simulated PMOS current data using the square function in (IV.4) and the linear function in (IV.15). The fitting was carried out for the gate voltage between 2.0 and 2.9
V. Figure IV.4 shows the SPECTRE simulated, the square-function fitted, and the
linear-function fitted curves, respectively. As can be seen, the square function can
fit the current very well in the voltage range we are interested. Thus, the employed
PMOS can be approximately modelled as a long-channel device.
10
SPECTRE DATA
Curvefit (square)
Curvefit (linear)
ISD (mA)
6
4
2
0
2
1.9
2.1
2.3
2.5
2.7
2.9
3.1
3.3
GATE VOLTAGE (V)
Figure IV.4: SPECTRE simulated and MATLAB fitted PMOS source-drain current versus
gate voltage. The two fitting functions are those in (IV.4) and (IV.15), respectively. The
fitting was carried out for the gate voltage between 2.0 and 2.9 V.
Low-pass Filter Transfer Function

To find the transfer function of the low-pass filter in Fig. IV.2 (b), we need to first
calculate the impedance exhibited by the power amplifier to the gate-bias-control circuit.
The two-stage CMOS PA design is described in the previous chapter, and the schematic is
shown in Fig. IV.5. Since the impedances of L1 and all the RF chokes are very small at the
envelope frequency, they are equivalent to ac ground. Thus, the input of the two-stage
115
VDD
VDD
RF
choke
RF
choke
VGG0
L1
C f1
Cb2
L i1
Vout
C1
Cb1
PA
input
M0
R f1
Vin
M1
Rb1
C i1
On-chip
2f termination
Cdc
VGG1
On-chip
2f termination
V PP
Mp
Compensation
circuitry
Figure IV.5: Schematic of the designed two-stage CMOS power amplifier.

PA is approximately the total gate capacitance of M0 in parallel with the dc blocking
capacitor Cb1 , i.e.,
CPA Cgs0 + Cgb0 + Cgd0 + Cb1 .
(IV.17)
The transfer function of the low-pass filter is then

G(s) =
Venv (s)
R1,2
=
Isdp (s)
1 + sC1 R1,2 + sCPA (R3 + R1,2 + sC1 R3 R1,2 )
(IV.18)
where R1,2 represents the total resistance of R1 in parallel with R2 . Note that the low-pass
filter will introduce both magnitude distortion and phase delay. To minimize these effects,
C1 , R1 , R2 , and R3 should be chosen as small as possible to maximize the frequency
of the dominant pole in (IV.18). However, to isolate the influence of the bias circuitry
on the PA RF path and minimize the current consumption, R1 , R2 , and R3 should be
116
maximized. In addition, to remove the RF frequency components at the envelope detector
output, C1 should be maximized. Therefore, tradeoffs in these regards have to be made. In
our implementation, C1 is chosen as 30 pF, R1 and R2 are chosen as 200 , R3 is 100 ;
the input of the PA is approximately 76 pF. This yields the two poles of the low-pass filter
as 9.4 and 117.6 MHz, respectively.
Final Output Envelope Signal

Assuming all the RF components will be removed by the low-pass filter, the output
voltage of the envelope detector is
Venv (t) =
R2
a0
VB0 + R1,2 + a1 |G(jd )| cos(d t + G(jd ))
R1 + R2
2
+ a2 |G(j2d )| cos(2d t + G(j2d )) +
(IV.19)
where G(j) represents the phase delay introduced by the low-pass filter. Since the
PMOS device we used exhibits long-channel current characteristics, we can substitute
(IV.10)-(IV.12) to (IV.19). This gives
Venv (t) =
R2
kp A2
VB0 +
[R1,2 + |G(jd )| cos(d t + G(jd ))].
R1 + R2
2
(IV.20)
For envelope frequencies much less than 9.4 MHz (the dominant pole of the low-pass filter),
(IV.20) reduces to
Venv (t)
kp A2
R2
VB0 +
R1,2 (1 + cos d t).
R1 + R2
2
(IV.21)
Here, the first term is the initial bias voltage set by the gate-bias-control circuit, as shown
in Fig. IV.2 (b); the second term is the output envelope signal. As can be seen, the output
117
envelope signal is proportional to the square of the input envelope signal amplitude. This
is due to the square relationship between the source-drain current and the gate voltage of
the long-channel PMOS device.
For illustration purposes, Fig. IV.6 shows the approximate time-domain waveforms
of Vgp (t), Isdp (t), and Venv (t). The waveforms are not scaled.
IV.3 Efficiency Improvement

The drain-efficiency improvement of the dynamic biasing technique was derived as
a closed-form expression in [37] for an ideal class-A FET amplifier. For an amplifier operating in class-AB mode, closed-form expressions cannot be obtained due to the nonlinear
relationship of the current of the class-AB device with the input voltage. Therefore, numerical calculations were employed to estimate the efficiency improvement of the dynamic
biasing technique.
IV.3.1 Drain Efficiency for Single-tone Input

The drain-source current IDS (VGS , VDS ) for a short-channel NMOS transistor as a
function of VGS and VDS can be approximately modelled as
k(VGS VTn )2
(1 + VDS )
1 + (VGS VTn )
IDS =
VGS > VTn

(IV.22)
VGS VTn
The I V curve of the employed device can be obtained from the SPECTRE simulator
for the VGS and VDS ranges where the device will be operated. Using the MATLAB least-
118
Vgp(t)
V GG0
time
(a)
Isdp(t)
time
(b)
Venv(t)
Isdp(t)
envelope
Output
envelope
time
(c)
Figure IV.6: Approximate time-domain waveforms of (a) input gate voltage, (b) sourcedrain current of Mp , and (c) output voltage of the envelope detector for a two-tone test
signal. The dashed lines in (a) and (b) are the corresponding signal envelopes. The dashed
line in (c) is the envelope of Isdp (t) for illustrating the delay of the ED output.
119
square curvefit function, we can fit (IV.22) to the device I V data with appropriate
coefficients of k, , and .
The single-tone input voltage signals for the fixed and dynamic biasing schemes are
Vgs (t) = VGG + A cos(c t + )
(IV.23)
Vgs (t) = VGG + vENV (A) + A cos(c t + )
(IV.24)
and
respectively, where A stands for the RF signal amplitude. The corresponding drain current
is
Ids =
k(Vgs VTn )2
(1 + Vds )
1 + (Vgs VTn )
Vgs > VTn
Vgs VTn
(IV.25)
To simplify our calculation, the Ids dependence on Vds was eliminated by approximating
Vds as a superposition of the dc bias and the purely linear part of the output signal:
Vds = VDD gv vgs = VDD gv A cos(c t + )
(IV.26)
where gv , the voltage gain of the amplifier at the fundamental frequency, can be estimated
from first-order simulations. Substituting (IV.23), (IV.24), and (IV.26) to (IV.25), Ids (t) can
be derived.
The dc and fundamental components of the drain current can be obtained by ap-
120
plying Fourier-series transforms to (IV.25)
IDD
1
=
T1
2
io =
T1
T1
2
T1
2
T1
2
Ids (t) dt
(IV.27)
Ids (t) cos(c t) dt.
(IV.28)
T1
2
The drain efficiency of the amplifier is defined as
Peff
1 2
io RO
Pout
=
= 2
.
Pdc
VDD IDD
(IV.29)
Substituting (IV.22)-(IV.28) to (IV.29), we are able to calculate the drain efficiency of the
amplifier.
IV.3.2 Average Efficiency for Varying-envelope Signals

To properly estimate the average PA efficiency, it is necessary to account for the
probability distribution of the long-time power usage as a function of the output power
Pout [38] [36]. Let this probability density function be p(Pout ), the average efficiency is
defined as
hPout i
hPdc i
R
p(Pout )Pout dPout
= R 0
.
p(Pout )Pdc (Pout ) dPout
0
avg =
(IV.30)
Here, hPdc i is the average dc power consumed by the amplifier, which directly corresponds with battery energy consumption.
121
IV.4 Distortion Calculation

IV.4.1 IM3 Expression
To understand the impact of the dynamic biasing technique on the linearity of the
CMOS class-AB power amplifier, it is illustrative to analyze the two-tone, third-order intermodulation (IM3 ) of the PA using Volterra analysis. In general, Volterra analysis assumes each nonlinear element in a circuit can be described by a third-order, power-series
expansion in which the series coefficients depend only on the circuits bias point. As discussed in the previous chapter, such analysis cannot be directly applied to describe highly
nonlinear circuits, such as a class-AB power amplifier; but we can alleviate this problem
by employing power-series expansions of order greater than three, and by allowing the series coefficients to depend on both the bias point and the RF signal power. As previously
demonstrated, the major sources of nonlinearity for a NMOS device working in a class-AB
mode are the effective gate-source capacitance (Ceff ) and the drain-source current (idsn ), in
which the first one can be linearized by applying a capacitance-compensation technique.
Both of these two nonlinearities can be expanded to power series of the input gate-source
voltage vgs , i.e.,
2
3
4
Ceff = c1 + c2 vgs + c3 vgs
+ c4 vgs
+ c5 vgs
(IV.31)
2
3
+ g3 vgs
.
(IV.32)
and
122
It is important to reemphasize that when the bias point or RF signal power changes, the
coefficients (c1 through c5 and g1 through g3 ) also change, such that the expansions always
trace out the appropriate Ceff and idsn versus vgs curve.
The voltage signal at the gate of M0 , when the dynamic biasing technique is applied,
contains both RF and envelope components. Assuming the spacing of the two tones is
much less than the dominant pole (9.4 MHz) of the low-pass filter, from (IV.21), the gate
voltage signal of the output device, M0 , is
Vg0 (t) = A(cos 1 t + cos 2 t) +
=(
R2
kp A2
VGG0 +
R1,2 (1 + cos d t)
R1 + R2
2
R2
VGG0 + A2 ) + [A(cos 1 t + cos 2 t) + A2 cos d t]
R1 + R2
(IV.33)
kp
R1,2
2
(IV.34)
where
=
d = 1 2 .
(IV.35)
The first term in (IV.33) is the dc bias voltage, and the second term is the ac signal.
Note that this dc bias voltage varies with the input envelope amplitude, thus will have
impact on PA linearity. This will be discussed later in this section.
Substituting the ac signal in (IV.33) to (IV.32) gives
9
3
3
idsn = (g1 A + g3 A3 + g3 2 A5 ) cos(1 t) + g3 A3 cos((22 1 )t)
4
2
4
3
+ g2 A3 cos((22 1 )t) + g3 2 A5 cos((22 1 )t) +
4
3
g1 A cos(1 t) + ( g3 + g2 )A3 cos((22 1 )t) + .
4
(IV.36)
123
Cgdn
+
ZI
~
v gs, 21 2
c1
Ceff, 21 2
~
g1 v
gs, 21 2
dsn, 21 2
ZO
Figure IV.7: Circuit for the Volterra calculation.

As can be seen, the IM3 of idsn now consists of two terms: the first, 43 g3 A3 , comes from the
intrinsic current nonlinearity g3 ; the second, g2 A3 , arises from the currents second-order
nonlinearity g2 . Note that the even-order terms of Ceff are greatly reduced by applying the
capacitance compensation technique, thus their influence are ignored.
Based on the method of nonlinear currents [23], the circuit for the Volterra calculation is shown in Fig. IV.7. Here, ZI represents the impedance seen looking into the input
matching network from the NMOS gate when is = 0, and ZO represents the impedance
seen looking into the output matching network from the NMOS drain. It is worth mentioning that both ZI and ZO include short-circuit terminations at the second-harmonic frequency, as described in the previous chapter. The distortion currents generated by Ceff and
idsn have the following phasor amplitudes:
3
3
dsn,21 2 = ( g3 + g2 )
vgs,
1
4
and
Ceff ,21 2
1 3
5 5
= j(21 2 ) c3 vgs,
+ c5 vgs,
1
1
4
8
(IV.37)
(IV.38)
where vgs,1 is the phasor amplitude of the gate-source voltage at the fundamental fre-
124
quency. The distortion voltages that result at the gate and drain can then be computed using
the circuit of Fig. IV.7:
vds,21 2 =
ZO {dsn,21 2 [1 + j(21 2 )Cgdn ZI0 ] Ceff ,21 2 [g1 j(21 2 )Cgdn ]ZI0 }
1 + j(21 2 )Cgdn (ZI0 + ZO + g1 ZI0 ZO )
(IV.39)
where ZI0 ZI k c1 , and the impedances ZI0 and ZO should be evaluated at the intermodulation frequency 21 2 . The drain voltage at the fundamental frequency is also easily
found to be
vds,1 =
g1 ZO + j1 Cgdn ZO
vgs,1
1 + j1 Cgdn ZO
(IV.40)
where, in this case, ZO should be evaluated at the fundamental frequency 1 . The IM3 at
the drain are then simply
vds,21 2
.
IM3D = 20 log
vds,1
(IV.41)
IV.4.2 Estimation of g2 and g3

As described in the previous chapter, with the capacitance compensation technique,
idsn becomes the dominant source of nonlinearity for the two-stage CMOS class-AB PA.
Since (IV.37) shows that both g2 and g3 contribute to the idsn nonlinearity, it is beneficial to
first estimate these two polynomial coefficients. To be complete, we estimate g2 for three
devices: a long-channel class-A device, an ideal linear class-B device, and the implemented
class-AB device.
125
Estimation of g2
a) a long-channel class-A device
For a long-channel class-A device, g2 is in the same order of g1 , as illustrated in the
long-channel current expression:
Cox
ids (vgs ) =
2
Cox
=
2
W
L
W
L
(vgs + VGG VT )2
2
[(VGG VT )2 + 2(VGG VT )vgs + vgs
].
(IV.42)
The IDS versus VGS curve for such a device is illustrated in Fig. IV.8 (a). Comparing (IV.42) with (IV.32), we have
g2
1
=
.
g1
2(VGG VT )
(IV.43)
Typical values of (VGG VT ) for a CMOS class-A PA is in the range of 0.25 0.5 V,
which implies that g2 is approximately 1-2 times of g1 .
b) an ideal class-B device
For an ideal class-B device that has current characteristics shown in Fig. IV.8 (b),
g2 is also in the same order of g1 . Assuming the current can be expanded for three
terms, i.e.,
3
2
.
+ g3 vgs
(IV.44)
For an input signal of cos t, (IV.44) gives

idsn (t) = g1 cos t +
g2
cos 2t + .
2
(IV.45)
126
IDS
IDS
VT
VGG
VT
VGS
VGS
vgs
vgs
(a)
(b)
Figure IV.8: IDS versus VGS for (a) a long-channel class-A device, and (b) an ideal class-B
device.
In the meantime, the output current of an ideal class-B device is also
cos t
T4 < t T4
idsn (t) =
T
0
< t 3T
4
4
(IV.46)
Here, to simplify our analysis, we let the slope of the IDS versus VGS curve as unity.
Fourier expansion on (IV.46) gives
idsn (t) =
1
2
cos t +
cos 2t + .
2
3
(IV.47)
Comparing (IV.45) with (IV.47), we have

g2
8
=
.
g1
3
(IV.48)
Thus, for an ideal class-B device, g2 is approximately equal to g1 . Note that the above
derivations are only for the first-order estimation.
127
c) the implemented class-AB device
For a general class-AB device, g2 varies with the device characteristics, bias voltages,
and signal amplitude. In such cases, numerical calculations described in the previous
chapter is necessary. The ratio of g2 to g1 for the four gate bias voltages (0.75 0.90 V) of the implemented class-AB device is shown in Fig. IV.9 (a). As can be
seen, this ratio for most bias voltages and power levels are larger than one.
Estimation of g3
The estimation of g3 for a CMOS class-AB device is not straightforward. Again,
numerical calculations are employed, and it was found that g3 varies dramatically with
both the gate bias voltage, VGG0 , and the output power, Pout , as shown in Fig. IV.9 (b).
IV.4.3 Final IM3 Calculation

The maximum single-tone RF signal amplitude at the gate of M0 is designed as
0.60 V. Thus, the maximum tone amplitude (Amax ) for an input two-tone signal is 0.30 V. If
the gate bias voltage is designed to vary from 0.75 to 0.85 V, (IV.21) gives the peak-to-peak
value of Venv (t) as
2A2max = VGG0 |max VGG0 |min = 0.85 0.75.
(IV.49)
Thus, can be calculated. The output IM3 can then be calculated from (IV.37)(IV.41).
Figure IV.10 shows the comparison of the calculated and simulated load-voltage IM3 of
the designed CMOS class-AB PA with the dynamic biasing technique. As illustrated in
128
5
VGG0=0.75 V
VGG0=0.80 V
V
=0.85 V
GG0
VGG0=0.90 V
g2/g1
0
10
10
20
30
OUTPUT POWER (dBm)
(a)
g3/g1
VGG0=0.75 V
VGG0=0.80 V
V
=0.85 V
GG0
VGG0=0.90 V
1
10
10
20
30
OUTPUT POWER (dBm)
(b)
Figure IV.9: Ratio of (a) g2 and (b) g3 to g1 for the four gate bias voltages (0.75 - 0.90 V)
of the implemented class-AB device.
129
(IV.33), the dc gate bias voltage of M0 varies with the tone amplitude, A. Thus, each
swept A corresponds to a different set of power-series coefficients of Ceff and idsn , which is
obtained by performing the interpolations among the four sets of coefficients at VGG0 from
0.75 to 0.90 V.
LOADVOLTAGE IM3 (dBc)
20
40
60
Calculation (ED)
Simulation (ED)
80
10
20
30
OUTPUT POWER (dBm)
Figure IV.10: Comparison of the calculated and simulated IM3 of the load voltage at 21
2 versus peak-envelope output power. The gate bias is designed to vary from 0.75 V to
0.85 V.
Figure IV.11 shows the contributions to the load IM3 arising from g2 , g3 and Ceff
nonlinearities, as computed from (IV.37)(IV.41). The contribution from one nonlinearity
source is found by setting the other two to zero. As shown, the g2 nonlinearity limits the
load IM3 over a wide range of power levels.
130
20
40
60
g3 contribution
g contribution
2
Ceff contribution
80
10
20
30
OUTPUT POWER (dBm)
Figure IV.11: Contributions to the load-voltage IM3 from the g2 , g3 , and Ceff nonlinearities.
The values are computed from the Volterra expressions (IV.37)(IV.41), as described in the
text.
IV.5 Experimental Results

IV.5.1 IC Implementation
The power amplifier employed for the dynamic biasing technique is the PA3 described in the previous chapter (the envelope detector is disabled for the measurements at
that chapter). The implementation details, such as the off-chip matching design, can also
be found in that chapter. Figures IV.12 shows the die microphotograph of the PA3. The
ED block is the envelope detector circuit. Including bonding pads, the chip occupies an
area of 2.0 1.6 mm2 .
131
Figure IV.12: Die microphotograph of the highly integrated and compensated two-stage
CMOS PA (PA3). The ED block is the envelope detector circuit.
132
IV.5.2 Measurement Results

Envelope Detector Output
The output voltage of the envelope detector, Venv , is measured using a high definition oscilloscope. The PMOS device is biased at the class-B mode and the corresponding
envelope output varies from 0.75 V, when no input signal is applied, to 0.85 V, when the
output power reaches the designed maximum: 24 dBm. Figure IV.13 shows the calculated,
simulated, and measured Venv versus output power for a single-tone input. As can be seen,
our analysis accurately predicts the response of the envelope detector.
0.85
Venv (V)
0.83
Calculation
Simulation
Measurement
0.81
0.79
0.77
0.75
2
10
14
18
22
26
OUTPUT POWER (dBm)
Figure IV.13: Calculated, simulated, and measured Venv versus output power for a singletone input.
Gain and Efficiency

Figure IV.14 shows the measured gain and power-added efficiency (PAE) for PA3
when the dynamic biasing technique is applied, and PA3 when the dynamic biasing technique is disabled and the gate is biased at VGG0 = 0.85 V, respectively. As expected, the
133
dynamic biasing technique improves the PAs 1-dB compress point due to the increased
gate bias. However, this does not yield better linearity, as shown later in the linearity measurements.
35
35
VGG0=0.85 V
VGG0=dynamic
30
25
25
20
20
15
15
10
10
0
5
10
15
20
25
PAE (%)
GAIN (dB)
30
0
30
OUTPUT POWER (dBm)
Figure IV.14: Measured gain and power-added efficiency versus output power for PA3 with
the dynamic biasing technique, and PA3 when the envelope detector is disabled and the gate
is biased at VGG0 = 0.85 V, respectively.
Define the power consumption improvement as

=
Pdc, 0.85 V Pdc, dynamic

Pdc, 0.85 V
(IV.50)
where Pdc, 0.85 V and Pdc, dynamic represent the dc power consumption of PA3 when the
dynamic biasing technique is applied, and PA3 when the dynamic biasing technique is
disabled and the gate is biased at VGG0 = 0.85 V, respectively. Figure IV.15 shows the
measured power consumption improvement versus the PA output power. As can be seen,
the dynamic biasing technique can improve the power consumption by nearly 50 % for the
output stage and 30 % for the total two-stage.
POWER CONSUMPTION IMPROVEMENT (%)
134
60
Twostage
Output stage
50
40
30
20
10
0
5
10
15
20
25
30
OUTPUT POWER (dBm)
Figure IV.15: Measured power consumption improvement versus the PA output power.
Linearity
To verify its linearity performance, PA3 was tested using both two-tone and WCDMA
signals. Again, the testings were carried out for both biasing schemes. Figures IV.16 show
the measured IM3 , adjacent-channel leakage power (ACP1), and alternate-channel power
(ACP2). Figures IV.17 shows the comparison between the calculated and measured loadvoltage IM3 versus output power. As can be seen, a good agreement is obtained between
the calculations and the measurements, verifying our distortion analysis. The linearity
measurements also validate our claim that the dynamic biasing technique can introduce
significant nonlinearity into the CMOS class-AB PA.
Although more nonlinear, PA3 with the dynamic biasing technique can marginally
meet the 3GPP-WCDMA ACP requirements of -33 dBc and -43 dBc at the output power
of 24 dBm.
135
VGG0=0.85 V
V
=dynamic
20
MEASURED IM3 (dBc)
GG0
30
40
50
5
10
15
20
25
30
25
30
25
30
OUTPUT POWER (dBm)
(a)
20
MEASURED ACP1 (dBc)
VGG0=0.85 V
V
=dynamic
GG0
30
40
50
10
15
20
OUTPUT POWER (dBm)
(b)
40
MEASURED ACP2 (dBc)
VGG0=0.85 V
V
=dynamic
GG0
50
60
70
5
10
15
20
OUTPUT POWER (dBm)
(c)
Figure IV.16: Measured (a) IM3 , (b) adjacent-channel leakage power, and (c) alternatechannel power versus peak-envelope output power of PA3 for both biasing schemes.
136
Calculation
Measurement
LOADVOLTAGE IM3 (dBc)
20
30
40
50
5
10
15
20
25
30
OUTPUT POWER (dBm)
Figure IV.17: Comparison between the calculated and measured load-voltage IM3 versus
output power.
IV.6 Summary
The dynamic biasing technique can improve the efficiency of a CMOS class-AB
PA at low output power levels, as demonstrated by both calculations and experiments.
However, the envelope signal introduced by the dynamic biasing technique can significantly
limit the overall linearity of the CMOS class-AB PA, as verified by both Volterra analysis
and experimental results. Thus, further linearization methods are necessary to reduce this
nonlinearity.
Chapter V
Conclusions
Linearity and efficiency are the two most important characteristics of power amplifiers for wireless applications. In this dissertation, we investigate three topics on CMOS
power amplifiers: class-E, class-AB, and dynamic biasing technique.
Class-E power amplifier is a promising candidate for realizing high efficiency. Previous analytical efforts on class-E power amplifiers assumed either zero switch resistance
and/or infinite drain inductance, leading to less optimized design. In this dissertation, we
developed an improved design technique by accounting for both finite drain inductance
and finite on resistance for a CMOS device. This design technique expresses the circuit
parameters in terms of the device width and the design specifications, such as the output
power and operating frequency fc . A design example based on the developed algorithm
achieves an output power of 0.25 W and a drain efficiency of 87% for a 3.5 mm NMOS
class-E device with VDD = 2 V and fc = 1.90 GHz.
The intrinsic linearity obtained in a CMOS class-AB operation is often insufficient to
meet the stringent linearity requirement imposed by modern wireless standards. In this dissertation, we found that the nonlinear gate-source capacitance is a dominant source of distortion that limits the linearity of CMOS class-AB power amplifiers. A simple technique is
137
138
proposed to cancel this nonlinearity by using a compensating nonlinearity, provided by the
gate-source capacitance of an appropriately biased and sized PMOS device placed alongside the NMOS device that provides the class-AB amplification. Volterra analysis and
two-tone SPECTRE simulations were used to verify the technique. Prototype two-stage
CMOS class-AB power amplifiers were implemented. Experiments show that the amplifiers employing the compensation technique can improve both the two-tone, third-order
intermodulation and adjacent-channel leakage power by approximately 8 dB. When operated at VDD = 3.3 V, the final linearized power amplifier is capable of delivering an output
power of 24 dBm with a small-signal gain of nearly 24 dB and an overall power-added
efficiency of 29 %. At the designed output power of 24 dBm, the adjacent-channel leakage
power of the linearized amplifier is -35 dBc, meeting the 3GPP-WCDMA requirements
of -32 dBc. The experimental results also prove the feasibility of linear CMOS class-AB
power amplifiers for wireless communication systems.
Although the designed two-stage CMOS class-AB power amplifier exhibits good linearity and maximum efficiency, it still suffers serious efficiency degradation when operated
at low output power levels. This deserves special attentions considering the statistical nature of power usage in wireless communication systems: as exemplified in [36], the most
probable output power of a IS-95-CDMA system is only 1 mW, despite the maximum of
0.5 W. In this dissertation, it was demonstrated that a dynamic biasing technique can improve the efficiency of a CMOS class-AB power amplifier by controlling the gate bias
voltage with the envelope of input RF signal. However, the envelope signal introduced by
139
the dynamic biasing technique can significantly limit the overall linearity of the CMOS
class-AB PA, as verified by both Volterra analysis and experimental results. The prototype
power amplifier employing the dynamic biasing technique exhibited more than 6 dB worse
in IM3 and ACP performances than the one without the technique applied. Thus, further
linearization or compensation methods are necessary to reduce the nonlinearity introduced
by the dynamic biasing technique.
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UNIVERSITY OF CALIFORNIA, SAN DIEGO

CMOS Power Amplifiers for Wireless Communications

A dissertation submitted in partial satisfaction of the

The dissertation of Chengzhou Wang is approved, and it is

University of California, San Diego

To my parents and sisters

Signature Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii

Class-E Power Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

II.4.1 Validity of Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Linear CMOS Class-AB Power Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

IV Dynamic Biasing Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

IV.2.1 Basic concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Schematic and improved model of CMOS class-E power amplifier. . . . . . . .

Simplified models of CMOS class-AB power amplifiers. . . . . . . . . . . . . . . . .

III.37 Photograph of the PCB implementation of PA3. . . . . . . . . . . . . . . . . . . . . . . . 97

Comparison of Pout and Peff between theoretical prediction and HSPICE

B.S., Electronics, Beijing University, China

M.S., Electrical Engineering (Electronic Circuits & Systems),

ABSTRACT OF THE DISSERTATION

CMOS Power Amplifiers for Wireless Communications

Max. TX power (dBm)

TX duty ratio (%)

Peak-ave. ratio (dB)

cent current (mA)

I.1.2 Power Amplifier Classifications

I.2 Limitations of Sub-micron CMOS Technology

I.2.1 Low Breakdown Voltages

I.2.2 Low Transconductance-to-current Ratio

I.2.3 Low Substrate Resistivity

I.3 Dissertation Motivations

I.4 Dissertation Organization

II.2 Improved Class-E Analysis

II.2.2 Circuit Equations

Solving this equation gives

Solving this equation yields

where the coefficient C is a constant to be determined, and is defined as

iLon (t) t=(n+1)T

= iLoff (t) |t=nT

vdon (t) t=(n+1)T

= vdoff (t) |t=nT .

iLon (t) t=(n+1/2)T = iLoff (t) t=(n+1/2)T .

class-E conditions: The optimum class-E conditions are:

vdoff (t) t=(n+1/2)T

i2don (t)Ron dt.

Substituting (II.18), (II.19), and (II.21) into (II.20), we have

II.2.4 Component Evaluation

As shown in (II.3a), V the amplitude of v2 (t) is a function of Io , X, and RL ; in addition,

vd (t) sin(c t + 1 ) dt.

II.3 A Design Example

L1 (nH) L2 (nH) C2 (pF)

DRAIN EFFICIENCY (%)

OUTPUT POWER (W)

DEVICE WIDTH (mm)

II.4.2 Choice of Device Width

II.4.3 Relationship between Pout and VDD

II.4.4 Comparison with Previous Works

DEVICE WIDTH (mm)

DRAIN EFFICIENCY (%)

DEVICE WIDTH (mm)

III.2 Distortion Effects of the Gate-Source Capacitance

III.2.2 Capacitance Components

Cggn (ac simulation)

GATESOURCE VOLTAGE (V)