Introduction to Verilog HDL

with Quartus Prime

L.M.P.Villalba, C.B.Maghamil, A.J.W. Lomoya
Fourth Year, Bachelor of Science in Electrical Engineering

I. INTRODUCTION
Verilog is a Hardware Description Language; a
textual format for describing electronic circuits and
systems. Applied to electronic design, Verilog is
intended to be used for verification through
simulation, for timing analysis, for test analysis
(testability analysis and fault grading) and for logic
synthesis. The first version of the IEEE standard for
Verilog was published in 1995. A revised version
was published in 2001; this is the version used by
most Verilog users. SystemVerilog is a huge set of
extensions to Verilog, and was first published as an
IEEE standard in 2005.
The designers of Verilog wanted a language
with syntax similar to the C programming language.
Like C, Verilog is case-sensitive and has a basic preprocessor. Its control flow keywords are equivalent,
and its operator precedence is compatible with C, a
difference is that Verilog requires that variables be
given a definite size and consists of a hierarchy of
modules. Modules encapsulate design hierarchy,
and communicate with other modules through a set
of declared input, output, and bidirectional ports.
Sequential statements are placed inside a begin/end
block and executed in sequential order within the
block. However, the blocks themselves are executed
concurrently, making Verilog a dataflow language.
Subsets of statements in the Verilog language are
synthesizable. Verilog modules that conform to a
synthesizable coding style, known as registertransfer level or RTL, can be physically realized by
synthesis
software.
Synthesis
software
algorithmically transforms the abstract Verilog
source into a net list, a logically equivalent
description consisting only of elementary logic
primitives such as AND, OR, NOT, flip-flops, etc.,
that are available in a specific FPGA or VLSI
technology. Further manipulations to the netlist
ultimately lead to a circuit fabrication blueprint.
A type of Verilog that we will be using the
Quartus Prime Verilog, which is a software designed
by Intel. Quartus Prime design software includes
everything you need to design for Intel FPGAs,
SoCs, and CPLDs from design entry and synthesis
to optimization, verification, and simulation.
Dramatically increased capabilities on devices with
multi-million logic elements are providing designers
with the ideal platform to meet next-generation
design opportunities. For designers to effectively

take advantage of these devices, software must

dramatically increase design productivity. The new
Quartus Prime software, built on the successful
Quartus II software, is breaking barriers of FPGA
design productivity with an additional Spectra-Q
engine that is optimized for Arria 10 and future
devices. The Spectra-Q engine enables new levels of
design
productivity
for
next-generation
programmable devices with a set of faster and more
scalable algorithms, a hierarchical database
infrastructure, and a unified compiler technology.

II. OBJECTIVES
The objectives of this experiment are, first,
to understand the basic concepts of the Verilog
Hardware Description Language (Verilog
HDL) through the simulation and coding of
various digital logic circuits, second, to
synthesize coded circuits through Quartus
Primes register-transfer level (RTL), and
finally to compare the Verilog syntax similarity
to other programming languages.
III. CODE
NOT Gate
module notgate (i,o);
input i;
output o;
assign o = !i;
endmodule
AND Gate
module andgate (i1, i2, o);
input i1, i2;
output o;
assign o = i1 & i2;
endmodule
OR Gate
module orgate (i1, i2, o);
input i1, i2;
output o;
assign o = i1 | i2;
endmodule

XOR Gate
module xorgate (i1, i2, o);
input i1, i2;
output o;
assign o = i1 ^ i2;
endmodule

IV. DATA AND RESULTS

The Verilog Hardware Description
Language is very much the same with other
programming language such as C and C++
where they are based. The following Figure-1
a, b, c, and d are synthesized in Quartus Prime
using Verilog Hardware Description Language.
The code used to generate this is found in the
CODE section before.

(a)

(b)

(c)

(d)
Figure-1. (a) NOT, (b) AND, (c) OR, (d)
XOR.
With Verilog HDL, it is important to note
that there is a standard way of coding to adhere
to the conventions that are accepted by many.
V. ANALYSIS AND CONCLUSION
When making a module, first, module
must be declared followed by the module name.
The module name then must include in its
arguments the variables used in the module.

After module declaration, termination with

semi-colon ; must be done as same with C
and C++ languages. Declaration of designation
of variables then follows such as declaring
variable i as input and o as output. This will
tell Quartus that i is an input to a logic circuit
and o is an output. With all the variables
declared then, assigning the value of the output
based upon the input can then be done by first
declaring assign then followed by the
equations required and with the mathematical
and logical operators. Operator precedence
must be observed carefully since the hardware
synthesized depends upon the sequence of the
program. For Verilog, NOT is designated as a
tilde or exlamation point ~ or !, AND is
designated as an ampersand &, OR is
designated as pipe | , while XOR is
designated as a caret ^. Logical and
mathematical operators are not the same thus it
needs to be differentiated in assigning values.
Such as when using + instead of | if you
want OR function, the result will not be the
same for a mathematical operator will add two
variables while a logical operator will make a
boolean operations. After the function block is
declared, it is important to end the module with
endmodule command.
Figure 1 is the register-transfer level (RTL)
where the code is realized in a gate level
hardware. Quartus can also be used to code and
synthesize in transistor, gate, and silicon level
thus making it more versatile than other
softwares.
Programming the logic gates compared to
simulation software such as MultiSim also
gives a different disadvantage. For Verilog is
designing the hardware with gates and timing,
it is much easier to simulate it to MultiSim.
However, the advantage of Verilog is that it can
be uploaded into the hardware to perform the
logic circuit designed. With the coding syntax
and flow correct, the code can then be
synthesized in RTL and we can see the
hardware from our code.
In sum, Verilog HDL has syntax similar to
C language and that making gate level logic
circuit synthesis is easy, lastly, which we can
check and see the logic circuit after compilation
in the register transfer level.

VI. REFERENCE
Verilog. n.d.Wikipedia. Retrieved on
November 22, 2016.
https://en.m.wikipedia.org/wiki/Verilog
What is Verilog?.n.d.http://www.verilog.com
Intel Quartus Prime Design Software
Overview. Retrieved from
https://www.altera.com/products/designsoftware/fpga-design/quartusprime/overview.html.