PROJECT 3

Nagaraj Siddeshwara, Karthik Vijayakumar and Kalyan Pingali

Date: 12/09/16

EXECUTIVE SUMMARY
The aim of this project is to get familiarized with work with DE1-SoC that contains Altera Cyclone V
FPGA and ARM 9 processor. The project has 4 modules:
Module 1: The module introduces inputs and outputs that are on the DE1SoC. Using these a real time
clock is developed and used in Morse code communication.
Module 2: This deals with prompting the user to use ARM 9 HPS integrated with Cyclone V FPGA as a
multipurpose device using Assembly Level Programming on Altera Monitor Program 15.1. This involves
the effective use of interrupts and ARM Generic Interrupt Controller (GIC) where the HPS is
programmed as a Real Time Clock to display time in seconds and hundredth of a second, a counter with
constant speed, a Counter whose speed is decided by the user through KEYS[3:0].
Module 3: This deals with learning to communicate with HPS and FPGA fabric through AXI (Advanced
eXtensible Interface) bridge. It deals with generating an ARM execution file through Quartus Prime EDS
Suite 15.1 and operating LEDs on DE1-SoC.
Module 4: Here we are demonstrating the use of DE1SoC as the Embedded System built on the chip, we
are building the FIR filter structure to get the filter the incoming recorded signal and we are sending it
back to the speaker as the output of the system. Here, we can extend this to add the Adaptive filter to give
the adaptive filtering structure instead of the FIR filter to implement

MODULE 4
In this module, we are configuring the audio codec module present in the DE1SoC board to
record the real time speech signal from the microphone, store the data in SDRAM and send back the
recorded data through the Audio Block to DAC to generate the real time audio signal to the speaker. The
challenges faced here as follows. We had to design QSyS system, defining the parameters required for
each of the IPs along with the interrupt priorities was a challenge by itself, coding in the Eclipse platform
for each of the drivers specified and writing the I2C software module, integrating the modules to work
with each other and getting the output for each of these things to work in unison was demanding.

OBJECTIVES:

To master the DE1- SoC design flow by designing the new system from the scratch.
Apply the concepts used in the other modules to create a new design in DE1-SoC.
To get a strong grip on SoC EDS design flow.
Learn to design an Embedded System Design on the Programmable module from the scratch.

PROCEDURE:
1. Open Quartus II, start a new project with the appropriate data fed into it.
2. In the menu option, select Tools and in the drop down menu choose Qsys System Builder Open
the double click on it to open.
3. Add the elements to QSyS design :- From the IP catalogue choose the following elements
PLL :- Input to this block is clock of 50 MHz. Output will be two clock sources one of
80MHz and 10 MHz.
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PROJECT 3
Nagaraj Siddeshwara, Karthik Vijayakumar and Kalyan Pingali
Date: 12/09/16
Nios II Processor:- Choose the Nios II (f). Clock given to this is 80 MHz from the PLL
and Set the base address and reset address accordingly.
JTAG:- This is used as an interface for the communicating between the host PC and the
DE1 SoC board.
SDRAM:- This block is used to store the input sample data from the ADC.
Onchip memory :- This block is used as the RAM for the Nios II processor.
Avalon Cross Clocking Bridge:- These are used as an interface between the peripherals
and the processor both of which are working at two different frequencies.
PIOs:- We have added three PIOs one for configuring the Keypad, LEDs, Switches.
Audio Clock:-This block is used as the clock to Audio Codec present in the board.
Audio A/V Config :- This block is used to configure the Audio/ Video registers present in
the Processor.
Audio :- This block is used to transfer the data from the ADC and DAC this has four
buffers in it. Each of which is used for left and right channels of the stereo audio output.
.
4. Set the base address and see the address map for overlapping of the addresses. Save the file and
generate the list.
5. Close the file, compile to verify for the timing constraints and Open Pin Planner to check if each
of the pins in the board is connected properly to the specified locations.
6. In the menu bar, select tools to open drop down interface choose Nios II software build tools for
Eclipse.
7. Write the code here to integrate the device drivers used in the module to generate appropriately.
8. Switch on the board, connect the USB cable and using programmer, download the program on to
the FPGA.
9. After building the project and Select the option of running from the

OBSERVATION AND RESULTS:

1. Percent utilization summary of the project is shown below.

2.

Fmax Summary:

PROJECT 3
Nagaraj Siddeshwara, Karthik Vijayakumar and Kalyan Pingali
Date: 12/09/16

MODULE TEST RESULTS: (Observation of board behaviour )

The board is configured to take inputs from the switches and keypads. Upon the setting on the switch, the
sampling rate of the ADC is set to 44.1KHz. The input to the device is chose as the mic and the output is
as the speakers. The ADC is configured via software and it starts receiving the speech samples from the
ADC. The samples are stored in the SDRAM and sent to Nios II processor for processing the signal, the
Filtered samples are sent back to the DAC for outputting the data onto the speakers.
We have used FIR low pass filter of order 64,Cut off frequency of 8 kHz and the transition band from
8khz to 10 KHz. This is equi-ripple filter with double precision coefficients are used in the design. The
co-efficients used in the design are generated via FDATool in the Signal Processing tool box of the
MATLAB.

LESSONS LEARNED:

Parameters inside the QSys IP blocks have significant meaning and can affect the performance of
the output of the program.
Understood the Nios II software development process studying the code and the reference manual
provided by Altera. Understood the importance of the HAL during the process.
Usage of interrupts in real time processing is very important. All the inputs are sent in response to
interrupts for efficient working and design. Even though these are asynchronous, it is better to use
in the design to performance considerations.

CONCLUSION:
The real time audio filtering process is time consuming and worth putting an effort to learn the intricacies
of the design. The filtering of the signal requires the understanding of the whole system designed. The
design and implementation of this module presented us an opportunity to implement and use the IPs
which are customized and usage of these in our design effectively. Data sheets of the IPs have invaluable
information that can help us in the design implementation.

MODULE 1
OBJECTIVES:

To learn how to connect simple input (switches) and output (LEDs, 7-segment displays) devices
to an FPGA chip and implement a circuit that uses these devices
To understand clocks in timed circuits and display timers using 7 segment displays

PROCEDURE:

Lab1
o

Part 1:
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PROJECT 3
Nagaraj Siddeshwara, Karthik Vijayakumar and Kalyan Pingali
Date: 12/09/16
Create a Quartus file to link LEDs to Switches by assigning the LED vector to
the switch vector
Assign pins on board accordingly (follow Quartus II Introduction using Verilog
Design) and dump code using programmer. Test by sliding switches
o Part 2:
Create a Quartus file to implement a 4 bit wide 2to1 mux
Assign switch 9 as the select s, and 7 through 4 as input Y and 3 through 0 as
input X and connect LEDs 3 through 0 as the output, while still probing LED 9
for input s
Make necessary pin assignments
Dump code using Programmer tool and test by sliding switches, observing LEDs
o Part 3:
Create a Quartus file to implement a 2 bit wide 3to1 mux
Assign switches 8 and 9 as select lines, and 5 through 0 as inputs U, V and W.
Also assign LEDs 0 and 1 as the output.
Make necessary pin assignments
Dump code using Programmer tool and test by sliding switches, observing LEDs
o Part 4:
Create a Quartus file to display using the 7 segment display
Write a VHDL entity to connect c1c0 to switches 0 and 1 and outputs of decoder
to HEX0 display (declared as a vector)
Make pin assignments and dump code using programmer tool and test by
toggling switches 0 and 1
o Part 5:
Include the entity given in Lab1_VHDL.pdf in D2L, in a new Quartus file
Connect switches 9 and 8 to inputs of the 3 instances of 2 bit wide 3 to 1 mux,
and also connect switches 5 through 0 to each instance of the mux as required to
produce patterns as shown in the pdf mentioned above
Make necessary pin assignments and program the board using programmer tool
and test by toggling switches and observing LEDs
o Part 6:
Using the entity developed in part 5, make a new Quartus file and change
switches 9 through 7 to select inputs
Make appropriate changes to pin planner and dump code using programmer tool
and test by switching 9 through 7 and observe 7 segment displays
Lab5
o Part 1:
Create a Quartus file to design a modulo k counter, with a VHDL file for an 8 bit
counter to count with mod 20
Configure key0 as reset and key1 as manual clock, LEDs 7 through 0 as the
counter display and LED 9 as rollover
Make pin assignments, use programmer tool to dump code and then test
o Part 2:
Using the basic modulo counter from part 1, interface three 7 segment displays
(HEX 2 through 0) and configure them to display as a three-digit counter
Assign key0 as a reset to the counter and use the on board clock for all
Make pin assignments, use programmer tool to dump code and then test
o Part 3:
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PROJECT 3
Nagaraj Siddeshwara, Karthik Vijayakumar and Kalyan Pingali
Date: 12/09/16
Modify part 2 to display a real time clock by counting from 0 to 99 (hundredth of
second) on HEX 1 and 0, 0 to 59 on HEX 3 and 2 and minutes (0 to 59) on HEX
4 and 3
Use switches 0 through 7 to pre-set time and key0 as a reset
Make pin assignments, use programmer tool to dump code and then test
o Part 4:
Using the timing knowledge accumulated in the above parts, we develop a half
second counter and use this to implement the Morse code
Switches 2 through 0 are to be configured to display A through H using an LED.
Also configure key0 as a reset

OBSERVATION AND RESULTS:

In step 2, the displays worked accurately as expected.
In lab1:
-

In part 1, switches toggled the LEDs accurately

In part 2, toggling switch 9 toggled LEDs 3 through 0 according to inputs
defined by switches
In part 3, toggling switches 8 and 9 made LEDs 0 and 1 show inputs U, V and
W accordingly
In part 4, selecting 00/01/10 showed d/E/1 respectively on the 7 segment
display
In part 5, toggling switches 9 and 8 displayed d/E/1 according to logic in part
3 and 4
In part 6, displays toggled on 7 segment array depending on switch 9 through
7 inputs

In lab5:
-

In part 1, the counter wraps around at 20 and resets on pressing key0

In part 2, the modulo counter counts using the three 7 segment displays
every 1 second
In part 3, the six 7 segment displays make up a real time clock!
In part 4, Morse code works perfectly for the developed characters
SOS works with accurate gap of half second between parts of same character
and one and half second between characters
To test the accuracy of the real time clock, we can start a stop watch at the
same time and observe for around 5 to 10 minutes to check for any drift

MODULE TEST RESULTS:

In lab 1:
Utilization for part 1: (Less than 1 %)

Utilization for part 2: (Less than 1 %)

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PROJECT 3
Nagaraj Siddeshwara, Karthik Vijayakumar and Kalyan Pingali
Date: 12/09/16

Utilization for part 3: (Less than 1 %)

Utilization for part 4: (Less than 1 %)

Utilization for part 5: (Less than 1 %)

Utilization for part 6: (Less than 1 %)

In lab5:
Fmax for part 1:

Utilization for part 1: (Less than 1 %)

Fmax for part 2:

Utilization for part 2: (Less than 1 %)

Fmax for part 3:

Utilization for part 3: (Less than 1 %)

Fmax for part 4:

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PROJECT 3
Nagaraj Siddeshwara, Karthik Vijayakumar and Kalyan Pingali
Date: 12/09/16

Utilization for part 4: (Less than 1 %)

LESSONS LEARNED:
-

Programming the DE1SoC

Achieving real time accuracy is an art which needs very careful evaluation of all scenarios and
thinking of worst case delays

CONCLUSION:
Understood the working of switches, LEDs and HEX displays through exercises. Also understood the
working of timers and how to develop a real time clock and use it to communicate with Morse code.

MODULE 2
OBJECTIVES:

To understand the usage and significance of ARM Generic Interrupt Controller (GIC)
To understand the implementation of a Counter of Variable Speed, a Real Time clock
Get familiarised with the usage and significance of ARM 9 HPS on Altera DE1-SoC
To understand how Assembly programming can used in using ARM 9 HPS as a multipurpose
device.

PROCEDURE:

Follow the instructions in lab5.pdf file uploaded on D2L.

Power up and connect FPGA board to PC.
After opening Altera Monitor Program 15.1, create a new Project
Then write the required Assembly code. Then click Compile and Load to compile the code.
Click Run button to download on FPGA and verify the obtained results.

OBSERVATION AND RESULTS:

Its easy to create the Timer function in Module 1 than Module 2 as its easy to code in HDL than in
Assembly. Assembly programming needs thorough understanding of Processor architecture and the
syntax and commands. Also as HDL is a universal language, its syntax is easier to learn and implement.
The Assembly program in Module 2 uses lesser resources as
Part 1: The value at Program Counter is 0x00000208.
Part 2: The value at Program Counter is 0x00000040.
Part 3: The value at Program Counter is 0x000000D8.
Part 4: The value at Program Counter is 0x000000E4.

MODULE TEST RESULTS:

PROJECT 3
Nagaraj Siddeshwara, Karthik Vijayakumar and Kalyan Pingali
Date: 12/09/16
Part 1: Upon successful download of program to DE1-SoC, when KEY0 is pressed , number 0 is
displayed on HEX0, when KEY1 is pressed , number 1 is displayed on HEX1 and so on.
Part 2: Upon successful download of program to DE1-SoC, Counter starts counting from 0 on LEDR and
when KEY0 is pressed, the counter pauses at the present value displaying the static value on LEDR..
Part 3: Upon successful download of program to DE1-SoC, when KEY0 is pressed, the counter pauses
and continues to increment and vice versa whose value is displayed on LEDR. When KEY1 is pressed,
the speed of the count is doubled. When KEY2 is pressed, the speed of the count reduces by half. The
count is displayed on LEDR.
Part 4: Upon successful download of program to DE1-SoC, the second and hundredth of a second are
displayed on HEX3 and HEX2 and HEX1 and HEX0 respectively. When KEY3 is pressed, the clock is
paused. When time display reaches 59:99, the display is reset to 00:00.
Note: Refer Module_2 subfolder inside Deliverables folder to get the snapshots.

LESSONS LEARNED:

Learnt to use ARM 9 HPS on Altera DE1-SoC.

Understood the significance of GIC
The multitude of applications of HPS in various conditions.

CONCLUSION:
The usage of ARM 9 HPS is understood through interrupts using GIC. The programs were successfully
downloaded and the results were displayed on LEDs and HEX displays. Also, the use of Altera Monitor
Program 15.1 is understood. Also, the implementation of Constant Speed Counter, Variable speed counter
and real time clock displaying seconds and hundredth of a second are understood thoroughly.

MODULE 3
OBJECTIVES:

To understand Altera SoC EDS(Embedded Design Suite) operation

To create a Linux Boot SD-Card for DE1-SoC with a given image file
To learn the skill to boot Linux from SD-Card on DE1-SoC
To learn the skill to copy files into Linux file system on DE1-SoC
To learn basic Linux command operation skill

PROCEDURE:

Follow the instructions in My_First_HPS-Fpga.pdf file uploaded on D2L.

Power up and connect FPGA board to PC.
Load the MicroSD card image to MicroSD card and insert into the MicroSD slot on the board.
Open the Quartus Prime EDS Suite 15.1 and type the required commands to generate the ARM
execution file.
Download the .sof file on FPGA and verify the result.

OBSERVATION AND RESULTS:

8

PROJECT 3
Nagaraj Siddeshwara, Karthik Vijayakumar and Kalyan Pingali
Date: 12/09/16
The fmax is found to be 277.55 MHz. The restricted maximum frequency is 275 MHz.
The percentage utilization is found to be 7%.
Upon successful compiling of main.c file in hps-c subfolder, the ARM execution file my_first_hpsfpga is generated. Upon following the instructions in the manual My_First_HPS-Fpga.pdf the LEDs
LEDR[9:0] all are turned on and blink 60 times and stop .

MODULE TEST RESULTS:

The connection between HPS and FPGA is successfully done and Linux OS is booted from FPGA. Upon
downloading the. sof file on FPGA, the LEDs are founded to blinking for 60 times and then stop.
Note: Refer Module_3 subfolder inside Deliverables folder to get the snapshots

LESSONS LEARNED:

Understood the use and operation of Altera SoC EDS(Embedded Design Suite)
Learned to create a Linux Boot SD-Card for DE1-SoC with a given image file
Learned to boot Linux from SD-Card on DE1-SoC
Learned to copy files into Linux file system on DE1-SoC

CONCLUSION:
The communication between HPS and FPGA through AXI (Advanced eXtensible Interface) bridge is
achieved. The Linux OS is successfully booted from FPGA board and the LEDs blinking is successfully
observed.

REFERENCES:
https://people.ece.cornell.edu/land/courses/ece5760/DE1_SOC/Audio_core.pdf
https://www.usna.edu/EE/ec463/notes/08_EC463_Audio_student.pdf
ftp://ftp.altera.com/up/pub/Altera_Material/13.1/University_Program_IP_Cores/Clocks/Alt
era_UP_Clocks.pdf

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PROJECT 3
Nagaraj Siddeshwara, Karthik Vijayakumar and Kalyan Pingali
Date: 12/09/16

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