EE539: Analog Integrated Circuit Design; Common mode feedback

circuits
Nagendra Krishnapura (nagendra@iitm.ac.in)
18 April 2006

Vdd
M3

M4
vop + von
CL

CL

2
vop
von

M1

M2

common
mode
detector
Vcm,out
error amplifier

I0
M0

Figure 1: Principle of common mode feedback

Adjust top current sources (M3,4 ) via feedback to control the bottom current source (M0 ).
Detected common mode voltage equals Vcm,out in steady state-assuming a large loop gain.

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Vdd

Vdd
error amplifier

M3

M4
CL

CL

replaced by a wire

M3

M4

Rcm
CL

CL
Rcm

Rcm

Rcm
M1

M2

M1

M2

I0
M0
(a)

I0
M0
(b)

Figure 2: (a) CMFB circuit using common mode diode connection, (b) redrawn

Common mode diode connection: output voltage adjusts itself to ensure that I 3 + I4 = I0 .
Resulting common mode equals vcm,out = Vdd VT

I0 /K3 . Cannot be set independently of

device parameters
Largest positive output swing = VT , implying a largest differential peak-peak swing of 4VT , independent of the supply voltage.
Common mode detector using resistors: loads the differential amplifier and reduces the gain.

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Vdd

Vdd
M3,4

M3,4

W3,4 = 2W3

W3,4 = 2W3

magnitude

2CL

Vf

Vt

cascode connection
Rcm /2 large R
out
Vcm,in

M1,2
W1,2 = 2W1

gm3 /gds3
gm1 /(gds1 + gds3 + Gcm )
Rcm /2
differential gain
(no mirror pole)
common mode
u,d = gm1 /CL
loop gain

2CL

Vcm,in

M1,2
W1,2 = 2W1

gds3 /CL
u,cm = gm3 /CL
(gds1 + gds3 + Gcm )/CL

I0

I0

Gcm /Cgs3

M0

M0
Vf
Vt

gm3

gds3 (1 + sCgs3 Rcm )(1 + sCL /gds3 )

(a)

(b)

(c)

Figure 3: (a) Common mode equivalent ckt., (b) CMFB loop gain calculation, (c) Typical differential gain
and CM loop gain magnitudes

CMFB loop gain: Dominant pole at the output

Second pole significant if a large Rcm is used
Feedback around a single transistor (M3,4 ). Typically stable.
No mirror pole in the fully differential amplifiers response

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Vdd
M3

Vdd
M4

CL

M13

M14

CL
Rcm
M1

Rcm
Vcm,out

M2

M11

M12

Vcm vi /2
I0

I10

M0

M10

Differential pair

Error amplifier
I10 = I0 /
W10 = W0 /
W11 = W1 /
W13 = W3 /
> 1 minimize power consumption

Figure 4: CMFB circuit with explicit error amplifier

A second differential amplifier used as an error amplifier. Its output current is mirrored to the opamps
load devices (M3 , M4 )
To have no systematic error in the output CM voltage, aspect ratios of M 3,4,13,14 are in ratios of
respective currents. i.e. without mismatches, the error amplifier operates with zero input voltage
Error amplifier current can be scaled down to minimize power consumption.

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Vdd

Vdd

M3,4

M13

M14

2CL
Rcm /2
Vcm,out

M1,2

M11

M12

Vcm
I0

I10

M0

M10

Differential pair

Error amplifier

Figure 5: CM equivalent
Vdd

Vdd

W3,4 = 2W3
M3,4

M13

M14

gm1 Vx
2CL

Vf
Rcm /2

gm1 /2Vx

gm1 /2Vx

Cx
Vcm,out

M1,2

M11

M12

W1,2 = 2W1

Vcm

Vx
I10

I0

M10

M0

Error amplifier

Differential pair

Cx : capacitive loading from the error amplifier

Vf

gm1
1
1
1
=
Vt
2gds3 1 + sgds3 /CL 1 + sCx Rcm 1 + sgm3 /Cp3
(Assumed that Rcm Cx << CL /gds3 ; Cp3 is the parasitic capacitance at the drain of M13

Figure 6: CMFB loop gain calculation

Differential response: Single pole at the output.

CMFB loop gain: Three poles; Approx. two poles with a small R cm ; Dominant pole at the output.
CL compensates both the common mode and differential loops.
Using a large (small current in the error amplifier) results in a lower frequency non dominant pole
in CMFB loop gain.

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Vdd
M3

Vdd
M4

CL

M13

M14

CL

M1

M2

Vcm,out

M11

M12

M12

Vcm vi /2
I0

I10

M0

M10

Differential pair

Common mode detector + Error amplifier

I10 = I0 /
W10 = W0 /
W11 = W1 /
W12 = W11 /2
W13 = W3 /
> 1 minimize power consumption

Figure 7: CMFB circuit using differential pair CM detector

Split the transistor in the error amplifier differential pair into two halves and apply vop , von to their
gates. Current summation ensures common mode detection.
Active CM detector does not load the opamp.
Resistive CM detector: highly linear
Active CM detector: Linearity, and consequently, the swing of the output signals, depends on the
linearity of the error amplifier differential pair

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Vdd
M3,4

Vdd
Vt

Vf

M13

M14

2CL

Cascode
large Rout

Vcm,out

M1,2

I0
M0

M11

M12

I10
M10

Figure 8: CMFB loop gain calculation using the common mode equivalent circuit

Two pole response

Vf
gm3 gm11
1
1
=
Vt
gds3 2gm14 1 + sCL /gds3 1 + sCx /gm14
Non dominant pole gm14 /Cx moves to lower frequencies if a very small current is used in the error
amplifier.

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Vdd
Common mode detector and feedback
Vdd

M11 M12

Rs
M3

Vbias,p

M4

CL

Vbias,p
ID

CL

M1

Vdd

M2
vop

Vcm vi /2

von
Gs

I0

Vbias,p

M0

ID

Differential pair
Gs = 2Kp
(a)

vop + von
2

VT

(b)
Vdd

Vdd
Common mode detector and feedback

M11 M12

M24
W12 /L12

M3

M4

Vcm,out
(W12 /)/L12

Vbias,p
M23

CL W3 /L3

W3 /L
C3

M1

(W3 /)/L3

M2

Vcm vi /2
I0

I0 /2

M0
Differential pair

replica biasing

(c)

Figure 9: (a) Common mode feedback using transistors in triode region, (b) Degenerated resistor, Degeneration using MOS transistors whose resistance depends on the common mode voltage, (c) Replica biasing to
set the output common mode voltage

Parallel transistors in triode region with vop , von as inputs realize a conductance as a function of the
common mode
Replica biasing with the gate of M24 at the desired common mode level
Upper limit of vop , von is Vdd VT . M13,14 go into saturation region at a voltage slightly below this.

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CL

CL

Ycm = 2sCL
Ydif f = sCL /2

CL

CL

Ycm = 0
Ydif f = sCL /2

C2

C1

C1

C2

Ycm = 2sC2
Ydif f = s(C1 + C2 )/2

Figure 10: Differential and common mode loading

Floating capacitors dont contribute to common mode loading

There should be sufficient common mode loading to compensate the CMFB loop

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Vdd
M3

M4

Vbias,p

M13
M6

M14

Cx
M5

M1

Cc

M2

CL

Vcm vi /2

Vcm,out

Cc
Rcm

Rcm

M11

M12

CL

I0

I0 /

M0

M8

I1

M7

I1

M10

Differential pair
Fully differential two stage opamp

Error amplifier

Figure 11: Two stage opamp with common mode feedback

Output common mode voltage is measured and common mode feedback applied to the first stage load.
Can use separate common mode feedback for each stage

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Vdd
M1,4

M14

M13
M5,6
Cx

Vcm,out

2Cc
Vcm,in
2CL

M1,2

M11

M12

Rcm /2
Vf

Vt

M7,8

I0
M0

I0 /
M10

2I1

Figure 12: Common mode equivalent circuit of the two stage opamp

Common mode feedback: Negative feedback around two stages

Compensation through Cc
Differential response
Ad (s) =
p1
p2

1 sCc /gm5
gm5
gm1
gds1 + gds3 gds5 + gds6 + Gcm (1 + s/p1 )(1 + s/p2 )
gds3
C3 + Cc (1 + gm5 /gds5 )
c
gm5 CcC+C
3

Cc CL
Cc +CL

CL +

C3 is the parasitic capacitance at the drain of M3 .

Common mode loop gain
Acmloop (s) =
p1
p2
p3 =

gm5
gm11
gm3
1 sCc /gm5
gds3 gds5 + gds6 2gm13 (1 + s/p1 )(1 + s/p2 )(1 + s/p3 )
gds3
C3 + Cc (1 + gm5 /gds5 )
c
gm5 CcC+C
3

CL +
gm13
Cx

Cc C3
Cc +C3

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Vdd
M3

M4

M13
M6

M14

Cx
M5
M12

M1

M2

Cc

Vcm,out

Cc
vop

CL

von

I0
M0

Fully differential two stage opamp

M11

M12
vop

von

CL

I0 /
M8

I1

M7

I1

M10

Common mode detector + error amplifier

Figure 13: Two stage fully differential opamp with split transistor common mode detector

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Rcm
Rcm

Vi

Vo

Vi

Vo

Cload

Vo
Vi

Ccm

Vo

1 + sRcm Cload

Vi

Cload

1 + sRcm Ccm
1 + sRcm (Ccm + Cload )

Figure 14: (a) Resistive common mode detector, (b) Introducing a zero to reduce phase lag

To minimize loading, increase Rcm .

Rcm with parasitic capacitance at the input of the error amplifier adds phase lag and degrades stability.
Use a capacitor across Rcm to introduce phase lead and ensure stability of the common mode feedback
loop.

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R

R
Vcm vi /2

Vcm,out vo /2

R
R
(a)
Vdd
M3

Vdd
M4

M3,4
W3,4 = 2W3

Rout 1/gds0
CL
R

much smaller than without differential feedback

V

CL
Rcm

Rcm

Rcm /2

R
R

M1

M2

Vt

2CL

R/2

Vcm,in

M1,2
W1,2 = 2W1

R/2

I0

I0

M0

M0
Vf

(b)

Vt

gm3

(gds3 + gds0 ) (1 + sCgs3 Rcm )(1 + sCL /(gds3 + gds0 ))

(c)

Figure 15: (a) Opamp with differential feedback, (b) Transistor level circuit, (c) Common mode equivalent
circuit

Differential feedback can change CMFB loop gain.

CM loop gain needs to be evaluated with differential feedback in place.