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logic
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Theory: In CMOS technology, both p-type and n-type MOSFETs are used to implement digital
circuits e.g., logic gates. CMOS logic gates have the desirable properties of high noise immunity
and low static power consumption . Since one transistor of the pair is always off, the series
combination draws significant power only momentarily during switching between on and off
states. Consequently, CMOS devices do not produce as much waste heat as other forms of logic,
for example transistortransistor logic (TTL) or NMOS logic, which normally have some
standing current even when not changing state. CMOS also allows a high density of logic
functions on a chip. It was primarily for this reason that CMOS became the most used
technology to be implemented in VLSI chips. The phrase "metaloxidesemiconductor" is a
reference to the physical structure of certain field-effect transistors, having a metal gate electrode
placed on top of an oxide insulator, which in turn is on top of a semiconductor material.
Parameters to look for in a logic family:
Noise Margins:
The noise margins for an inverter are defined as shown in fig. 1(a).
NMHIGH = VOH - VIH
NMLOW = VIL - VOL
Propagation Delays:
The propagation delays are defined as shown in fig. 1 (b).
tpLH= t2 t1, tpHL = t4- t3
tp= (tpLH+ tpHL) / 2
Propagation delays t and tPHL are defined as the times required for output voltage to reach
the middle between the low and high logic levels, i.e. 50 % of V DD in case of CMOS logic.
High-to-Low propagation delay (tpHL): Time taken to fall from VOH to 50%.
PLH
Low-to-High propagation delay (tpLH): Time taken to rise from 50% to VOL.
The propagation delay of the CMOS inverter is determined by the time it takes to charge and
discharge the capacitances present in the logic circuit. Given below is circuit depicting
capacitances in Cmos inverter circuit