MACH and PAL/GAL Macro Reference Manual

TTL Function Macros

1999

Lattice / Vantis Applications Engineering

TABLE OF CONTENTS
Macro Name
V7400
V7402
V7408
V7410
V7411
V7420
V7421
V7427
V7430
V7432
V7442
V7449
V7451
V7482
V7483
V7485
V7486
V74133
V74138
V74139
V74148
V74150
V74151
V74152
V74153
V74154
V74157
V74158
V74161
V74162
V74163
V74164
V74166
V74168
V74169
V74174
V74181
V74182
V74273
V74280
V74283
V74298
V74352
V74377
V74518
V74521

Macro Description

Page

2 Input NAND gate

2 Input NOR gate
2 Input AND gate
3 Input NAND gate
3 Input AND gate
4 Input NAND gate
4 Input AND gate
3 Input NOR gate
8 Input NAND gate
2 Input OR gate
BCD to Decimal decoder
BCD to 7 Segment decoder
Dual 2 Wide 2/3 Input AOI Gate
2 Bit Full Adder
4 Bit Full Adder
4 Bit Magnitude Comparator
2 Input XOR gate
13 Input NAND gate
3-to-8 Line Decoder
2-to-4 Line Decoder
8-to-3 Priority Line Encoder
16-to-1 Multiplexer with Enable
8-to-1 Multiplexer with Enable
8-to-1 Multiplexer with Enable, Active Low
Dual 4-to-1 Multiplexer with Enable
4-to-16 Line Decoder
Quad 2-to-1 Multiplexer
Quad 2-to-1 Multiplexer (Active Low)
Presettable Sync 4 bit Binary Counter
4 Bit BCD/Decade Counter w/ Sync Reset
4 Bit Binary Counter w/ Sync Reset
8 Bit SIPO Shift Register
8 Bit PISO Shift Register
4 Bit Loadable Up/Down BCD Counter
4 Bit Loadable Up/Down Binary Counter
Hex D FlipFlops with Clear
4 Bit ALU
Look Ahead Carry Generator
Octal D FlipFlops with clear
9 Bit Odd/Even Parity Generator/Checker
4 Bit Full Adder with Fast Carry
Quad 2-to-1 Mux with Storage
Dual 4-to-1 Multiplexer with Enable, Active low
Octal D FlipFlops with data enable
8 Bit Identity Comparator
8 Bit Identity Comparator Low out

Legend :
H:
L:
X:
f:
r:
a,b,c, :

HIGH votage level

LOW votalge level
Immaterial or dont-care
Clock falling edge
Clock rising edge
Input or output constants

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

V7400

Quad 2 Input NAND Gate

LOGIC SYMBOL

FUNCTIONAL DESCRIPTION

PIN DESCRIPTION
Pin Names
Description
A0 - D0
A1 - D1
YA YD

V7400

NAND gate A D inputs 0

NAND gate A D inputs 1
NAND gate A D outputs

FUNCTION TABLE
Inputs

Outputs

Input0 Input1
H
H
L
X
X
L

Y
L
H
H

4 Independent 2 input NAND gates

V7402

Quad 2 Input NOR Gate

FUNCTIONAL DESCRIPTION

LOGIC SYMBOL

PIN DESCRIPTION
Pin Names
Description
A0 - D0
A1 - D1
YA YD

NOR-gate A - D inputs 0
NOR-gate A - D inputs 1
NOR-gate A - D outputs

FUNCTION TABLE
Inputs

Input0 Input1
H
X
X
H
L
L

V7402

Outputs

Y
L
L
H

4 Independent 2 input NOR gates

V7408

Quad 2 input AND Gate

LOGIC SYMBOL

FUNCTIONAL DESCRIPTION

PIN DESCRIPTION
Pin Names
Description
A0 - D0
A1 - D1
YA YD

V7408

AND-gate A - D inputs 0
AND-gate A - D inputs 1
AND-gate A - D outputs

FUNCTION TABLE
Inputs

Outputs

Input0 Input1
H
H
L
X
X
L

Y
H
L
L

4 Independent 2 input AND gates

V7410

Triple 3 Input NAND Gate

LOGIC SYMBOL

FUNCTIONAL DESCRIPTION

3 Independent 3 input NAND gates

PIN DESCRIPTION
Pin Names
Description
NAND-gate A C inputs 0
NAND-gate A C inputs 1
NAND-gate A C inputs 2
NAND-gate A C outputs

A0 C0
A1 C1
A2 C2
YA YC

FUNCTION TABLE
Inputs

Input0
L
X
X
H

Input1
X
L
X
H

Outputs

Input2
X
X
L
H

V7410

Y
H
H
H
L

V7411

Triple 3 Input AND Gate

LOGIC SYMBOL

FUNCTIONAL DESCRIPTION

3 Independent 3 input AND gates

PIN DESCRIPTION
Pin Names
Description
AND-gate A C inputs 0
AND-gate A C inputs 1
AND-gate A C inputs 2
AND-gate A C outputs

A0 C0
A1 C1
A2 C2
YA YC

FUNCTION TABLE
Inputs

Input0
L
X
X
H

Input1
X
L
X
H

Outputs

Input2
X
X
L
H

V7411

Y
L
L
L
H

V7420

Dual 4 Input NAND Gate

LOGIC SYMBOL

FUNCTIONAL DESCRIPTION

PIN DESCRIPTION
Pin Names
Description
NAND-gate A inputs
NAND-gate B inputs
NAND-gate A & B output

A0 A3
B0 B3
YA, YB

FUNCTION TABLE
Inputs A/B

0
H
L
X
X
X

1
H
X
L
X
X

2
H
X
X
L
X

Outputs

3
H
X
X
X
L

V7420

YA,YB
L
H
H
H
H

2 Independent 4 input NAND gates

V7421

Dual 4 Input AND Gate

LOGIC SYMBOL

FUNCTIONAL DESCRIPTION

PIN DESCRIPTION
Pin Names
Description
AND-gate A inputs
AND-gate B inputs
AND-gate A & B output

A0 A3
B0 B3
YA, YB

FUNCTION TABLE
Inputs A/B

0
H
L
X
X
X

1
H
X
L
X
X

2
H
X
X
L
X

Outputs

3
H
X
X
X
L

V7421

YA,YB
H
L
L
L
L

2 Independent 4 input AND gates

V7427

Triple 3 Input NOR Gate

LOGIC SYMBOL

FUNCTIONAL DESCRIPTION

3 Independent 3 input NOR gates

PIN DESCRIPTION
Pin Names
Description
NOR-gate A C inputs 0
NOR-gate A C inputs 1
NOR-gate A C inputs 2
NOR-gate A C outputs

A0 C0
A1 C1
A2 C2
YA YC

FUNCTION TABLE
Inputs

Input0
H
X
X
L

Input1
X
H
X
L

Outputs

Input2
X
X
H
L

V7427

Y
L
L
L
H

10

V7430

Single 8 Input NAND Gate

FUNCTIONAL DESCRIPTION

LOGIC SYMBOL

PIN DESCRIPTION
Pin Names
A0 A7
YA

One 8 input NAND gate

Description
NAND-gate inputs
NAND-gate output

FUNCTION TABLE
Inputs

A0
H

A1
H

A2
H

A3
H

A4
H

V7430

Outputs

A5
H

A6
H

A7
H

All the others

11

YA
L
H

V7432

Quad 2 Input OR Gate

FUNCTIONAL DESCRIPTION

LOGIC SYMBOL

PIN DESCRIPTION
Pin Names
Description
A0 - D0
A1 - D1
YA YD

V7432

OR-gate A - D inputs 0
OR-gate A - D inputs 1
OR-gate A - D outputs

FUNCTION TABLE
Inputs

Outputs

Input0 Input1
L
L
H
X
X
H

Y
L
H
H

12

4 Independent 2 input OR gates

V7442

BCD to Decimal Decoder

LOGIC SYMBOL

V7442

FUNCTIONAL DESCRIPTION

Decodes 4-bit BCD input into a single

Active-LOW output

Accepts four lines of BCD encoded data

and provides ten mutually exclusive
Active-LOW outputs

PIN DESCRIPTION
Pin Names
Description
A0 A3
Y0 Y9

BCD input lines

Decimal decoded output (Active-LOW)

FUNCTION TABLE
Inputs

A3
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

A2
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

A1
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

Outputs

A0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

Y0
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

Y1
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H

Y2
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H

Y3
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H

Y4
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H

13

Y5
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H

Y6
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H

Y7
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H

Y8
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H

Y9
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H

V7449

BCD to 7 Segment Decoder

LOGIC SYMBOL

FUNCTIONAL DESCRIPTION

PIN DESCRIPTION
Pin Names

Translates four lines of BCD(8421) input

data into the 7-segment numeral code

Provides an Active-LOW blanking input

Description
BCD inputs
Blanking input (Active-LOW)
7-Segment outputs

A0 A3
BI
A,B,C,D,E,F,G

FUNCTION TABLE
Inputs
DEC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
BI

A3
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X

A2
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X

A1
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
X

Outputs
A0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X

BI
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L

V7449

A
H
L
H
H
L
H
L
H
H
H
L
L
L
H
L
L
L

B
H
H
H
H
H
L
L
H
H
H
L
L
H
L
L
L
L

C
H
H
L
H
H
H
H
H
H
H
L
H
L
L
L
L
L

D
H
L
H
H
L
H
H
L
H
L
H
H
L
H
H
L
L

E
H
L
H
L
L
L
H
L
H
L
H
L
L
L
H
L
L

F
H
L
L
L
H
H
H
L
H
H
L
L
H
H
H
L
L

14

G
L
L
H
H
H
H
H
L
H
H
H
H
H
H
H
L
L

V7451

Dual 2 Wide 2/3 Input AOI Gate

LOGIC SYMBOL

FUNCTIONAL DESCRIPTION

The AOI gate A has 2 wide 2 input AND-ORInverter function

The AOI gate B has 2 wide 3 input AND-ORInverter function

PIN DESCRIPTION
Pin Names
Description
AA0 AA1
AB0 AB1
YA
BA0 BA2
BB0 BB2
YB

AOI-A A-AND gate inputs

AOI-A B-AND gate inputs
AOI-A output
AOI-B A-AND gate inputs
AOI-B B-AND gate inputs
AOI-B output

FUNCTION TABLE
Inputs
AA0 AA1 AB0 AB1
L
L
L
X
L
L
X
L
L
X
L
L
X
L
L
L
X
X
H
H
H
H
X
X

V7451

Outputs
YA
H
H
H
H
L
L

AOI-B gate has same functionality as AOI-A except 3-input AND gates

15

V7482

2 Bit Full Adder

LOGIC SYMBOL

FUNCTIONAL DESCRIPTION

Performs the addition of two 2 bit binary

numbers

TTL7482 generates a rippled carry out, but

this macros CO can be as fast as carry look
ahead due to internal node collapse

PIN DESCRIPTION
Pin Names
Description
Carry input
Operand A inputs
Operand B inputs
Sum outputs
Carry output

CI
A0 A1
B0 B1
S0 S1
CO

FUNCTION TABLE
Inputs
A1

A0

B1

B0

L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

V7482

Outputs
CI = L
CI = H
CO S1 S0
CO S1 S0
L
L
L
L
L
H
L
L
H
L
H
L
L
H
L
L
H
H
L
H
H
H
L
L
L
L
H
L
H
L
L
H
L
L
H
H
L
H
H
H
L
L
H
L
L
H
L
H
L
H
L
L
H
H
L
H
H
H
L
L
H
L
L
H
L
H
H
L
H
H
H
L
L
H
H
H
L
L
H
L
L
H
L
H
H
L
H
H
H
L
H
H
L
H
H
H

16

V7483

4 Bit Full Adder

FUNCTIONAL DESCRIPTION

LOGIC SYMBOL

Performs the full adder operation of two 4bit binary numbers

Partial carry look ahead logic to generate

carry out
Bit0 > Bit1 : Carry look ahead
Bit1 > Bit2 : Ripple carry
Bit2 > Bit3 : Carry look ahead

PIN DESCRIPTION
Pin Names

Description
4-bit binary input A
4-bit binary input B
Carry input
4-bit sum output
Final carry output

A0 A3
B0 B3
CI
S0 S3
CO

FUNCTION TABLE
Inputs
A3

A2

B3

B2

L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

V7483

Outputs
C2 = L
CO S3 S2
L
L
L
L
L
H
L
H
L
L
H
H
L
L
H
L
H
L
L
H
H
H
L
L
L
H
L
L
H
H
H
L
L
H
L
H
L
H
H
H
L
L
H
L
H
H
H
L

First 2 bit operation is same as the V7482.

The C2 is internal node signal like CO of V7482.

17

C2 = H
CO S3 S2
L
L
H
L
H
L
L
H
H
H
L
L
L
H
L
L
H
H
H
L
L
H
L
H
L
H
H
H
L
L
H
L
H
H
H
L
H
L
L
H
L
H
H
H
L
H
H
H

V7485

4 Bit Magnitude Comparator

FUNCTIONAL DESCRIPTION

LOGIC SYMBOL

Compares two 4 bit numbers which

activates one of three outputs; A less than
B, A equal B, and A greater than B

For proper compare operation, the AEB

signal in the initial stage must be held HIGH
for cascading applications

PIN DESCRIPTION
Pin Names
Description
Port A input (4-Bit)
Port B input (4-Bit)
Cascade input (A < B)
Cascade input AEB (A = B)
Cascade input AGB (A > B)
Active-HIGH output Y (A < B)
Active-HIGH output Y (A = B)
Active-HIGH output Y (A > B)

A0 A3
B0 B3
ALB
AEB
AGB
YALB
YAEB
YAGB

FUNCTION TABLE
Inputs
A3,B3
A3>B3
A3<B3
A3=B3
A3=B3
A3=B3
A3=B3
A3=B3
A3=B3
A3=B3
A3=B3
A3=B3

A2,B2
X
X
A2>B2
A2<B2
A2=B2
A2=B2
A2=B2
A2=B2
A2=B2
A2=B2
A2=B2

A1,B1
X
X
X
X
A1>B1
A1<B1
A1=B1
A1=B1
A1=B1
A1=B1
A1=B1

A0,B0
X
X
X
X
X
X
A0>B0
A0<B0
A0=B0
A0=B0
A0=B0

V7485

A>B A<B A=B

X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
L
L
H
L
L
L
H

Outputs
A>B A<B A=B
H
L
L
L
H
L
H
L
L
L
H
L
H
L
L
L
H
L
H
L
L
L
H
L
H
L
L
L
H
L
L
L
H

Any input status of the ALB,AEB and AGB not shown in the table is invalid.

18

V7486

Quad 2 Input XOR Gate

FUNCTIONAL DESCRIPTION

LOGIC SYMBOL

PIN DESCRIPTION
Pin Names
Description
A0 - D0
A1 - D1
YA YD

V7486

XOR gate A - D inputs 0

XOR gate A - D inputs 1
XOR gate A - D outputs

FUNCTION TABLE
Inputs

Outputs

Input0 Input1
L
L
L
H
H
L
H
H

Y
L
H
H
L

19

4 Independent 2 input XOR gates

V74133

Single 13 Input NAND Gate

LOGIC SYMBOL

V74133

FUNCTIONAL DESCRIPTION

PIN DESCRIPTION
Pin Names

One13 Input NAND gate

Description

A0 A12
YA

13 NAND-gate inputs
Output

FUNCTION TABLE
Inputs

Outputs

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12

H H H H H H H H H H H
H
H

Y
L
H

All the other cases

20

V74138

1 of 8 Decoder / Demultiplexer

V74138

FUNCTIONAL DESCRIPTION

LOGIC SYMBOL

PIN DESCRIPTION
Pin Names

Functionally compatible with TTL 74138

Three binary weighed inputs

Eight mutually exclusive Active-LOW

outputs

Three enable inputs allow parallel

expansion up to 1-of-32 decoder

Description

Decoder line inputs

Active-LOW enable inputs
Active-HIGH enable input
Active-LOW decoder outputs

A0 A2
EN1, EN2
EN3
Y0 Y7

FUNCTION TABLE
Inputs

EN1
H
X
X
L
L
L
L
L
L
L
L

EN2
X
H
X
L
L
L
L
L
L
L
L

EN3
X
X
L
H
H
H
H
H
H
H
H

A0
X
X
X
L
H
L
H
L
H
L
H

Outputs

A1
X
X
X
L
L
H
H
L
L
H
H

A2
X
X
X
L
L
L
L
H
H
H
H

Y0
H
H
H
L
H
H
H
H
H
H
H

21

Y1
H
H
H
H
L
H
H
H
H
H
H

Y2
H
H
H
H
H
L
H
H
H
H
H

Y3
H
H
H
H
H
H
L
H
H
H
H

Y4
H
H
H
H
H
H
H
L
H
H
H

Y5
H
H
H
H
H
H
H
H
L
H
H

Y6
H
H
H
H
H
H
H
H
H
L
H

Y7
H
H
H
H
H
H
H
H
H
H
L

V74139

Dual 1-of-4 Decoder

FUNCTIONAL DESCRIPTION

LOGIC SYMBOL

Dual 1-of-4 Independent decoder

Two inputs provide four mutually exclusive

Active- LOW outputs

Each 1-of-4 decoder has individual ActiveLOW enable input

PIN DESCRIPTION
Pin Names
Description
A0, A1
B0, B1
ENA
ENB
YA0 - YA3
YB0 - YB3

Decoder line inputs for decoder A

Decoder line inputs for decoder B
Active-LOW enable input for decoder A
Active-LOW enable input for decoder B
Active-LOW outputs for decoder A
Active-LOW outputs for decoder B

FUNCTION TABLE
Inputs
ENA
A1
A0
H
X
X
L
L
L
L
L
H
L
H
L
L
H
H

V74139

Outputs

Y0
H
L
H
H
H

Y1
H
H
L
H
H

Y2
H
H
H
L
H

Decoder B has the same functionality as A.

22

Y3
H
H
H
H
L

V74148

8 to 3 Priority Line Encoder

FUNCTIONAL DESCRIPTION

LOGIC SYMBOL

Generates 3 bit binary output code which

represents the highest order Active-LOW
data input

Encodes eight data lines to three binary

lines

Octal expansion by cascading ENI and

ENO

PIN DESCRIPTION
Pin Names
Description
8-bit input data lines (Active-LOW)
Input enable (Active-LOW)
3-bit binary output (Active-LOW)
Group signal output (Active-LOW)
Output enable (Active-LOW)

D0 D7
ENI
Y0 Y2
GS
ENO

FUNCTION TABLE
Inputs

ENI
H
L
L
L
L
L
L
L
L
L

D0
X
H
X
X
X
X
X
X
X
L

D1
X
H
X
X
X
X
X
X
L
H

D2
X
H
X
X
X
X
X
L
H
H

D3
X
H
X
X
X
X
L
H
H
H

D4
X
H
X
X
X
L
H
H
H
H

V74148

Outputs

D5
X
H
X
X
L
H
H
H
H
H

D6
X
H
X
L
H
H
H
H
H
H

D7
X
H
L
H
H
H
H
H
H
H

A2
H
H
L
L
L
L
H
H
H
H

23

A1
H
H
L
L
H
H
L
L
H
H

A0
H
H
L
H
L
H
L
H
L
H

GS
H
H
L
L
L
L
L
L
L
L

ENO
H
L
H
H
H
H
H
H
H
H

V74150

16-to-1 Multiplexer w/Enable

FUNCTIONAL DESCRIPTION

LOGIC SYMBOL

Decodes four data-select lines (S0 S3) to

select one out of 16 data sources

The enable input EN should be LOW to

enable the Y output

Active-Low outputs

PIN DESCRIPTION
Pin Names
A0 A15
S0 S3
EN
Y

Description
Data input lines
Data select lines
Enable input (Active-LOW)
Output (Active-LOW)

FUNCTION TABLE
Inputs

Outputs
Y

S3
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

S2

S1

S0

V74150

EN

An=L
An=H
X
X
X
H
H
H
L
L
L
L
H
L
L
L
H
L
H
L
L
H
L
L
H
L
L
H
H
L
H
L
H
L
L
L
H
L
H
L
H
L
H
L
H
H
L
L
H
L
H
H
H
L
H
L
L
L
L
L
H
L
L
L
H
L
H
L
L
H
L
L
H
L
L
H
H
L
H
L
H
L
L
L
H
L
H
L
H
L
H
L
H
H
L
L
H
L
H
H
H
L
H
L
The n represents a decimal conversion value of the S0-S3 input. When S0-S3 =07h, An = A7.

24

V74151

8-to-1 Multiplexer w/Enable

V74151

FUNCTIONAL DESCRIPTION

Decodes three data-select lines to select one

of eight data sources

The enable input EN should be LOW to

enable the Y output

Provides both Active-Low and Active-HIGH

outputs

LOGIC SYMBOL
PIN DESCRIPTION
Pin Names

FUNCTION TABLE
Inputs
S2

S1

S0

EN

X
L
L
L
L
H
H
H
H

X
L
L
H
H
L
L
H
H

X
L
H
L
H
L
H
L
H

H
L
L
L
L
L
L
L
L

Description
Data input lines
Data select lines
Enable input (Active-LOW)
Output (Active-HIGH)
Output (Active-LOW)

A0 A7
S0 S2
EN
Y
YN

Outputs
Y
An=L An=H
L
L
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

YN
An=L An=H
H
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L

The n represents a decimal conversion value of the S0-S2 input. When S0-S2 =07h, An = A7.

25

V74152

8-to-1 MUX, W/ LOW Output

LOGIC SYMBOL

PIN DESCRIPTION
Pin Names

FUNCTION TABLE
Inputs
S2
L
L
L
L
H
H
H
H

S1
L
L
H
H
L
L
H
H

FUNCTIONAL DESCRIPTION

Decodes three data input lines to select one

of eight data source

Provides an Inverted-MUX output signal

Description
Data input lines
Data select lines
Inverted-MUX output

A0 A7
S0 S2
Y

S0
L
H
L
H
L
H
L
H

V74152

Outputs
Y
An=L An=H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L

The n represents a decimal conversion value of the S0-S2 input. When S0-S2 =07h, An = A7.

26

V74153

Dual 4-to-1 Multiplexer w/Enable

LOGIC SYMBOL

PIN DESCRIPTION
Pin Names

FUNCTIONAL DESCRIPTION

Two 4-to-1 multiplexer with common dataselect lines

Each 4-to-1 MUX has an active-LOW

enable input line to enable the output

Description
Data A input lines
Enable A input (Active-LOW)
Data B input lines
Enable B input (Active-LOW)
Data select lines
Output A (Active-HIGH)
Output B (Active-HIGH)

A0 A3
ENA
B0 B3
ENB
S0 S1
YA
YB

FUNCTION TABLE
Inputs

S1
X
L
L
L
L
H
H
H
H

S0
X
L
L
H
H
L
L
H
H

A0
X
L
H
X
X
X
X
X
X

A1
X
X
X
L
H
X
X
X
X

A2
X
X
X
X
X
L
H
X
X

V74153

Outputs

A3
X
X
X
X
X
X
X
L
H

ENA
H
L
L
L
L
L
L
L
L

YA
L
L
H
L
H
L
H
L
H

MUX B has the same functionality as A.

27

V74154

1-of-4 Decoder / Demultiplexer

LOGIC SYMBOL

FUNCTIONAL DESCRIPTION

PIN DESCRIPTION
Pin Names
A0 A3
EN0, EN1
Y0 Y15

V74154

4 Inputs provides16 mutually exclusive

active-LOW outputs

Two enable inputs, EN0 and EN1, are used

to enable MUX and to cascade multiple
V74154 macros

Description

Decoder line inputs

Active-LOW enable inputs
Active-LOW outputs

FUNCTION TABLE
Inputs
EN1 EN2 A0 A1 A2 A3
H
H
X X X X
H
L
X X X X
L
H
X X X X
L
L
L L L L
L
L
H L L L
L
L
L H L L
L
L
H H L L
L
L
L L H L
L
L
H L H L
L
L
L H H L
L
L
H H H L
L
L
L L L H
L
L
H L L H
L
L
L H L H
L
L
H H L H
L
L
L L H H
L
L
H L H H
L
L
L H H H
L
L
H H H H

Outputs (Y)
0
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

1
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H

2
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H

3
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H

4
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H

5
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H

28

6
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H

7
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H

8
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H

9
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H

10
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H

11
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H

12
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H

13
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H

14
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H

15
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L

V74157

Quad 2-to-1 Multiplexer

LOGIC SYMBOL

PIN DESCRIPTION
Pin Names

FUNCTIONAL DESCRIPTION

Selects one of two 4-Bit words based on the

select line

Active-LOW common enable input

Common data select line

Description
MUX A inputs
MUX B inputs
MUX C inputs
MUX D inputs
Common data select lines
Active-LOW enable input
MUX (A D) outputs

A0, A1
B0, B1
C0, C1
D0, D1
S
EN
YA, YB, YC, YD

FUNCTION TABLE
Inputs

EN
H
L
L

S
X
L
H

Outputs

YA
L
A0
A1

YB
L
B0
B1

V74157

YC
L
C0
C1

YD
L
D0
D1

29

V74158

Quad 2-to-1 Multiplexer Low-Out

LOGIC SYMBOL

PIN DESCRIPTION
Pin Names
A0, A1
B0, B1
C0, C1
D0, D1
S
EN
YA, YB, YC, YD

FUNCTIONAL DESCRIPTION

Selects one of two 4-Bit words based on

the select line

Active-LOW MUX output

Active-LOW common enable input

Common data select line

Description
MUX A inputs
MUX B inputs
MUX C inputs
MUX D inputs
Data select Lines
Active-LOW enable input
Active-LOW MUX (A D) outputs

FUNCTION TABLE
Inputs

EN
H
L
L

S
X
L
H

Outputs

YA
H
/A0
/A1

YB
H
/B0
/B1

V74158

YC
H
/C0
/C1

YD
H
/D0
/D1

30

V74161

Loadable 4-Bit Binary Counter

LOGIC SYMBOL

V74161

FUNCTIONAL DESCRIPTION

4-bit wide binary counter

Synchronous parallel load

Asynchronous Active-LOW reset

Two enable input lines, CEP & CET

An Active-HIGH terminal count (TC) is

generated when the count is 0Fh and the CET
is HIGH

To cascade the counter, feed the TC to the

input of the next stage counter

PIN DESCRIPTION
Pin Names
Description
D0 D3
CET
CEP
LD
CL
CK
Q0 Q3
TC

4 bit data Input

Clock enable trickle input
Clock enable parallel input
Synchronous load enable input (Active-LOW)
Asynchronous clear input (Active-LOW)
Clock pulse input (Active-rising-edge)
Counter outputs
Terminal-count output

FUNCTION TABLE
Inputs

Outputs
CK CL LD CEP CET D0 D1 D2 D3
Q0 Q1 Q2 Q3 TC
X
L
X
X
X
X
X
X
X
L
L
L
L
L
r
H
L
X
X
a
b
c
d
a
b
c
d
X
r
H
H
H
H
X
X
X
X
Count Up
*
r
H
H
L
X
X
X
X
X
Hold Count
*
r
H
H
X
L
X
X
X
X
Hold Count
*
* The TC is HIGH when the counter output is 0Fh and CET is HIGH. Otherwise, it stays LOW.

31

V74162

4-Bit BCD/Decade Counter

LOGIC SYMBOL

V74162

FUNCTIONAL DESCRIPTION

4-bit wide BCD/ Decade up counter

Synchronous parallel load

Synchronous Active-LOW reset

Two enable input lines, ENP & ENT

An Active-HIGH terminal-count signal (TC) is

generated when the count is 9h and the ENT is
HIGH

To increment the counter width, feed the TC to

the ENT and ENP inputs of the next stage macro

The implementation of V74162 is based on

Fairchild TTL databook. Please note that the
state transitions for this macro differ when data
sheets of several vendors are compared.

PIN DESCRIPTION
Pin Names
Description
D0 D3
ENP
ENT
LD
CL
CK
Q0 Q3
TC

4-Bit counter data inputs

Active-HIGH count enable input
Active-HIGH count and terminal-count enable input
Active-LOW synchronous load enable input
Active-LOW synchronous reset input
Clock input
4-Bit BCD count outputs
Active-HIGH terminal count output

FUNCTION TABLE
Inputs

Outputs
CK CL LD ENP ENT D0 D1 D2 D3
Q0 Q1 Q2 Q3 TC
r
L
X
X
X
X
X
X
X
L
L
L
L
L
r
H
L
X
X
a
b
c
d
a
b
c
d
X
r
H
H
H
H
X
X
X
X
Count Up
*
r
H
H
L
X
X
X
X
X
Hold Count
*
r
H
H
X
L
X
X
X
X
Hold Count
*
* The TC is HIGH when the counter output is 09d and the ENT is HIGH. Otherwise, it stays LOW.

32

V74163

4 Bit Binary Counter w/Sync

LOGIC SYMBOL

V74163

FUNCTIONAL DESCRIPTION

4-bit wide binary counter

Synchronous parallel load

V74163 has a synchronous Active-LOW

reset, while V74161 has an asynchronous
one

Two enable input lines, ENP & ENT

An Active-HIGH terminal count (TC) is

generated when the count is 0Fh and the
ENT is HIGH

To cascade the counter, feed the TC to the

input of the next stage counter

PIN DESCRIPTION
Pin Names
Description
D0 D3
ENT
ENP
LD
CL
CK
Q0 Q3
TC

4 bit data Input

Clock enable trickle input
Clock enable parallel input
Synchronous load enable input (Active-LOW)
Synchronous clear input (Active-LOW)
Clock pulse input (Active-rising-edge)
Counter outputs
Terminal-count output

FUNCTION TABLE
Inputs

Outputs
CK CL LD ENP ENT D0 D1 D2 D3
Q0 Q1 Q2 Q3 TC
r
L
X
X
X
X
X
X
X
L
L
L
L
L
r
H
L
X
X
a
b
c
d
a
b
c
d
X
r
H
H
H
H
X
X
X
X
Count Up
*
r
H
H
L
X
X
X
X
X
Hold Count
*
r
H
H
X
L
X
X
X
X
Hold Count
*
* The TC is HIGH when the counter output is 0Fh and ENT is HIGH. Otherwise, it stays LOW.

33

V74164

8 Bit SIPO Shift Register

FUNCTIONAL DESCRIPTION

LOGIC SYMBOL

8-bit serial-in parallel-out shift register

Active-LOW asynchronous reset input

2 serial inputs are logically ANDed

Risingedge clock input

PIN DESCRIPTION
Pin Names
Description
Shift register line inputs
Active-LOW asynchronous clear input
Clock input (Active-rising-edge)
Shift register 8-bit parallel outputs

A0, A1
CL
CK
Q0 Q7

FUNCTION TABLE
CK
X
r
r
r

Inputs
CL
A1
L
X
H
L
H
X
H
H

A0
X
X
L
H

Q0
L
L
L
H

V74164

Q1
L
Q0
Q0
Q0

Q2
L
Q1
Q1
Q1

Outputs
Q3 Q4 Q5
L
L
L
Q2 Q3 Q4
Q2 Q3 Q4
Q2 Q3 Q4

34

Q6
L
Q5
Q5
Q5

Q7
L
Q6
Q6
Q6

V74166

8 Bit PISO Shift Register

FUNCTIONAL DESCRIPTION

LOGIC SYMBOL

8-bit parallel-in serial-out, serial-in serial out

shift register

Active-LOW asynchronous reset input

Active-LOW synchronous load input

Active-LOW synchronous clock enable

input (TTL has an asynchronous clock
enable)

Risingedge shift clock input

Setting the CE to HIGH inhibits shifting and

the registers retain their current values

PIN DESCRIPTION
Pin Names
Description
Serial data input
8-bit parallel input
Synchronous parallel load enable (Active-LOW)
Asynchronous clear input (Active-LOW)
Clock enable input (Active-LOW)
Clock pulse input (Active-rising-edge)
Shift register serial output

SDI
D0 D7
LD
CL
CE
CK
Q7

FUNCTION TABLE
LD
X
L
H
H
X

CE
X
L
L
L
H

Inputs
CK CL
X L
r H
r H
r H
r H

SDI
X
X
L
H
X

Q0
L
D0
L
H
Q0

V74166

Q1
L
D1
Q0
Q0
Q1

Q2
L
D2
Q1
Q1
Q2

Q3
L
D3
Q2
Q2
Q3

Outputs
Q4 Q5
L
L
D4 D5
Q3 Q4
Q3 Q4
Q4 Q5

35

Q6
L
D6
Q5
Q5
Q6

Q7
L
D7
Q6
Q6
Q7

V74168

4-Bit Up/Down BCD Counter

V74168

FUNCTIONAL DESCRIPTION

LOGIC SYMBOL

4-bit wide BCD up/ down count

Synchronous parallel load

No reset function available

Separate up / down control inputs

An Active-LOW terminal-count signal (TC)

is generated when the count is 09h and
U_DN is high or when the count is 0h and
U_DN is low

PIN DESCRIPTION
Pin Names
Description
Parallel counter data inputs
Up/Down Count Control, HIGH for up mode, LOW for down mode
Enable parallel input (Active-LOW)
Enable trickle input (Active-LOW)
Load enable input(Active LOW)
Clock input
Counter outputs
Terminal-count output (Active-LOW)

D0 D3
U_DN
ENP
ENT
LD
CK
Q0 Q3
TC

FUNCTION TABLE
Inputs
CK
r
r
r
r
r

LD U_DN
L
X
H
H
H
L
H
H
H
L

D0
a
X
X
X
X

D1
b
X
X
X
X

D2
c
X
X
X
X

D3
d
X
X
X
X

Outputs
Q0 Q1 Q2 Q3
a
b
c
d
Count Up
Count Down
H
L
L
H
L
L
L
L

36

TC
X
H
H
L
L

V74169

4 Bit Up/Down Binary Counter

V74169

FUNCTIONAL DESCRIPTION

LOGIC SYMBOL

Synchronous 4 stage up/down counter

Preset capability for programmable

operation

U_DN input to control direction of count

Parallel loading by the LOW to HIGH clock

transition

PIN DESCRIPTION
Pin Names
Description
Parallel counter data inputs
Up/Down Count Control, HIGH for up mode, LOW for down mode
Enable parallel input (Active-LOW)
Enable trickle input (Active-LOW)
Load enable input(Active-LOW)
Clock input
Binary counter outputs
Terminal-count output (Active-LOW)

D0 - D3
U_DN
ENP
ENT
LD
CK
Q0 Q3
TC

FUNCTION TABLE
Inputs
CK
r
r
r
r
r

LD U_DN
L
X
H
H
H
L
H
H
H
L

D0
a
X
X
X
X

D1
b
X
X
X
X

D2
c
X
X
X
X

D3
d
X
X
X
X

Outputs
Q0 Q1 Q2 Q3
a
b
c
d
Count Up
Count Down
H
H
H
H
L
L
L
L

37

TC
X
H
H
L
L

V74174

Hex D-Flip Flop with Clear

FUNCTIONAL DESCRIPTION

LOGIC SYMBOL

6 flip/flops with single rail outputs

Rising-edge clock and Active-LOW

asynchronous clear inputs

Individual data input to each D-flip/flop

PIN DESCRIPTION
Pin Names
Description
D-flip/flop data inputs
Clear input (Active-LOW)
Clock input
D-flip/flop data outputs

D1 D6
CL
CK
Q1 Q6

FUNCTION TABLE
Inputs
CL
L
H
H
H

CK
X
r
r
L

D
X
H
L
X

V74174

Outputs
Q
L
H
L
Q

38

V74181

4 Bit Arithmetic Logic Unit

LOGIC SYMBOL

V74181

FUNCTIONAL DESCRIPTION

Provides 16 arithmetic operations such as

add, subtract, compare, and etc

Provides 16 logic operations such as XOR,

compare, AND, NAND, OR, NOR, and etc

Provides look-ahead carry for high speed

arithmetic function

PIN DESCRIPTION
Pin Names
Description
ALU input A
ALU input B
Function select input (Active-LOW)
Mode control input
Carry input
Function output (Active-LOW)
Carry generate output (Active-LOW)
Carry propagate output (Active-LOW)
Equality comparator output
Carry output

A0 A3
B0 B3
S0 S3
M
CI
F0 F3
G
P
AEQB
CO

FUNCTION TABLE
Mode Select
Input
S3
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

S2
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

S1
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

S0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

Active Low
Logic
(M=H)
/A
/(A*B)
/(A+B)
/(A+B)
/(A+B)
/B
/(A+B)
A+/B
/A*B
A+B
B
A+B
Logic 0
A*/B
A*B
A

Operands
Arithmetic

(M=L, CI=L)
A minus 1
A*B minus 1
A*/B minus 1
Minus 1
A plus (A+/B)
A*B plus (A+/B)
A minus B minus 1
A+/B
A plus (A+B)
A plus B
A*/B plus (A+B)
A+B
A plus A
A*B plus A
A*/B minus A
A

39

Active High Operands

Logic
(M=H)
/A
/(A+B)
/A*B
Logic 0
/(A*B)
/B
A+B
A+/B
/A+B
/(A+B)
B
A*B
/(A+B)
A+/B
A+B
A

Arithmetic
(M=L, CI=H)
A
A+B
A+/B
Minus 1
A plus A*/B
(A+B) plus A*/B
A minus B minus 1
A*/B minus 1
A plus A*B
A plus B
(A+/B) plus A*B
A*B minus 1
A plus A
(A+B) plus A
(A+/B) plus A
A minus 1

V74182

Look Ahead Carry Generator

LOGIC SYMBOL

FUNCTIONAL DESCRIPTION

Provides look-ahead carries across 4

binary adders or group of adders

Generally used with the V74181 ALU to

provide high-speed look-ahead carry
implementation

Carry, generate-carry, and propagate-carry

functions are provided

PIN DESCRIPTION
Pin Names
Description
Cn
G0 G3
P0 P3
Cnx, Cny, Cnz
G
P

Carry Input
Input carry generate (Active-LOW)
Input carry propagate (Active-LOW)
Carry output
Carry generate output (Active-LOW)
Carry propagate output (Active-LOW)

FUNCTION TABLE
G3
L
X
X
X

Inputs

Outputs

G2 G1 G0 P3 P2 P1
X
X
X
X
X
X
L
X
X
L
X
X
X
L
X
L
L
X
X
X
L
L
L
L
All Other Combinations

G
L
L
L
L
H

Inputs
P3 P2 P1 P0
L
L
L
L
All Other Combinations

V74182

Outputs
P
L
H

40

V74273

Octal D Flip Flops with Clear

LOGIC SYMBOL

FUNCTIONAL DESCRIPTION

Octal D-FF with asynchronous reset

Individual data input to each D flip flop

PIN DESCRIPTION
Pin Names
Description
8-bit D-flip/flop data inputs
Asynchronous clear input (Active-LOW)
Clock input
8-bit D-flip/flop outputs

D0 D7
CL
CK
Q0 Q7

FUNCTION TABLE
Inputs
CL
L
H
H
H

CK
X
r
r
L

D
X
L
H
X

V74273

Outputs
Q
L
L
H
Q

41

V74280

9 Bit Odd/Even Parity

LOGIC SYMBOL

FUNCTIONAL DESCRIPTION

Combinatorial circuit which generates or

checks either Odd or Even parity on nine
data lines

Cascade for n bits

PIN DESCRIPTION
Pin Names
Description
A0 A8
SE
SO

V74280

Input data lines

Even parity sum output
Odd parity sum output

FUNCTION TABLE
Inputs

Outputs

Number of Inputs A0 A8 that

are high
0, 2, 4, 6, 8
1, 3, 5, 7, 9

SE
H
L

42

SO
L
H

V74283

4 Bit Full Adder with Fast Carry

LOGIC SYMBOL

V74283

FUNCTIONAL DESCRIPTION

Performs addition of two 4 bit binary words

Full carry look ahead across the four bits

PIN DESCRIPTION
Pin Names
Description
CI
A0 A3
B0 B3
S0 S3
CO

Carry input
4-bit A inputs
4-bit B inputs
4-bit sum 0 3 outputs
Resultant carry output from 4th bit

FUNCTION DESCRIPTION AND EXAMPLE

DESCRIPTION: The V74283 adds two 4 bit binary words (A plus B) along with the incoming carry
(CI). The resultant sum appears at the output Sum (S0-S3) and outgoing carry at CO. The binary
weight of the various inputs and outputs is indicated be the subscript numbers, representing
powers of two.
20 (A0 + B0 + CI) + 21 (A1 + B1) + 22 (A2 + B2) + 23 (A3 + B3) = S0 + 2S1 + 4S2 + 8S3 + 16CO
where (+) = plus
Interchanging inputs of the equal weight does not effect the operation. Thus CI, A0, B0 can be
arbitrarily assigned so various pins. Due to the symmetry of the binary add function, the V74283
can be used with all inputs and outputs Active-HIGH (positive logic) or with inputs and outputs
Active-LOW (negative logic). Note that if CI is not used it must be tied LOW for Active-HIGH logic
or tied HIGH for Active-LOW logic.
EXAMPLE:
Logic Levels
Active HIGH
Active LOW

CI
L
0
1

A0
L
0
1

A1
H
1
0

A2
L
0
1

A3
H
1
0

B0
H
1
0

B1
L
0
1

43

B2
L
0
1

B3
H
1
0

S0
H
1
0

S1
H
1
0

S2
L
0
1

S3
L
0
1

C4
H
1
0

V74298

Quad 2-to-1 Mux with Storage

FUNCTIONAL DESCRIPTION

LOGIC SYMBOL

PIN DESCRIPTION
Pin Names

Selects one of two 4 bit words and stores

each bit in a register on rising edge of clock

The selected data is transferred to the 4-bit

output register synchronous with the fallingedge clock

Description
Data inputs for input0
Data inputs for input1
Select input
Falling-edge clock
Storage-MUX outputs

A0, B0, C0, D0

A1, B1, C1, D1
S
CK
QA, QB, QC, QD

FUNCTION TABLE
Inputs
CK
H
f
f

S
X
L
H

Outputs
QA
QA
A0
A1

QB
QB
B0
B1

QC
QC
C0
C1

V74298

QD
QD
D0
D1

44

V74352

Dual 4-to-1 Mux with Enable

LOGIC SYMBOL

FUNCTIONAL DESCRIPTION

Two 4-to-1 multiplexer with common dataselect lines

Each 4-to-1 MUX has an Active-LOW

enable input line to enable the output

Active-LOW outputs

Inverted version of V74153

PIN DESCRIPTION
Pin Names
Description
A0 A3
ENA
B0 B3
ENB
S0 S1
YA
YB

MUX A 4 input lines

Enable A (Active-LOW)
MUX B 4 input Lines
Enable B (Active-LOW)
Common data select lines
MUX A output (Active-LOW)
MUX B output (Active-LOW)

FUNCTION TABLE
Inputs

V74352

Outputs

S1 S0 A0 A1 A2 A3 ENA
X
X
X
X
X
X
H
L
L
L
X
X
X
L
L
L
H
X
X
X
L
L
H
X
L
X
X
L
L
H
X
H
X
X
L
H
L
X
X
L
X
L
H
L
X
X
H
X
L
H
H
X
X
X
L
L
H
H
X
X
X
H
L
MUX B has the same functionality as A.

YA
H
H
L
H
L
H
L
H
L

45

V74377

Octal D Flip-Flop w/ Data enable

LOGIC SYMBOL

PIN DESCRIPTION
Pin Names

FUNCTIONAL DESCRIPTION

Eight D flip-flop with common Active-LOW

data enable input

Individual data input to each D flip-flop

Ideal for addressable register application

Data enable acts as synchronous clock

enable

Description
8-bit D flip-flop data inputs
Data enable input (Active-LOW)
Clock input
8-bit D flip-flop data outputs

D0 D7
EN
CK
Q0 Q7

FUNCTION TABLE
Inputs
EN
H
L
L
X

CK
X
r
r
L

D
X
H
L
X

V74377

Outputs
Q
Q
H
L
Q

46

V74518

8-Bit Identity Comparator

FUNCTIONAL DESCRIPTION

LOGIC SYMBOL

Compares two 8 bit numbers and sets Y

output HIGH if two numbers are equal

The Active-HIGH enable input must be held

HIGH to enable the Y output

PIN DESCRIPTION
Pin Names
Description
8 bit input data lines
8 bit input data lines
Enable input (Active-HIGH)
Comparator output

A0 A7
B0 B7
EN
YAEB

FUNCTION TABLE
Inputs
Data
A(7:0) =
A(7:0) >
A(7:0) <
X

A,B
B(7:0)
B(7:0)
B(7:0)

Outputs
EN
H
H
H
L

V74518

Y
H
L
L
L

47

V74521

8-Bit Comparator w/ Low Output

FUNCTIONAL DESCRIPTION

LOGIC SYMBOL

Compares two 8 bit numbers and sets

YAEB output LOW if two numbers are
equal

The enable input must be held LOW to

enable the YAEB output

PIN DESCRIPTION
Pin Names
Description
8-bit input data lines
8-bit input data lines
Enable input (Active-LOW)
Comparator output (Active-LOW)

A0 A7
B0 B7
EN
YAEB

FUNCTION TABLE
Inputs
Data
A(7:0) =
A(7:0) >
A(7:0) <
X

A,B
B(7:0)
B(7:0)
B(7:0)

Outputs
EN
L
L
L
H

V74521

YAEB
L
H
H
H

48