Addition

Full adder (FA) logic circuit: adds two bits of the same weight, along with a ca
rry-in bit, and produces a sum bit and a carry-out bit
Ripple-carry adder: a chain of n FA stages, linked by carry bits, can add two nbit numbers
:
Addition/subtraction
circuit
An n-bit adder with external XOR gates can add or subtract two operands. An FA s
tage produces its outputs after 2 logic gate delays
Longest delay path through the adder/subtractor circuit: 2n gate delays, assumin
g a ripple-carry design
Carry-lookahead addition:
Delay reduction: produce carry signals in parallel using carry-lookahead circuit
s
First, form generate (Gi) and propagate (Pi) functions in each stage i
Carry-lookahead circuits: A 4-bit adder has four carry-out signals
Delay in 4-bit adder
Ripple-carry design: 8 gate delays
Carry-lookahead design: 1 for all Pi and Gi, 2 for all ci, 1 for all si, 4 gate
delays
Carry-lookahead for larger n:
Logic gate fan-in constraints limit direct formation of all ci in 2 gate delays
for n larger than about 4
Higher-level generate and propagate functions are used for 4-bit blocks and 16-b
it blocks (Add hardware since we have more transistors on each die.)
Adder delay in longer adders
16-bit adder: 8 gate delays 64-bit adder: 12 gate delays
Compare these delays to 32 and 128 gate delays, respectively, for 16-bit and 64bit ripple-carry adders
Multiplication
Two, n-bit, unsigned numbers produce a 2n-bit product when they are multiplied
Multiplication can be done in a 2-dimensional combinational array composed of n^
2 basic cells, each containing an FA block, arranged in a trapezoidal shape
Longest delay path is approximately 6n gate delays, along the right edge and acr
oss the bottom of the array
Sequential circuit multiplier is composed of three n-bit registers, a n-bit adde
r, and a control sequencer (FSM)
A sequence of n addition cycles generates a 2nbit product
Delay = n x (adder + control delays) For n = 32, delay is approximately 32 x 14,
or 448 gate delays, assuming a carry- lookahead adder
more than twice the delay of the corresponding array multiplier
Multiplying signed numbers
Dealing with a negative multiplicand is described first Then, the Booth algorith
m is introduced as a way to deal with negative multipliers
High-speed multipliers
Neither the combinational array nor the sequential circuit multiplier are fast e
nough for high-performance processors
Two approaches can be used for higher speed: (1)Reduce the number of summands (2
)Use more parallelism in adding them
Division
Sequential circuit divider is composed of three n-bit registers, an n-bit add/su

btract unit, and a control sequencer

A sequence of n addition/subtraction cycles generates an n-bit quotient and an n
-bit remainder
For n=32, delay is approximately 450 gate delays, similar to a sequential multip
lier
Floating Point Numbers
The value represented is +/- 1.M x 2E E is actually encoded as E
is called an excess-127 representation

= E + 127 which

FP Addition/Subtraction
(1)Shift mantissa of number with smaller exponent to the right (2)Set exponent o
f result to larger exponent
(3)Perform addition/subtraction of mantissas and set sign of result (4)Normalize
the result, if necessary
FP Multiplication
(1)Add exponents and subtract 127 (to maintain excess-127 representation) (2)Mul
tiply mantissas, determine sign of result
(3)Normalize result, if necessary
FP Division
(1)Subtract exponents and add 127 (to maintain excess-127 representation) (2)Div
ide mantissas, determine sign of result
(3)Normalize result, if necessary
Guard Bits
Extra bits added to fraction during calculation. Need to be removed when storing
result
Truncation of FP mantissas
The mantissa resulting from an arithmetic operation on two floating-point number
s is longer than 24 bits
It must be truncated to 24 bits The IEEE standard requires that rounding to the
nearest 24-bit value is the truncation method to be used
Truncation
Chop off bits: Error: 0 1, biased
Von Neuman: any 1 s in guard, LSB is 1: Error: -1 - +1, unbiased
Rounding: 1 in MSB of guard, LSB is 1: Error: -1/2 - +1/2, unbiased