3 1 Cse Mpi Unit 1

NRI Institute Of Technology
UNIT I
8086 INTRODUCTION
1.1) An over view of 8085
1.2) Architecture of 8086 Microprocessor
1.3) Special functions of General purpose registers
1.4) 8086 flag register and function of 8086 Flags
1.5) Addressing modes of 8086
1.6) Instruction set of 8086
1.7) Assembler directives
1.8) Procedures, and macros
CSE III B.Tech I SEMESTER
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1.1) An over view of 8085:

Sub Topics:
1) Block diagram of 8085 microprocessor
2) 8085 system bus
3) 8085 registers
4) Timing and Control unit
5) Interrupt control unit
6) 8085 PIN DIAGRAM
1) Block diagram of 8085 microprocessor:
Fig1.1: Block Diagram of 8085 microprocessor
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2) 8085 system bus:
Address Bus:
The address bus is a group of 16 lines generally identified as A0 to A15.
The address bus is unidirectional: bits flow in one direction-from the MPU to
peripheral devices.
The MPU uses the address bus to perform the first function: identifying a peripheral
or a memory location.
Fig1.2: 8085 bus structure

Data Bus:
The data bus is a group of eight lines used for data flow. These lines are bidirectional data flow in both directions between the MPU and memory and
peripheral devices.
The MPU uses the data bus to perform the second function: transferring binary
information.
The eight data lines enable the MPU to manipulate 8-bit data ranging from 00 to FF
(28 = 256 numbers).
The largest number that can appear on the data bus is 11111111.
Control Bus:
The control bus carries synchronization signals and providing timing signals.
The MPU generates specific control signals for every operation it performs. These
signals are used to identify a device type with which the MPU wants to
communicate.
3) 8085 Registers:
The 8085 have six general-purpose registers to store 8-bit data during program
execution.
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These registers are identified as B, C, D, E, H, and L.

They can be combined as register pairs-BC, DE, and HL-to perform some 16-bit
operations.
Fig 1.3: 8085 Registers

Accumulator (A):
The accumulator is an 8-bit register that is part of the arithmetic/logic unit (ALU).
This register is used to store 8-bit data and to perform arithmetic and logical
operations.
The result of an operation is stored in the accumulator.
Flags:
The ALU includes five flip-flops that are set or reset according to the result of an
operation.
The microprocessor uses the flags for testing the data conditions. They are Zero (Z),
Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags.
The most commonly used flags are Sign, Zero, and Carry.
The bit position for the flags in flag register is,
A) Sign Flag (S):

After execution of any arithmetic and logical operation, if D7 of the result is 1, the
sign flag is set.
Otherwise it is reset. D7 is reserved for indicating the sign.
The remaining is the magnitude of number. If D7 is 1, the number will be viewed as
negative number. If D7 is 0, the number will be viewed as positive number.
B) Zero Flag (z):
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If the result of arithmetic and logical operation is zero, then zero flag is set
otherwise it is reset.
C) Auxiliary Carry Flag (AC):
If D3 generates any carry when doing any arithmetic and logical operation, this
flag is set. Otherwise it is reset.
D) Parity Flag (P):
If the result of arithmetic and logical operation contains even number of 1's then
this flag will be set and if it is odd number of 1's it will be reset.
E) Carry Flag (CY):
If any arithmetic and logical operation result any carry then carry flag is set
otherwise it is reset.
iii) Arithmetic and Logic Unit (ALU):
It is used to perform the arithmetic operations like addition, subtraction,
multiplication, division, increment and decrement and logical operations like
AND, OR and EX-OR.
It receives the data from accumulator and registers. According to the result it set
or reset the flags.
iv) Program Counter (PC):
This 16-bit register is used to sequencing the execution of instructions.
It is a memory pointer. Memory locations have 16-bit addresses, and that is why
this is a 16-bit register.
The function of the program counter is to point to the memory address of the next
instruction to be executed.
When an opcode is being fetched, the program counter is incremented by one to
point to the next memory location.
v) Stack Pointer (Sp)
The stack pointer is also a 16-bit register used as a memory pointer.
It points to a memory location in R/W memory, called the stack.
The beginning of the stack is defined by loading a 16-bit address in the stack
pointer (register).
vi) Temporary Register:
It is used to hold the data during the arithmetic and logical operations.
vii) Instruction Register:
When an instruction is fetched from the memory, it is loaded in the instruction
Register.
viii) Instruction Decoder:
It gets the instruction from the instruction register and decodes the instruction.
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It identifies the instruction to be performed.
ix) Serial I/O Control:
It has two control signals named SID and SOD for serial data transmission.
4) Timing and Control unit:
It has three control signals ALE, RD (Active low) and WR (Active low) and three
status signals IO/M (Active low), S0 and S1.
ALE is used for provide control signal to synchronize the components of
miroprocessor and timing for instruction to perform the operation.
RD (Active low) and WR (Active low) are used to indicate whether the operation
is reading the data from memory or writing the data into memory respectively.
IO/M (Active low) is used to indicate whether the operation is belongs to the
memory or peripherals.
5) Interrupt Control Unit:
It receives hardware interrupt signals and sends an acknowledgement for receiving

the interrupt signal.
Interrupt is nothing but signals send by an external device to the processor, to request
the processor to perform a particular task or work.
Mainly in the microprocessor based system the interrupts are used for data transfer
between the peripheral and the microprocessor.
The processor will check the interrupts always at the 2nd T-state of last machine
cycle.
If there is any interrupt it accept the interrupt and send the INTA (active low) signal
to the peripheral.
The vectored address of particular interrupt is stored in program counter.
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The processor executes an interrupt service routine (ISR) addressed in program

counter. It returned to main program by RET instruction.
Types of Interrupts:
It supports two types of interrupts.
i) Software
ii) Hardware
i) Software interrupts:
The software interrupts are program instructions.
These instructions are inserted at desired locations in a program.
The 8085 has eight software interrupts from RST 0 to RST 7.
The vector address for these interrupts can be calculated as follows.
Interrupt number * 8 = vector address
EX: - For RST 5, 5 * 8 = 40 = 28H
Vector address for interrupt RST 5 is 0028H
The Table shows the vector addresses of all interrupts.
ii) Hardware Interrupts:

An external device initiates the hardware interrupts and placing an appropriate signal
at the interrupt pin of the processor.
If the interrupt is accepted then the processor executes an interrupt service routine.
The 8085 has five hardware interrupts
(1) TRAP
(2) RST 7.5
(3) RST 6.5
(4) RST 5.5
(5) INTR
(1) TRAP:
This interrupt is a non-maskable interrupt. It is unaffected by any mask or interrupt
enable.
TRAP is the highest priority and vectored interrupt.
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TRAP interrupt is edge and level triggered.

This means hat the TRAP must go high and remain high until it is acknowledged. In
sudden power failure, it executes a ISR and send the data from main memory to
backup memory.
The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor
receives HOLD and TRAP at the same time then HOLD is recognized first and then
TRAP is recognized).
There are two ways to clear TRAP interrupt.
By resetting microprocessor (External signal)
By giving a high TRAP ACKNOWLEDGE (Internal signal)
(2) RST 7.5:

The RST 7.5 interrupt is a maskable interrupt.
It has the second highest priority.
It is edge sensitive (i.e) Input goes to high and no need to maintain high state until it
is recognized.
It is disabled by, 1.DI instruction 2.System or processor reset. 3.After reorganization
of interrupt.
It is enabled by EI instruction.
(3) RST 6.5 and 5.5:
The RST 6.5 and RST 5.5 both are level triggered. (i.e) Input goes to high and stay high
until it recognized.
Maskable interrupt. It is disabled by, 1.DI, SIM instruction 2.System or processor
reset. 3. after reorganization of interrupt.
Enabled by EI instruction.
The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.
(4) INTR:
INTR is a maskable interrupt. It is disabled by, 1.DI, SIM instruction 2.System or
processor reset. 3. after reorganization of interrupt.
a)
It is enabled by EI instruction.
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b)
It is non-vectored interrupt. After receiving INTA (active low) signal, it has to
supply the address of ISR.
c)
It has lowest priority.
d)
It is a level sensitive interrupts. ie. Input goes to high and it is necessary to
maintain high state until it recognized.
HARDWARE INTERRUPTS TABLE:
INTERRUPT MASKBLE/NON
PRIO
TYPE
MASKABLE
RITY
TRAP
NON MASKABLE
1
RST 7.5
MASKABLE
2
RST 6.5
MASKABLE
3
RST 5.5
MASKABLE
4
INTR
MASKABLE
5
EDGE/LEVEL
SENSITIVE
EDGE&LEVEL
EDGE
LEVEL
LEVEL
LEVEL
VECTORED/NON
VECTORED
VECTORED
VECTORED
VECTORED
VECTORED
NON VECTORED
6) 8085 PIN DIAGRAM:

The microprocessor is a clock-driven semiconductor device consisting of electronic
logic circuits manufactured by using either a large-scale integration (LSI) or very-largescale integration (VLSI) technique.
The microprocessor is capable of performing various computing functions and
making decisions to change the sequence of program execution.
In large computers, a CPU implemented on one or more circuit boards performs these
computing functions.
The microprocessor is in many ways similar to the CPU, but includes the logic
circuitry, including the control unit, on one chip.
The microprocessor can be divided into three segments for the sake clarity,
arithmetic/logic unit (ALU), register array, and control unit.
8085 is a 40 pin IC, DIP package. The signals from the pins can be grouped as follows
i) Power supply and clock signals
ii) Address bus
iii) Multiplexed Address / Data Bus
iv) Control and status signals
v) Interrupts and externally initiated signals
vi) Direct memory access
vii) Serial I/O ports
i) Power supply and Clock frequency signals:
Vcc
+ 5 volt power supply
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Vss
Ground
X1, X2: Crystal or R/C network or LC network connections to set the frequency
of internal clock generator.
The frequency is internally divided by two. Since the basic operating timing
frequency is 3 MHz, a 6 MHz crystal is connected externally.
CLK (output)-Clock Output is used as the system clock for peripheral and devices
interfaced with the microprocessor.
ii)
Address Bus:
A8 - A15 lines.
It carries the most significant 8 bits of the memory address or the 8 bits of the I/O
address.
iii)
Multiplexed Address / Data Bus:
AD0 - AD7 (input/output; 3-state)
These multiplexed set of lines used to carry the lower order 8 bit address as well
as data bus.
During the opcode fetch operation, in the first clock cycle, the lines deliver the
lower order address A0 - A7.
In the subsequent IO / memory, read / write clock cycle the lines are used as data
bus.The CPU may read or write out data through these lines.
Fig (a) - Pin Diagram of 8085 & Fig (b) - logical schematic of Pin diagram.
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iv)
Control and Status signals:
ALE (output) - Address Latch Enable.
This signal helps to capture the lower order address presented on the multiplexed
address / data bus.
RD (output 3-state, active low) - Read memory or IO device.
This indicates that the selected memory location or I/O device is to be read and
that the data bus is ready for accepting data from the memory or I/O device.
WR (output 3-state, active low) - Write memory or IO device.
This indicates that the data on the data bus is to be written into the selected
memory location or I/O device.
IO/M (output) - Select memory or an IO device.
This status signal indicates that the read / write operation relates to whether the
memory or I/O device. It goes high to indicate an I/O operation. It goes low for memory
operations.
Status Signals:
It is used to know the type of current operation of the microprocessor.
v) Interrupts and externally initiated operations:

They are the signals initiated by an external device to request the microprocessor
to do a particular task or work.
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On receipt of an interrupt, the microprocessor acknowledges the interrupt by the

active low INTA (Interrupt Acknowledge) signal.
Reset In (input, active low): This signal is used to reset the microprocessor. The
program counter inside the microprocessor is set to zero.
Reset Out (Output): It indicates CPU is being reset. Used to reset all the
connected devices when the microprocessor is reset.
vi) Direct Memory Access (DMA):

Tri state devices:
3 output states are high & low states and additionally a high impedance state.
When enable E is high the gate is enabled and the output Q can be 1 or 0 (if A is
0, Q is 1, otherwise Q is 0).
However, when E is low the gate is disabled and the output Q enters into a high
impedance state.
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When E is low, Q enters a high impedance state; high impedance means it is

electrically isolated from the OR gate's input, though it is physically connected.
Therefore, it does not draw any current from the OR gate's input.
When 2 or more devices are connected to a common bus, to prevent the devices
from interfering with each other, the tristate gates are used to disconnect all
devices except the one that is communicating at a given instant.
The CPU controls the data transfer operation between memory and I/O device.
Direct Memory Access operation is used for large volume data transfer between
memory and an I/O device directly.
The CPU is disabled by tri-stating its buses and the transfer is effected directly by
external control circuits.
HOLD signal is generated by the DMA controller circuit. On receipt of this
signal, the microprocessor acknowledges the request by sending out HLDA signal
and leaves out the control of the buses. After the HLDA signal the DMA
controller starts the direct transfer of data.
READY (input)
Memory and I/O devices will have slower response compared to microprocessors.
Before completing the present job such a slow peripheral may not be able to
handle further data or control signal from CPU.
The processor sets the READY signal after completing the present job to access
the data.
The microprocessor enters into WAIT state while the READY pin is disabled.
Single Bit Serial I/O port:
SID (input)
- Serial input data line
SOD (output)
- Serial output data line
These signals are used for serial communication.
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1.2) ARCHITECTURE OF 8086 MICROPROCESSOR:
It is a 16-bit p.
8086 has a 20 bit address bus can access up to 220 memory locations (1 MB).
It can support up to 64K I/O ports.
It provides 14, 16 -bit registers.
It has multiplexed address and data bus AD0- AD15 and A16 A19.
It requires single phase clock with 33% duty cycle to provide internal timing.
8086 is designed to operate in two modes, Minimum and Maximum.
It can prefetches upto 6 instruction bytes from memory and queues them in order
to speed up instruction execution.
It requires +5V power supply.
A 40 pin dual in line package.
8086 has two blocks BIU and EU.
The BIU performs all bus operations such as instruction fetching, reading and
writing operands for memory and calculating the addresses of the memory
operands. The instruction bytes are transferred to the instruction queue.
EU executes instructions from the instruction system byte queue.
Both units operate asynchronously to give the 8086 an overlapping instruction
fetch and execution mechanism which is called as Pipelining. This results in
efficient use of the system bus and system performance.
BIU contains Instruction queue, Segment registers, Instruction pointer, and
Address adder.
EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index
register, Flag register.
BUS INTERFACR UNIT:

It provides a full 16 bit bidirectional data bus and 20 bit address bus.
The bus interface unit is responsible for performing all external bus operations.
Specifically it has the following functions:
Instructions fetch Instruction queuing, Operand fetch and storage, Address
relocation and Bus control.
The BIU uses a mechanism known as an instruction stream queue to implement
pipeline architecture.
This queue permits prefetch of up to six bytes of instruction code. When ever the
queue of the BIU is not full, it has room for at least two more bytes and at the
same time the EU is not requesting it to read or write operands from memory, the
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BIU is free to look ahead in the program by prefetching the next sequential
instruction.
These prefetching instructions are held in its FIFO queue. With its 16 bit data bus,
the BIU fetches two instruction bytes in a single memory cycle.
After a byte is loaded at the input end of the queue, it automatically shifts up
through the FIFO to the empty location nearest the output.
The EU accesses the queue from the output end. It reads one instruction byte after
the other from the output of the queue. If the queue is full and the EU is not requesting
access to operand in memory.
These intervals of no bus activity, which may occur between bus cycles, are
known as idle state.
If the BIU is already in the process of fetching an instruction when the EU request
it to read or write operands from memory or I/O, the BIU first completes the
instruction fetch bus cycle before initiating the operand read / write cycle.
The BIU also contains a dedicated adder which is used to generate the 20bit
physical address that is output on the address bus. This address is formed med by
combining the current contents of the code segment CS register and the current
contents of the instruction pointer IP register.
The BIU is also responsible for generating bus control signals such as those for
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memory read or write and I/O read or write.
EXECUTION UNIT
The Execution unit is responsible for decoding and executing all instructions.
The EU extracts instructions from the top of the queue in the BIU, decodes them,
generates operands if necessary, passes them to the BIU and requests it to perform
the read or write bys cycles to memory or I/O and perform the operation specified
by the instruction on the operands.
During the execution of the instruction, the EU tests the status and control flags
and updates them based on the results of executing the instruction.
If the queue is empty, the EU waits for the next instruction byte to be fetched and
shifted to top of the queue.
When the EU executes a branch or jump instruction, it transfers control to a
location corresponding to another set of sequential instructions.
Whenever this happens, the BIU automatically resets the queue and then begins to
fetch instructions from this new location.
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1.3) Special functions of General purpose registers:

Accumulator:
Accumulator register consists of 2 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX.
AL in this case contains the low-order byte of the word, and AH contains the
high-order byte.
Accumulator can be used for I/O operations and string manipulation.
Base register:
Base register consists of 2 8-bit registers BL and BH, which can be combined
together and used as a 16-bit register BX.
BL in this case contains the low-order byte of the word, and BH contains the
high-order byte.
BX register usually contains a data pointer used for based, based indexed or
register indirect addressing.
Count register:
Count register consists of 2 8-bit registers CL and CH, which can be combined
together and used as a 16-bit register CX.
When combined, CL register contains the low-order byte of the word, and CH
contains the high-order byte.
Count register can be used as a counter in string manipulation and shift/rotate
instructions.
Data register:
Data register consists of 2 8-bit registers DL and DH, which can be combined
together and used as a 16-bit register DX.
When combined, DL register contains the low-order byte of the word, and DH
contains the high-order byte.
Data register can be used as a port number in I/O operations.
In integer 32-bit multiply and divide instruction the DX register contains highorder word of the initial or resulting number.
SPECIAL FUNCTIONS OF SPECIAL PURPOSE REGISTERS
Stack Pointer (SP) is a 16-bit register pointing to program stack.
Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP
register is usually used for based, based indexed or register indirect addressing.
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Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and
register indirect addressing, as well as a source data address in string
manipulation instructions.
Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed
and register indirect addressing, as well as a destination data address in string
manipulation instructions.
The si and di registers (Source Index and Destination Index) have some special
purposes as well. You may use these registers as pointers (much like the bx
register) to indirectly access memory. You'll also use these registers with the 8086
string instructions when processing character strings.
The bp register (Base Pointer) is similar to the bx register. You'll generally use
this register to access parameters and local variables in a procedure.
The sp register (Stack Pointer) has a very special purpose - it maintains the
program stack. Normally, you would not use this register for arithmetic
computations. The proper operation of most programs depends upon the careful
use of this register.
SEGMENTATION:
Since address registers and address operands are only 16 bits they can only
address 64k bytes.
In order to address the 20-bit address range of the 8086, physical addresses (those
that are put on the address bus) are always formed by adding the values of one of
the instruction are executed? The use of segment registers reduces the size of
pointers to 16 bits.
This reduces the code size but also restricts the addressing range of a pointer to
64k bytes. Performing address arithmetic within data structures larger than 64k is
awkward. This is the biggest drawback of the 8086 architecture. We will restrict
ourselves to short programs where all of the code, data and stack are placed into
the same 64k segment (i.e. CS=DS=SS).
Most of the registers contain data/instruction offsets within 64 KB memory
segment.
There are four different 64 KB segments for instructions, stack, data and extra
data.
To specify where in 1 MB of processor memory these 4 segments are located the
processor uses four segment registers:
Memory:
Program, data and stack memories occupy the same memory space. As the most
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of the processor instructions use 16-bit pointers the processor can effectively
address only 64 KB of memory.
To access memory outside of 64 KB the CPU uses special segment registers to
specify where the code, stack and data 64 KB segments are positioned within 1
MB of memory (see the "Registers" section below).
16-bit pointers and data are stored as:
Address: low-order byte
Address+1: high-order byte
Program memory:
Program can be located anywhere in memory. Jump and call instructions can be
used for short jumps within currently selected 64 KB code segment, as well as for
far jumps anywhere within 1 MB of memory.
All conditional jump instructions can be used to jump within approximately +127
to - 127 bytes from current instruction.
Data memory:
The processor can access data in any one out of 4 available segments, which
limits the size of accessible memory to 256 KB (if all four segments point to
different 64 KB blocks).
Accessing data from the Data, Code, Stack or Extra segments can be usually done
by prefixing instructions with the DS:, CS:, SS: or ES: (some registers and
instructions by default may use the ES or SS segments instead of DS segment).
Word data can be located at odd or even byte boundaries. The processor uses two
memory accesses to read 16-bit word located at odd byte boundaries. Reading
word data from even byte boundaries requires only one memory access.
Stack memory:
It can be placed anywhere in memory. The stack can be located at odd memory
addresses, but it is not recommended for performance reasons (see "Data
Memory" above).
Reserved locations:
0000h - 03FFh are reserved for interrupt vectors. Each interrupt vector is a 32-bit
pointer in format segment: offset.
FFFF0h - FFFFFh - after RESET the processor always starts program execution at
the FFF0h address.
The segment registers themselves only contain the most-significant 16 bits of the
20-bit value that is contributed by the segment registers. The least significant four
bits of the segment address are always zero.
By default, the DS (data segment) is used for data transfer instructions (e.g.
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MOV), CS (code segment) is used with control transfer instructions (e.g. JMP or
CALL), and SS is used with the stack pointer (e.g. PUSH or to save/restore
addresses during CALL/RET or INT instructions).
Code segment:
CS is a 16-bit register containing address of 64 KB segment with processor
instructions.
The processor uses CS segment for all accesses to instructions referenced by
instruction pointer (IP) register. CS register cannot be changed directly. The CS
register is automatically updated during far jump, far call and far return
instructions.
Stack segment:
SS is a 16-bit register containing address of 64KB segment with program stack.
By default, the processor assumes that all data referenced by the stack pointer
(SP) and base pointer (BP) registers is located in the stack segment.
SS register can be changed directly using POP instruction.
Data segment
DS is a 16-bit register containing address of 64KB segment with program data.
By default, the processor assumes that all data referenced by general registers
(AX, BX, CX, and DX) and index register (SI, DI) is located in the data segment.
DS register can be changed directly using POP and LDS instructions.
Extra segment:
ES is a 16-bit register containing address of 64KB segment, usually with program
data. By default, the processor assumes that the DI register references the ES
segment in string manipulation instructions.
ES register can be changed directly using POP and LES instructions.
It is possible to change default segments used by general and index registers by
prefixing instructions with a CS, SS, DS or ES prefix.
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1.4) 8086 flag register and function of 8086 Flags:
8086 has 16-bit register containing 9 1-bit flags:

Overflow Flag (OF) - set if the result is too large positive number, or is too small
negative number to fit into destination operand.
Direction Flag (DF) - if set then string manipulation instructions will auto-decrement
index registers. If cleared then the index registers will be auto-incremented.
Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.
Single-step Flag (TF) - if set then single-step interrupt will occur after the next
instruction.
Sign Flag (SF) - set if the most significant bit of the result is set.
Zero Flag (ZF) - set if the result is zero.
Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the AL
register.
Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the result
is even.
Carry Flag (CF) - set if there was a carry from or borrow to the most significant during
last result calculation.
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1.5) ADDRESSING MODES OF 8086:
Addressing mode tells where and how to locate data to be accessed.

In essence, they are different ways used to specify the operands.
There are 7 addressing modes divided into 3 categories in 8086 :
i. Register operand addressing-Register addressing mode
ii.Immediate operand addressing-Immediate addressing mode
iii.Memory operand addressing
Direct addressing mode
Register indirect addressing mode
Based addressing mode
Indexed addressing mode
Based-indexed addressing mode
1.5.1) Register Operand Addressing:

With the register addressing mode, the operand to be accessed is inside an

internal register of the 8088/8086
Internal registers that can be used as source / destination:
Operand sizes
Register
Byte (Reg 8)
Word
16)
Accumulator
Base
AL, AH
BL, BH
AX
BX
Count
Data
CL, CH
DL, DH
CX
DX
Stack pointer
Base pointer
SP
BP
Source index
SI
Destination
index
DI
Code segment
Data segment
CS
DS
Stack segment
Extra segment
SS
ES
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An example of instruction using this addressing mode is
MOV AX, BX
This stands for move the contents of BX (source operand) to AX (destination
operand)
E.g. what is the destination operand in the following instruction? How large is this
operand?
MOV CH, AH
The destination operand is register CH and it specifies an 8-bit operand.
1.5.2) Immediate Operand Addressing:

If an operand is part of an instruction instead of the contents of a register or
memory location, it is called an immediate operand
This operand is accessed using the immediate addressing mode
The operand can either be an 8-bit or 16-bit data
Immediate operands normally represent constant data
This addressing mode can only be used to specify a source operand
Consider the instruction: MOV AL, 15H
In this instruction, the source operand is 15H, while the destination operand is
register AL
Thus these instructions use both the immediate and register addressing modes.
E.g. Write an instruction that will move the immediate value 1234H into the CX
register
Solution:
The instruction must use immediate addressing mode for the source operand and
register addressing mode for the destination operand, i.e.
MOV CX, 1234H
1.5.3) Memory Operand Addressing:

In this categories, the operands are inside the memory

To access an operand in memory, 8086 must calculate the physical address (PA)
of the memory location before it can read or write the operand
The physical address is computed from a segment based address (SBA) and an
effective address (EA)
SBA identifies the starting location of the segment in memory, and EA represents
the offset of the operand from the beginning of this segment of memory
The value of EA can be specified in a variety of ways
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EA can be made up from as many as 3 elements: base, index and displacement

PA = SBA:EA
PA = Segment base: Base + Index + Displacement
PA =

CS
SS
DS
ES
BX
BP
SI
DI
8-bit displacement
16-bit displacement
Not all elements are always used in the effective address calculation
In fact, three addressing modes are defined by using various combination of these
elements:
i.
Register indirect addressing mode
ii.
Based addressing mode
iii.
Indexed addressing mode
iv.
Based-indexed addressing mode
For e.g. in based addressing mode, the EA calculation only includes the base
Direct Addressing Mode:

In this addressing mode, the effective address (EA) of the operand is specify
directly in the instruction
The effective address is used directly as the 16-bit offset of the memory location
of the operand from the segment base address specified by the selected segment
register.
PA = Segment base: Direct address
PA =

CS
SS
DS
ES
Direct address
The default segment register is DS

Thus the 20-bit physical address of the operand in memory is normally given by
DS:EA
However, by using a segment over-ride prefix, any of the four segment registers
can be used.
Consider the instruction: MOV CX, [1234H]
This stands for move the contents of the memory location with offset 1234H in
the current data segment into register CX
24
MPI

Address
Memory
content
01000
01001
01002
01003
01004
8B
0E
34
12
XX
8088/8086 MPU
0000
IP
0100
0200
CS
DS
SS
ES
XXXX
AX
BX
CX
DX
BP
SI
DI
MOV CX, [1234H]
Next instruction
.
.
.
PA = 02000H + 1234H
= 03234H
SP
Instruction
02000
02000
.
XX
XX
.
.
03234
03235
ED
BE
Source operand
After calculating the physical address of the operand, the 8086 reads the word of
data starting at that address (which is BEEDH) and loads it into the CS register.
Address
Memory
content
Instruction
01000
8B
MOV CX, [1234H]
01001
01002
0E
34
8088/8086 MPU
0004
IP
0100
0200
CS
DS
SS
01003
12
01004
XX
Next instruction
ES
.
AX
BX
BEED
CX
DX
.
.
02000
XX
02001
XX
SP
BP
SI
.
03234
ED
03235
BE
DI
25
Source operand
MPI

Register Indirect Addressing Mode:
In this addressing mode, the effective address is specified either in a base register
(BX or BP) or index register (SI or DI)
This effective address will be combined with a segment base address in a segment
register (default is DS register) to form a physical address
8 0 8 8 /8 0 8 6 M P U
0002
0100
0200
IP
CS
DS
A d d re ss
M e m o ry
co n te n t
In stru ctio n
01000
8B
M O V A X , [S I]
01001
04
01002
XX
N e x t in stru ctio n
SS
.
ES
.
BEED
AX
BX
CX
DX
02000
XX
02001
XX
1234
SP
BP
SI
DI
8088/8086 MPU
0000
0100
0200
IP
CS
DS
03234
ED
03235
BE
Address
Memory
content
Instruction
01000
8B
MOV AX, [SI]
01001
01002
04
XX
Next instruction
SS
ES
XXXX
AX
BX
.
PA = 02000H + 1234H
= 03234H
CX
DX
1234
S o u rc e o p e ra n d
SP
BP
SI
DI
.
.
02000
02001
XX
XX
.
.
.
03234
03235
26
ED
BE
Source operand
MPI

Consider the instruction: MOV AX, [SI]
This instruction will move the contents of the memory location at the physical
address given by the combination of the current data segment and the effective
address in register SI into AX register.
The result of executing this instruction and the instruction using direct address
mode are the same.
Using direct addressing, the EA is fixed; using register indirect addressing, the EA
can be changed.

Based Addressing Mode:

In this addressing mode, the effective address is obtained by adding a direct or
indirect displacement to the contents of either BX or BP register.
Segment base
PA =
CS
SS
DS
ES
Effective address
BX
BP
8-bit displacement
16-bit displacement
Base register
Element 0
Element 1
Element 2
.
.
.
Displacement
Array of
data
Element n-2
Element n-1

The value in the base register defines the beginning of a data structure (e.g. array)
in memory, and the displacement selects an element of data within the structure
To access a different element in the array, the programmer simply changes the
value of the displacement
To access the same element in another similar array, the programmer can change
the value in the base register so that it points to the beginning of the new array
Consider the instruction: MOV [BX]+1234H, AL
This instruction uses base register BX and direct displacement 1234H to derive
the destination operand.
27
MPI

The based addressing mode is implemented by specifying the base register in

brackets followed by a + sign and direct displacement
Address
Memory
content
Instruction
IP
01000
88
MOV [BX]+1234H, AL
CS
DS
01001
01002
01003
87
34
12
SS
ES
01004
.
XX
8088/8086 MPU
0000
0100
0200
BE
ED
1000
Next instruction
.
.
AX
BX
02000
02001
CX
DX
XX
XX
SP
BP
SI
PA = 02000H + 1000H + 1234H

.
= 04234H
.
04234
04235
DI
XX
XX
Destination operand
Address
Memory
content
Instruction
IP
01000
88
MOV [BX]+1234H, AL
CS
DS
01001
01002
01003
87
34
12
SS
ES
01004
.
XX
8088/8086 MPU
0004
0100
0200
BE
ED
1000
AX
BX
CX
DX
SP
BP
SI
DI
Next instruction
.
.
02000
02001
XX
XX
.
.
.
04234
04235
28
ED
XX
Destination operand
MPI
The microprocessor calculates the physical address of the destination operand

from the contents of DS, BX and the direct displacement, and then moves the
contents of AL into memory location at 04234H.
The default segment register for physical address calculation is DS register, but it
can be changed to other segment register with the segment-override prefix
If BP is used instead of BX, the calculation of the physical address is performed
using the contents of the stack segment (SS) register instead of DS register.
Indexed Addressing Mode:
Indexed addressing mode uses the value of the displacement as a pointer to the
starting point of an array of data in memory and the contents of the specified register
as an index that selects the specific element in the array to be accessed
Segment base
PA =
CS
SS
DS
ES
Effective address
SI
DI
Displacement
Element 0
Element 1
Element 2
8-bit displacement
16-bit displacement
Index register
.
.
.
Array of
data
Element n-2
Element n-1
8088/8086 MPU
Address
Memory
content
01000
01001
8A
84
0000
IP
0100
CS
01002
34
0200
DS
01003
12
SS
01004
XX
ES
XX
XX
CX
DX
BP
Next instruction
BX
2000
MOV AL, [SI]+1234H
.
.
AX
SP
Instruction
02000
XX
02001
XX
.
PA = 02000H + 2000H + 1234H
.
= 05234H
.
SI
DI
05234
BE
05235
XX
29
Source operand
MPI

The physical address of the source operand is first calculated from the contents of
DS, SI and the direct displacement
The data byte stored at 05234H is then moved to AL
8 08 8 /8 08 6 M PU
A d d ress
M e m ory
con ten t
Instru ction
M O V A L , [S I]+ 123 4 H
000 4
IP
01 00 0
8A
010 0
CS
01 00 1
01 00 2
84
34
020 0
DS
01 00 3
12
SS
ES
01 00 4
.
XX
AX
.
.
XX
BE
BX
CX
DX
02 00 0
XX
02 00 1
XX
.
.
SP
BP
200 0
N e xt in stru ction
SI
DI
.
05 23 4
BE
05 23 5
XX
S ou rce op e ra nd
Based-Indexed Addressing Mode:

This addressing mode is a combination of the based addressing mode and the
indexed addressing mode
The effective address is formed by three elements: base register, index register
and a displacement
Segment base
CS
SS
PA =
DS
ES

Effective address
BX
BP
SI
DI
8-bit displacement
16-bit displacement
It can be used to accessed complex data structures such as two-dimensional arrays

In this case, the displacement locates the starting point of the array in memory, the
base register specifies the x-coordinate of the array, and the index register
specifies the y-coordinate.
30
MPI

12
13
14
14
10
11
2D array
of data
Index register
+
Displacement

Changing the values in the base and index registers permits access to other
elements in the array
Consider the instruction: MOV AH, [BX][SI]+1234H
Before the source operand can be moved to the destination, the 8086 calculates its
physical address
The effective address is formed by BX and SI registers with 16-bit displacement
The physical address is then computed from the current contents of DS register
and the effective address.
8088/8086 MPU
Address
Memory
content
Instruction
MOV AH, [BX][SI]+1234H
0000
IP
01000
8A
0100
0200
CS
DS
01001
01002
01003
A0
34
12
SS
ES
01004
.
XX
XX
XX
1000
2000
SP
BP
SI
Next instruction
.
.
AX
BX
02000
02001
CX
DX
XX
XX
EA = 1000H + 2000H +1234H

PA = 02000H + EA
= 06234H
DI
Base register
.
.
.
06234
06235
BE
XX
Source operand
Execution of the instruction moves the value stored at the physical address into AH
31
MPI

8088/8086 MPU
Address
Memory
content
Instruction
MOV AH, [BX][SI]+1234H
0004
IP
01000
8A
0100
0200
CS
DS
01001
01002
01003
A0
34
12
SS
ES
01004
.
XX
BE
XX
1000
AX
BX
CX
DX
2000
SP
BP
SI
DI
Next instruction
.
.
02000
02001
XX
XX
.
.
.
06234
06235
32
BE
XX
Source operand
MPI
1.6) Instruction set of 8086:

Quick reference:
AAA
AAD
AAM
AAS
ADC
ADD
AND
CALL
CBW
CLC
CLD
CLI
CMC
CMP
CMPSB
CMPSW
CWD
DAA
DAS
DEC
DIV
HLT
IDIV
IMUL
IN
INC
INT
INTO
IRET
JA
JAE JNBE
JB
JNC
JBE
JNE
JC
JNG
JCXZ JNGE
JE
JNL
JG
JNLE
JGE
JNO
JL
JNP
JLE
JNS
JMP
JNZ
JNA
JO
JNAE
JP
JNB
JPE
JPO
JS
JZ
LAHF
LDS
LEA
LES
LODSB
LODSW
LOOP
LOOPE
LOOPNE
LOOPNZ
LOOPZ
MOV
MOVSB
MOVSW
MUL
NEG
NOP
NOT
OR
OUT
POP
POPA
POPF
PUSH
PUSHA
PUSHF
RCL
RCR
REP
REPE
REPNE
REPNZ
REPZ
RET
RETF
ROL
ROR
SAHF
SAL
SAR
SBB
SCASB
SCASW
SHL
SHR
STC
STD
STI
STOSB
STOSW
SUB
TEST
XCHG
XLATB
XOR
Operand types:
REG: AX, BX, CX, DX, AH, AL, BL, BH, CH, CL, DH, DL, DI, SI, BP, SP.
SREG: DS, ES, SS, and only as second operand: CS.
Memory: [BX], [BX+SI+7], variable, etc...(See Memory Access).
Immediate: 5, -24, 3Fh, 10001101b, etc...
Notes:
When two operands are required for an instruction they are separated by comma.
For example:
REG, memory
When there are two operands, both operands must have the same size (except shift
and rotate instructions). For example:
AL, DL
DX, AX
m1 DB ?
AL, m1
33
MPI

m2 DW?
AX, m2
Some instructions allow several operand combinations. For example:

memory, immediate
REG, immediate
memory, REG
REG, SREG
Some examples contain macros, so it is advisable to use Shift + F8 hot key to Step
Over (to make macro code execute at maximum speed set step delay to zero),
otherwise emulator will step through each instruction of a macro. Here is an
example that uses PRINTN macro:
include 'emu8086.inc'
ORG 100h
MOV AL, 1
MOV BL, 2
PRINTN 'Hello World!' ; macro.
MOV CL, 3
PRINTN 'Welcome!'
; macro.
RET
These marks are used to show the state of the flags:

1 - instruction sets this flag to 1.
0 - instruction sets this flag to 0.
r - flag value depends on result of the instruction.
? - flag value is undefined (maybe 1 or 0).
Some instructions generate exactly the same machine code, so disassembler may have a
problem decoding to your original code. This is especially important for Conditional
Jump instructions (see "Program Flow Control" in Tutorials for more information).
Instructions in alphabetical order:

Instruction
AAA
Operands
No
operands
Description
ASCII Adjust after Addition.
Corrects result in AH and AL after addition when working
with BCD values.
It works according to the following Algorithm:
34
MPI

if low nibble of AL > 9 or AF = 1 then:
AL = AL + 6
AH = AH + 1
AF = 1
CF = 1
else
AF = 0
CF = 0
in both cases:
clear the high nibble of AL.
Example:
MOV AX, 15 ; AH = 00, AL = 0Fh
AAA
; AH = 01, AL = 05
RET
CZSOPA
r ? ? ? ? r
ASCII Adjust before Division.

Prepares two BCD values for division.
Algorithm:
AAD
AAM
No
operands
No
operands
AL = (AH * 10) + AL
AH = 0
Example:
MOV AX, 0105h ; AH = 01, AL = 05
AAD
; AH = 00, AL = 0Fh (15)
RET
CZSOPA
? r r ? r ?
ASCII Adjust after Multiplication.

Corrects the result of multiplication of two BCD values.
35
MPI

Algorithm:
AH = AL / 10
AL = remainder
Example:
MOV AL, 15 ; AL = 0Fh
AAM
; AH = 01, AL = 05
RET
CZSOPA
? r r ? r ?
ASCII Adjust after Subtraction.

Corrects result in AH and AL after subtraction when
working with BCD values.
Algorithm:
AAS
No
operands
AL = AL - 6
AH = AH - 1
AF = 1
CF = 1
else
AF = 0
CF = 0
in both cases:
clear the high nibble of AL.
Example:
MOV AX, 02FFh ; AH = 02, AL = 0FFh
AAS
; AH = 01, AL = 09
RET
CZSOPA
r ? ? ? ? r
36
MPI

Add with Carry.
ADC
REG,
memory
memory,
REG
REG, REG
memory,
immediate
REG,
immediate
Algorithm:
operand1 = operand1 + operand2 + CF
Example:
STC
; set CF = 1
MOV AL, 5 ; AL = 5
ADC AL, 1 ; AL = 7
RET
CZSOPA
r r r r r r
Add.
ADD
AND
REG,
memory
memory,
REG
REG, REG
memory,
immediate
REG,
immediate
REG,
memory
memory,
REG
REG, REG
memory,
immediate
REG,
immediate
Algorithm:
operand1 = operand1 + operand2
Example:
MOV AL, 5 ; AL = 5
ADD AL, -3 ; AL = 2
RET
CZSOPA
r r r r r r
Logical AND between all bits of two operands. Result is

stored in operand1.
These rules apply:
1 AND 1 = 1
1 AND 0 = 0
0 AND 1 = 0
0 AND 0 = 0
Example:
37
MPI

MOV AL, 'a'
; AL = 01100001b
AND AL, 11011111b ; AL = 01000001b ('A')
RET
CZSOP
0 r r 0 r
Transfers control to procedure, return address is (IP) is

pushed to stack. 4-byte address may be entered in this
form: 1234h:5678h, first value is a segment second value is
an offset (this is a far call, so CS is also pushed to stack).
Example:
ORG 100h ; directive to make simple .com file.
CALL
procedure
name
label
4-byte
address
CALL p1
ADD AX, 1
RET
; return to OS.
p1 PROC ; procedure declaration.

MOV AX, 1234h
RET ; return to caller.
p1 ENDP
CZSOPA
unchanged
Convert byte into word.

Algorithm:
CBW
No
operands
if high bit of AL = 1 then:
AH = 255 (0FFh)
else
38
MPI
AH = 0
Example:
MOV AX, 0 ; AH = 0, AL = 0
MOV AL, -5 ; AX = 000FBh (251)
CBW
; AX = 0FFFBh (-5)
RET
CZSOPA
unchanged
Clear Carry flag.

Algorithm:
CLC
No
operands
CF = 0
C
0
Clear Direction flag. SI and DI will be incremented by

chain instructions: CMPSB, CMPSW, LODSB, LODSW,
MOVSB, MOVSW, STOSB, STOSW.
Algorithm:
CLD
No
operands
DF = 0
D
0
Clear Interrupt enable flag. This disables hardware

interrupts.
CLI
No
operands
Algorithm:
IF = 0
39
MPI
I
0
Complement Carry flag. Inverts value of CF.

Algorithm:
CMC
No
operands
if CF = 1 then CF = 0
if CF = 0 then CF = 1
C
r
Compare.
Algorithm:
CMP
REG,
memory
memory,
REG
REG, REG
memory,
immediate
REG,
immediate
operand1 - operand2
result is not stored anywhere, flags are set (OF, SF, ZF,
AF, PF, CF) according to result.
Example:
MOV AL, 5
MOV BL, 5
CMP AL, BL ; AL = 5, ZF = 1 (so equal!)
RET
CZSOPA
r r r r r r
Compare bytes: ES:[DI] from DS:[SI].

Algorithm:
CMPSB
No
operands
DS:[SI] - ES:[DI]
set flags according to result:
OF, SF, ZF, AF, PF, CF
if DF = 0 then
40
MPI

SI = SI + 1
DI = DI + 1
o
o
else
SI = SI - 1
DI = DI - 1
o
o
Example:
see cmpsb.asm in c:\emu8086\examples\.
CZSOPA
r r r r r r
Compare words: ES:[DI] from DS:[SI].

Algorithm:
CMPSW
No
operands
DS:[SI] - ES:[DI]
if DF = 0 then
o SI = SI + 2
o DI = DI + 2
else
SI = SI - 2
DI = DI - 2
o
o
Example:
see cmpsw.asm in c:\emu8086\examples\.
CZSOPA
r r r r r r
Convert Word to Double word.

CWD
No
operands
Algorithm:
if high bit of AX = 1 then:
41
MPI
DX = 65535 (0FFFFh)
else
DX = 0
Example:
MOV DX, 0 ; DX = 0
MOV AX, 0 ; AX = 0
MOV AX, -5 ; DX AX = 00000h:0FFFBh
CWD
; DX AX = 0FFFFh:0FFFBh
RET
CZSOPA
unchanged
Decimal adjust After Addition.

Corrects the result of addition of two packed BCD values.
Algorithm:
AL = AL + 6
AF = 1
if AL > 9Fh or CF = 1 then:

DAA
No
operands
AL = AL + 60h
CF = 1
Example:
MOV AL, 0Fh ; AL = 0Fh (15)
DAA
; AL = 15h
RET
CZSOPA
r r r r r r
42
MPI

Decimal adjust After Subtraction.
Corrects the result of subtraction of two packed BCD
values.
Algorithm:
DAS
No
operands
AL = AL - 6
AF = 1
if AL > 9Fh or CF = 1 then:
AL = AL - 60h
CF = 1
Example:
MOV AL, 0FFh ; AL = 0FFh (-1)
DAS
; AL = 99h, CF = 1
RET
CZSOPA
r r r r r r
Decrement.
Algorithm:
operand = operand - 1
DEC
REG
memory
DIV
REG
memory
Example:
MOV AL, 255 ; AL = 0FFh (255 or -1)
DEC AL
; AL = 0FEh (254 or -2)
RET
ZSOPA
r r r r r
CF - unchanged!
Unsigned divide.
43
MPI

Algorithm:
when operand is a byte:
AL = AX / operand
AH = remainder (modulus)
when operand is a word:
AX = (DX AX) / operand
DX = remainder (modulus)
Example:
MOV AX, 203 ; AX = 00CBh
MOV BL, 4
DIV BL
; AL = 50 (32h), AH = 3
RET
CZSOPA
? ? ? ? ? ?
Halt the System.
HLT
No
operands
Example:
MOV AX, 5
HLT
CZSOPA
unchanged
Signed divide.
Algorithm:
IDIV
REG
memory

AL = AX / operand
AH = remainder (modulus)
AX = (DX AX) / operand
DX = remainder (modulus)
Example:
MOV AX, -203 ; AX = 0FF35h
MOV BL, 4
IDIV BL ; AL = -50 (0CEh), AH = -3 (0FDh)
RET
CZSOPA
? ? ? ? ? ?
44
MPI
Signed multiply.
Algorithm:
IMUL
IN
REG
memory
AL,
im.byte
AL, DX
AX,
im.byte
AX, DX

AX = AL * operand.
(DX AX) = AX * operand.
Example:
MOV AL, -2
MOV BL, -4
IMUL BL ; AX = 8
RET
CZSOPA
r ? ? r ? ?
CF=OF=0 when result fits into operand of IMUL.
Input from port into AL or AX.
Second operand is a port number. If required to access port
number over 255 - DX register should be used.
Example:
IN AX, 4 ; get status of traffic lights.
IN AL, 7 ; get status of stepper-motor.
CZSOPA
unchanged
Increment.
Algorithm:
operand = operand + 1
INC
REG
memory
Example:
MOV AL, 4
INC AL
; AL = 5
RET
ZSOPA
r r r r r
CF - unchanged!
45
MPI

Interrupt numbered by immediate byte (0..255).
Algorithm:
Push to stack:
o
o
o
INT
immediate
byte
flags register
CS
IP
IF = 0
Transfer control to interrupt procedure
Example:
MOV AH, 0Eh ; teletype.
MOV AL, 'A'
INT 10h
; BIOS interrupt.
RET
CZSOPAI
unchanged
0
Interrupt 4 if Overflow flag is 1.

Algorithm:
if OF = 1 then INT 4
INTO
No
operands
Example:
; -5 - 127 = -132 (not in -128..127)
; the result of SUB is wrong (124),
; so OF = 1 is set:
MOV AL, -5
SUB AL, 127 ; AL = 7Ch (124)
INTO
; process error.
RET
Interrupt Return.
IRET
No
operands
Algorithm:
Pop from stack:
46
MPI
IP
CS
flags register
o
o
o
CZSOPA
popped
Short Jump if first operand is Above second operand (as set

by CMP instruction). Unsigned.
Algorithm:
if (CF = 0) and (ZF = 0) then jump
Example:
JA
label
ORG 100h
MOV AL, 250
CMP AL, 5
JA label1
PRINT 'AL is not above 5'
JMP exit
label1:
PRINT 'AL is above 5'
exit:
RET
CZSOPA
unchanged
Short Jump if first operand is Above or Equal to second

operand (as set by CMP instruction). Unsigned.
Algorithm:
JAE
label
if CF = 0 then jump
Example:
ORG 100h
MOV AL, 5
47
MPI

CMP AL, 5
JAE label1
PRINT 'AL is not above or equal to 5'
JMP exit
label1:
PRINT 'AL is above or equal to 5'
exit:
RET
CZSOPA
unchanged
Short Jump if first operand is Below second operand (as set

by CMP instruction). Unsigned.
Algorithm:
if CF = 1 then jump
Example:
JB
label
ORG 100h
MOV AL, 1
CMP AL, 5
JB label1
PRINT 'AL is not below 5'
JMP exit
label1:
PRINT 'AL is below 5'
exit:
RET
CZSOPA
unchanged
Short Jump if first operand is Below or Equal to second

operand (as set by CMP instruction). Unsigned.
JBE
label
Algorithm:
if CF = 1 or ZF = 1 then jump
Example:
48
MPI
ORG 100h
MOV AL, 5
CMP AL, 5
JBE label1
PRINT 'AL is not below or equal to 5'
JMP exit
label1:
PRINT 'AL is below or equal to 5'
exit:
RET
CZSOPA
unchanged
Short Jump if Carry flag is set to 1.

Algorithm:
if CF = 1 then jump
Example:
JC
label
ORG 100h
MOV AL, 255
ADD AL, 1
JC label1
PRINT 'no carry.'
JMP exit
label1:
PRINT 'has carry.'
exit:
RET
CZSOPA
unchanged
Short Jump if CX register is 0.

JCXZ
label
Algorithm:
if CX = 0 then jump
Example:
49
MPI

ORG 100h
MOV CX, 0
JCXZ label1
PRINT 'CX is not zero.'
JMP exit
label1:
PRINT 'CX is zero.'
exit:
RET
CZSOPA
unchanged
Short Jump if first operand is Equal to second operand (as

set by CMP instruction). Signed/Unsigned.
Algorithm:
if ZF = 1 then jump
Example:
JE
label
ORG 100h
MOV AL, 5
CMP AL, 5
JE label1
PRINT 'AL is not equal to 5.'
JMP exit
label1:
PRINT 'AL is equal to 5.'
exit:
RET
CZSOPA
unchanged
Short Jump if first operand is Greater then second operand

(as set by CMP instruction). Signed.
JG
label
Algorithm:
50
MPI

if (ZF = 0) and (SF = OF) then jump
Example:
ORG 100h
MOV AL, 5
CMP AL, -5
JG label1
PRINT 'AL is not greater -5.'
JMP exit
label1:
PRINT 'AL is greater -5.'
exit:
RET
CZSOPA
unchanged
Short Jump if first operand is Greater or Equal to second

operand (as set by CMP instruction). Signed.
Algorithm:
if SF = OF then jump
Example:
JGE
label
ORG 100h
MOV AL, 2
CMP AL, -5
JGE label1
PRINT 'AL < -5'
JMP exit
label1:
PRINT 'AL >= -5'
exit:
RET
CZSOPA
unchanged
JL
label
Short Jump if first operand is Less then second operand (as

set by CMP instruction). Signed.
51
MPI
Algorithm:
if SF <> OF then jump
Example:
ORG 100h
MOV AL, -2
CMP AL, 5
JL label1
PRINT 'AL >= 5.'
JMP exit
label1:
PRINT 'AL < 5.'
exit:
RET
CZSOPA
unchanged
Short Jump if first operand is Less or Equal to second

Algorithm:
if SF <> OF or ZF = 1 then jump
Example:
JLE
label
ORG 100h
MOV AL, -2
CMP AL, 5
JLE label1
PRINT 'AL > 5.'
JMP exit
label1:
PRINT 'AL <= 5.'
exit:
RET
CZSOPA
unchanged
52
MPI

Unconditional Jump. Transfers control to another part of
the program. 4-byte address may be entered in this form:
1234h:5678h, first value is a segment second value is an
offset.
Algorithm:
JMP
label
4-byte
address
always jump
Example:
ORG 100h
MOV AL, 5
JMP label1 ; jump over 2 lines!
PRINT 'Not Jumped!'
MOV AL, 0
label1:
PRINT 'Got Here!'
RET
CZSOPA
unchanged
Short Jump if first operand is Not Above second operand

(as set by CMP instruction). Unsigned.
Algorithm:
if CF = 1 or ZF = 1 then jump
Example:
JNA
label
ORG 100h
MOV AL, 2
CMP AL, 5
JNA label1
PRINT 'AL is above 5.'
JMP exit
label1:
PRINT 'AL is not above 5.'
exit:
RET
CZSOPA
53
MPI

unchanged
Short Jump if first operand is Not Above and Not Equal to

second operand (as set by CMP instruction). Unsigned.
Algorithm:
if CF = 1 then jump
Example:
JNAE
label
ORG 100h
MOV AL, 2
CMP AL, 5
JNAE label1
PRINT 'AL >= 5.'
JMP exit
label1:
PRINT 'AL < 5.'
exit:
RET
CZSOPA
unchanged
Short Jump if first operand is Not Below second operand

(as set by CMP instruction). Unsigned.
Algorithm:
if CF = 0 then jump
Example:
JNB
label
ORG 100h
MOV AL, 7
CMP AL, 5
JNB label1
PRINT 'AL < 5.'
JMP exit
label1:
PRINT 'AL >= 5.'
54
MPI

exit:
RET
CZSOPA
unchanged
Short Jump if first operand is Not Below and Not Equal to

second operand (as set by CMP instruction). Unsigned.
Algorithm:
if (CF = 0) and (ZF = 0) then jump
Example:
JNBE
label
ORG 100h
MOV AL, 7
CMP AL, 5
JNBE label1
PRINT 'AL <= 5.'
JMP exit
label1:
PRINT 'AL > 5.'
exit:
RET
CZSOPA
unchanged
Short Jump if Carry flag is set to 0.

Algorithm:
JNC
label
if CF = 0 then jump
Example:
ORG 100h
MOV AL, 2
ADD AL, 3
JNC label1
PRINT 'has carry.'
JMP exit
55
MPI

label1:
PRINT 'no carry.'
exit:
RET
CZSOPA
unchanged
Short Jump if first operand is Not Equal to second operand

(as set by CMP instruction). Signed/Unsigned.
Algorithm:
if ZF = 0 then jump
Example:
JNE
label
ORG 100h
MOV AL, 2
CMP AL, 3
JNE label1
PRINT 'AL = 3.'
JMP exit
label1:
PRINT 'Al <> 3.'
exit:
RET
CZSOPA
unchanged
Short Jump if first operand is Not Greater then second

Algorithm:
JNG
label
if (ZF = 1) and (SF <> OF) then jump

Example:
ORG 100h
MOV AL, 2
CMP AL, 3
56
MPI

JNG label1
PRINT 'AL > 3.'
JMP exit
label1:
PRINT 'Al <= 3.'
exit:
RET
CZSOPA
unchanged
Short Jump if first operand is Not Greater and Not Equal to

second operand (as set by CMP instruction). Signed.
Algorithm:
if SF <> OF then jump
Example:
JNGE
label
ORG 100h
MOV AL, 2
CMP AL, 3
JNGE label1
PRINT 'AL >= 3.'
JMP exit
label1:
PRINT 'Al < 3.'
exit:
RET
CZSOPA
unchanged
Short Jump if first operand is Not Less then second

Algorithm:
JNL
label
if SF = OF then jump
Example:
57
MPI

ORG 100h
MOV AL, 2
CMP AL, -3
JNL label1
PRINT 'AL < -3.'
JMP exit
label1:
PRINT 'Al >= -3.'
exit:
RET
CZSOPA
unchanged
Short Jump if first operand is Not Less and Not Equal to

second operand (as set by CMP instruction). Signed.
Algorithm:
if (SF = OF) and (ZF = 0) then jump
Example:
JNLE
label
ORG 100h
MOV AL, 2
CMP AL, -3
JNLE label1
PRINT 'AL <= -3.'
JMP exit
label1:
PRINT 'Al > -3.'
exit:
RET
CZSOPA
unchanged
Short Jump if Not Overflow.

JNO
label
Algorithm:
if OF = 0 then jump
Example:
58
MPI

; -5 - 2 = -7 (inside -128..127)
; the result of SUB is correct,
; so OF = 0:
ORG 100h
MOV AL, -5
SUB AL, 2 ; AL = 0F9h (-7)
JNO label1
PRINT 'overflow!'
JMP exit
label1:
PRINT 'no overflow.'
exit:
RET
CZSOPA
unchanged
Short Jump if No Parity (odd). Only 8 low bits of result are

checked. Set by CMP, SUB, ADD, TEST, AND, OR, XOR
instructions.
Algorithm:
if PF = 0 then jump
Example:
JNP
label
ORG 100h
MOV AL, 00000111b ; AL = 7
OR AL, 0
; just set flags.
JNP label1
PRINT 'parity even.'
JMP exit
label1:
PRINT 'parity odd.'
exit:
RET
CZSOPA
unchanged
59
MPI

Short Jump if Not Signed (if positive). Set by CMP, SUB,
ADD, TEST, AND, OR, XOR instructions.
Algorithm:
if SF = 0 then jump
Example:
JNS
label
ORG 100h
MOV AL, 00000111b ; AL = 7
OR AL, 0
; just set flags.
JNS label1
PRINT 'signed.'
JMP exit
label1:
PRINT 'not signed.'
exit:
RET
CZSOPA
unchanged
Short Jump if Not Zero (not equal). Set by CMP, SUB,

Algorithm:
if ZF = 0 then jump
Example:
JNZ
label
ORG 100h
MOV AL, 00000111b ; AL = 7
OR AL, 0
; just set flags.
JNZ label1
PRINT 'zero.'
JMP exit
label1:
PRINT 'not zero.'
exit:
RET
CZSOPA
unchanged
60
MPI
Short Jump if Overflow.

Algorithm:
if OF = 1 then jump
Example:
; -5 - 127 = -132 (not in -128..127)
; the result of SUB is wrong (124),
; so OF = 1 is set:
JO
label
org 100h
MOV AL, -5
SUB AL, 127 ; AL = 7Ch (124)
JO label1
PRINT 'no overflow.'
JMP exit
label1:
PRINT 'overflow!'
exit:
RET
CZSOPA
unchanged
Short Jump if Parity (even). Only 8 low bits of result are

instructions.
Algorithm:
JP
label
if PF = 1 then jump
Example:
ORG 100h
MOV AL, 00000101b ; AL = 5
OR AL, 0
; just set flags.
JP label1
PRINT 'parity odd.'
JMP exit
61
MPI

label1:
exit:
RET
CZSOPA
unchanged
Short Jump if Parity Even. Only 8 low bits of result are

instructions.
Algorithm:
if PF = 1 then jump
Example:
JPE
label
ORG 100h
MOV AL, 00000101b ; AL = 5
OR AL, 0
; just set flags.
JPE label1
PRINT 'parity odd.'
JMP exit
label1:
exit:
RET
CZSOPA
unchanged
Short Jump if Parity Odd. Only 8 low bits of result are

instructions.
Algorithm:
JPO
label
if PF = 0 then jump
Example:
ORG 100h
62
MPI

MOV AL, 00000111b ; AL = 7
OR AL, 0
; just set flags.
JPO label1
JMP exit
label1:
PRINT 'parity odd.'
exit:
RET
CZSOPA
unchanged
Short Jump if Signed (if negative). Set by CMP, SUB,

Algorithm:
if SF = 1 then jump
Example:
JS
label
ORG 100h
MOV AL, 10000000b ; AL = -128
OR AL, 0
; just set flags.
JS label1
PRINT 'not signed.'
JMP exit
label1:
PRINT 'signed.'
exit:
RET
CZSOPA
unchanged
Short Jump if Zero (equal). Set by CMP, SUB, ADD,

TEST, AND, OR, XOR instructions.
JZ
label
Algorithm:
if ZF = 1 then jump
Example:
63
MPI

ORG 100h
MOV AL, 5
CMP AL, 5
JZ label1
PRINT 'AL is not equal to 5.'
JMP exit
label1:
PRINT 'AL is equal to 5.'
exit:
RET
CZSOPA
unchanged
Load AH from 8 low bits of Flags register.

Algorithm:
AH = flags register
LAHF
No
operands
AH bit: 7 6 5 4 3 2 1 0
[SF] [ZF] [0] [AF] [0] [PF] [1] [CF]
bits 1, 3, 5 are reserved.
CZSOPA
unchanged
Load memory double word into word register and DS.

Algorithm:
LDS
REG,
memory
REG = first word

DS = second word
Example:
ORG 100h
LDS AX, m
RET
64
MPI

m DW 1234h
DW 5678h
END
AX is set to 1234h, DS is set to 5678h.
CZSOPA
unchanged
Load Effective Address.

Algorithm:
REG = address of memory (offset)
Example:
LEA
REG,
memory
MOV BX, 35h

MOV DI, 12h
LEA SI, [BX+DI] ; SI = 35h + 12h = 47h
Note: The integrated 8086 assembler automatically
replaces LEA with a more efficient MOV where possible.
For example:
org 100h
LEA AX, m
RET
m dw 1234h
END
; AX = offset of m
CZSOPA
unchanged
Load memory double word into word register and ES.

LES
REG,
memory
Algorithm:
REG = first word
65
MPI
ES = second word
Example:
ORG 100h
LES AX, m
RET
m DW 1234h
DW 5678h
END
AX is set to 1234h, ES is set to 5678h.
CZSOPA
unchanged
Load byte at DS:[SI] into AL. Update SI.

Algorithm:
AL = DS:[SI]
if DF = 0 then
o SI = SI + 1
else
o
LODSB
No
operands
SI = SI - 1
Example:
ORG 100h
LEA SI, a1
MOV CX, 5
MOV AH, 0Eh
m: LODSB
INT 10h
LOOP m
RET
a1 DB 'H', 'e', 'l', 'l', 'o'
CZSOPA
66
MPI

unchanged
Load word at DS:[SI] into AX. Update SI.

Algorithm:
AX = DS:[SI]
if DF = 0 then
o SI = SI + 2
else
o
LODSW
No
operands
SI = SI - 2
Example:
ORG 100h
LEA SI, a1
MOV CX, 5
REP LODSW ; finally there will be 555h in AX.
RET
a1 dw 111h, 222h, 333h, 444h, 555h
CZSOPA
unchanged
Decrease CX, jump to label if CX not zero.

Algorithm:
LOOP
CX = CX - 1
if CX <> 0 then
o jump
label
else
o
no jump, continue
Example:
ORG 100h
67
MPI

MOV CX, 5
label1:
PRINTN 'loop!'
LOOP label1
RET
CZSOPA
unchanged
Decrease CX, jump to label if CX not zero and Equal (ZF =

1).
Algorithm:
CX = CX - 1
if (CX <> 0) and (ZF = 1) then
o jump
else
o
LOOPE
label
no jump, continue
Example:
; Loop until result fits into AL alone,
; Or 5 times. The result will be over 255
; on third loop (100+100+100),
; So loop will exit.
ORG 100h
MOV AX, 0
MOV CX, 5
label1:
PUTC '*'
ADD AX, 100
CMP AH, 0
LOOPE label1
RET
CZSOPA
unchanged
68
MPI

Decrease CX, jump to label if CX not zero and Not Equal
(ZF = 0).
Algorithm:
CX = CX - 1
o jump
else
o
no jump, continue
Example:
; Loop until '7' is found,
; Or 5 times.
LOOPNE
label
ORG 100h
MOV SI, 0
MOV CX, 5
label1:
PUTC '*'
MOV AL, v1[SI]
INC SI
; next byte (SI=SI+1).
CMP AL, 7
LOOPNE label1
RET
v1 db 9, 8, 7, 6, 5
CZSOPA
unchanged
Decrease CX, jump to label if CX not zero and ZF = 0.

Algorithm:
LOOPNZ
label
CX = CX - 1
o jump
else
69
MPI

o
no jump, continue
Example:
; Loop until '7' is found,
; Or 5 times.
ORG 100h
MOV SI, 0
MOV CX, 5
label1:
PUTC '*'
MOV AL, v1[SI]
INC SI
; next byte (SI=SI+1).
CMP AL, 7
LOOPNZ label1
RET
v1 db 9, 8, 7, 6, 5
CZSOPA
unchanged
Decrease CX, jump to label if CX not zero and ZF = 1.

Algorithm:
CX = CX - 1
o jump
else
o
LOOPZ
no jump, continue
label
Example:
; Loop until result fits into AL alone,
; or 5 times. The result will be over 255
; on third loop (100+100+100),
; so loop will exit.
ORG 100h
MOV AX, 0
MOV CX, 5
label1:
PUTC '*'
70
MPI

ADD AX, 100
CMP AH, 0
LOOPZ label1
RET
CZSOPA
unchanged
Copy operand2 to operand1.

The MOV instruction cannot:
MOV
REG,
memory
memory,
REG
REG, REG
memory,
immediate
REG,
immediate
SREG,
memory
memory,
SREG
REG,
SREG
SREG,
REG
Set the value of the CS and IP registers.

Copy value of one segment register to another
segment register (should copy to general register
first).
copy immediate value to segment register (should
copy to general register first).
Algorithm:
operand1 = operand2
Example:
ORG 100h
MOV AX, 0B800h ; set AX = B800h (VGA memory).
MOV DS, AX
; copy value of AX to DS.
MOV CL, 'A'
; CL = 41h (ASCII code).
MOV CH, 01011111b; CL = color attribute.
MOV BX, 15Eh
; BX = position on screen.
MOV [BX], CX ; w.[0B800h:015Eh] = CX.
RET
; returns to operating system.
CZSOPA
unchanged
Copy byte at DS:[SI] to ES:[DI]. Update SI and DI.

MOVSB
No
operands
Algorithm:
ES:[DI] = DS:[SI]
if DF = 0 then
71
MPI

SI = SI + 1
DI = DI + 1
o
o
else
SI = SI - 1
DI = DI - 1
o
o
Example:
ORG 100h
CLD
LEA SI, a1
LEA DI, a2
MOV CX, 5
REP MOVSB
RET
a1 DB 1,2,3,4,5
a2 DB 5 DUP(0)
CZSOPA
unchanged
Copy word at DS:[SI] to ES:[DI]. Update SI and DI.

Algorithm:
MOVSW
No
operands
ES:[DI] = DS:[SI]
if DF = 0 then
o SI = SI + 2
o DI = DI + 2
else
o
o
SI = SI - 2
DI = DI - 2
Example:
ORG 100h
CLD
LEA SI, a1
72
MPI

LEA DI, a2
MOV CX, 5
REP MOVSW
RET
a1 DW 1,2,3,4,5
a2 DW 5 DUP(0)
CZSOPA
unchanged
Unsigned multiply.
Algorithm:
MUL
REG
memory

AX = AL * operand.
(DX AX) = AX * operand.
Example:
MOV AL, 200 ; AL = 0C8h
MOV BL, 4
MUL BL
; AX = 0320h (800)
RET
CZSOPA
r ? ? r ? ?
CF=OF=0 when high section of the result is zero.
Negate. Makes operand negative (two's complement).
Algorithm:
NEG
REG
memory
Invert all bits of the operand

Add 1 to inverted operand
Example:
MOV AL, 5 ; AL = 05h
NEG AL ; AL = 0FBh (-5)
NEG AL ; AL = 05h (5)
RET
CZSOPA
r r r r r r
73
MPI
No Operation.
Algorithm:
NOP
No
operands
Do nothing
Example:
; do nothing, 3 times:
NOP
NOP
NOP
RET
CZSOPA
unchanged
Invert each bit of the operand.

Algorithm:
NOT
REG
memory
if bit is 1 turn it to 0.
if bit is 0 turn it to 1.
Example:
MOV AL, 00011011b
NOT AL ; AL = 11100100b
RET
CZSOPA
unchanged
OR
REG,
memory
memory,
REG
REG, REG
memory,
immediate
REG,
immediate
Logical OR between all bits of two operands. Result is

stored in first operand.
These rules apply:
1 OR 1 = 1
1 OR 0 = 1
0 OR 1 = 1
0 OR 0 = 0
74
MPI

Example:
MOV AL, 'A'
; AL = 01000001b
OR AL, 00100000b ; AL = 01100001b ('a')
RET
CZSOPA
0 r r 0 r ?
Output from AL or AX to port.

First operand is a port number. If required to access port
number over 255 - DX register should be used.
OUT
im.byte,
AL
im.byte,
AX
DX, AL
DX, AX
Example:
MOV AX, 0FFFh ; Turn on all
OUT 4, AX ; traffic lights.
MOV AL, 100b ; Turn on the third
OUT 7, AL ; magnet of the stepper-motor.
CZSOPA
unchanged
Get 16 bit value from the stack.

Algorithm:
POP
REG
SREG
memory
operand = SS:[SP] (top of the stack)

SP = SP + 2
Example:
MOV AX, 1234h
PUSH AX
POP DX ; DX = 1234h
RET
CZSOPA
unchanged
POPA
No
operands
Pop all general purpose registers DI, SI, BP, SP, BX, DX,
CX, AX from the stack.
SP value is ignored, it is Popped but not set to SP register).
75
MPI
Note: this instruction works only on 80186 CPU and later!

Algorithm:
POP DI
POP SI
POP BP
POP xx (SP value ignored)
POP BX
POP DX
POP CX
POP AX
CZSOPA
unchanged
Get flags register from the stack.

Algorithm:
POPF
No
operands
flags = SS:[SP] (top of the stack)

SP = SP + 2
CZSOPA
popped
Store 16 bit value in the stack.

Note: PUSH immediate works only on 80186 CPU and
later!
PUSH
REG
SREG
memory
immediate
Algorithm:
SP = SP - 2
SS:[SP] (top of the stack) = operand
Example:
MOV AX, 1234h
PUSH AX
76
MPI

POP DX ; DX = 1234h
RET
CZSOPA
unchanged
Push all general purpose registers AX, CX, DX, BX, SP,
BP, SI, DI in the stack.
Original value of SP register (before PUSHA) is used.
Note: this instruction works only on 80186 CPU and later!
Algorithm:
PUSHA
No
operands
PUSH AX
PUSH CX
PUSH DX
PUSH BX
PUSH SP
PUSH BP
PUSH SI
PUSH DI
CZSOPA
unchanged
Store flags register in the stack.

Algorithm:
PUSHF
No
operands
SP = SP - 2
SS:[SP] (top of the stack) = flags
CZSOPA
unchanged
RCL
memory,
immediate
REG,
immediate
Rotate operand1 left through Carry Flag. The number of

rotates is set by operand2.
When immediate is greater then 1, assembler generates
several RCL xx, 1 instructions because 8086 has machine
77
MPI
memory,
CL
REG, CL
code only for this instruction (the same principle works for
all other shift/rotate instructions).
Algorithm:
shift all bits left, the bit that goes off is set to CF
and previous value of CF is inserted to the rightmost position.
Example:
STC
; set carry (CF=1).
MOV AL, 1Ch
; AL = 00011100b
RCL AL, 1
; AL = 00111001b, CF=0.
RET
CO
r r
OF=0 if first operand keeps original sign.
Rotate operand1 right through Carry Flag. The number of
rotates is set by operand2.
Algorithm:
RCR
memory,
immediate
REG,
immediate
memory,
CL
REG, CL
shift all bits right, the bit that goes off is set to CF
and previous value of CF is inserted to the left-most
position.
Example:
STC
; set carry (CF=1).
MOV AL, 1Ch
; AL = 00011100b
RCR AL, 1
; AL = 10001110b, CF=0.
RET
CO
r r
Repeat following MOVSB, MOVSW, LODSB, LODSW,
STOSB, STOSW instructions CX times.
REP
chain
instruction
Algorithm:
check_cx:
78
MPI

if CX <> 0 then
do following chain instruction

CX = CX - 1
go back to check_cx
else
exit from REP cycle
Z
r
Repeat following CMPSB, CMPSW, SCASB, SCASW

instructions while ZF = 1 (result is Equal), maximum CX
times.
Algorithm:
check_cx:
if CX <> 0 then
REPE
chain
instruction

CX = CX - 1
if ZF = 1 then:
o go back to check_cx
else
o
exit from REPE cycle
else
exit from REPE cycle
Example:
see cmpsb.asm in c:\emu8086\examples\.
Z
r
79
MPI

instructions while ZF = 0 (result is Not Equal), maximum
CX times.
Algorithm:
check_cx:
if CX <> 0 then
REPNE
chain
instruction

CX = CX - 1
if ZF = 0 then:
else
o
exit from REPNE cycle
else
exit from REPNE cycle
Z
r

instructions while ZF = 0 (result is Not Zero), maximum
CX times.
Algorithm:
check_cx:
REPNZ
chain
instruction
if CX <> 0 then

CX = CX - 1
if ZF = 0 then:
else
80
MPI

o
exit from REPNZ cycle
else
exit from REPNZ cycle
Z
r

instructions while ZF = 1 (result is Zero), maximum CX
times.
Algorithm:
check_cx:
if CX <> 0 then
REPZ
chain
instruction

CX = CX - 1
if ZF = 1 then:
else
o
exit from REPZ cycle
else
exit from REPZ cycle
Z
r
Return from near procedure.

RET
No
operands
or even
immediate
Algorithm:
Pop from stack:

o IP
81
MPI
if immediate operand is present: SP = SP + operand
Example:
ORG 100h ; for COM file.
CALL p1
ADD AX, 1
RET
; return to OS.
p1 PROC ; procedure declaration.
MOV AX, 1234h
RET ; return to caller.
p1 ENDP
CZSOPA
unchanged
Return from Far procedure.

Algorithm:
RETF
No
operands
or even
immediate
Pop from stack:

o IP
o CS
if immediate operand is present: SP = SP + operand
CZSOPA
unchanged
Rotate operand1 left. The number of rotates is set by

operand2.
ROL
memory,
immediate
REG,
immediate
memory,
CL
REG, CL
Algorithm:
shift all bits left, the bit that goes off is set to CF
and the same bit is inserted to the right-most
position.
Example:
MOV AL, 1Ch
; AL = 00011100b
ROL AL, 1
; AL = 00111000b, CF=0.
RET
CO
82
MPI

r r
Rotate operand1 right. The number of rotates is set by
operand2.
Algorithm:
ROR
memory,
immediate
REG,
immediate
memory,
CL
REG, CL
shift all bits right, the bit that goes off is set to CF
and the same bit is inserted to the left-most
position.
Example:
MOV AL, 1Ch
; AL = 00011100b
ROR AL, 1
; AL = 00001110b, CF=0.
RET
CO
r r
Store AH registers into low 8 bits of Flags register.
Algorithm:
flags register = AH
SAHF
No
operands
AH bit: 7 6 5 4 3 2 1 0
[SF] [ZF] [0] [AF] [0] [PF] [1] [CF]
bits 1, 3, 5 are reserved.
CZSOPA
r r r r r r
SAL
memory,
immediate
REG,
immediate
memory,
CL
REG, CL
Shift Arithmetic operand1 Left. The number of shifts is set

by operand2.
Algorithm:
Shift all bits left, the bit that goes off is set to CF.
Zero bit is inserted to the right-most position.
Example:
MOV AL, 0E0h
83
; AL = 11100000b
MPI

SAL AL, 1
RET
CO
; AL = 11000000b, CF=1.
r r
Shift Arithmetic operand1 Right. The number of shifts is
set by operand2.
Algorithm:
SAR
memory,
immediate
REG,
immediate
memory,
CL
REG, CL
Shift all bits right, the bit that goes off is set to CF.
The sign bit that is inserted to the left-most position
has the same value as before shift.
Example:
MOV AL, 0E0h
; AL = 11100000b
SAR AL, 1
; AL = 11110000b, CF=0.
MOV BL, 4Ch
; BL = 01001100b
SAR BL, 1
; BL = 00100110b, CF=0.
RET
CO
r r
Subtract with Borrow.
Algorithm:
SBB
REG,
memory
memory,
REG
REG, REG
memory,
immediate
REG,
immediate
operand1 = operand1 - operand2 - CF

Example:
STC
MOV AL, 5
SBB AL, 3 ; AL = 5 - 3 - 1 = 1
RET
CZSOPA
r r r r r r
84
MPI

Compare bytes: AL from ES:[DI].
Algorithm:
SCASB
No
operands
ES:[DI] - AL
if DF = 0 then
o DI = DI + 1
else
DI = DI - 1
CZSOPA
r r r r r r
Compare words: AX from ES:[DI].

Algorithm:
SCASW
No
operands
ES:[DI] - AX
if DF = 0 then
o DI = DI + 2
else
DI = DI - 2
CZSOPA
r r r r r r
SHL
memory,
immediate
REG,
immediate
memory,
CL
Shift operand1 Left. The number of shifts is set by

operand2.
Algorithm:
Shift all bits left, the bit that goes off is set to CF.
85
MPI
REG, CL
Zero bit is inserted to the right-most position.
Example:
MOV AL, 11100000b
SHL AL, 1
; AL = 11000000b, CF=1.
RET
CO
r r
Shift operand1 Right. The number of shifts is set by
operand2.
Algorithm:
SHR
memory,
immediate
REG,
immediate
memory,
CL
REG, CL
Shift all bits right, the bit that goes off is set to CF.
Zero bit is inserted to the left-most position.
Example:
MOV AL, 00000111b
SHR AL, 1
; AL = 00000011b, CF=1.
RET
CO
r r
Set Carry flag.
Algorithm:
STC
No
operands
CF = 1
C
1
STD
No
operands
Set Direction flag. SI and DI will be decremented by chain

instructions: CMPSB, CMPSW, LODSB, LODSW,
MOVSB, MOVSW, STOSB, STOSW.
86
MPI

Algorithm:
DF = 1
D
1
Set Interrupt enable flag. This enables hardware interrupts.

Algorithm:
STI
No
operands
IF = 1
I
1
Store byte in AL into ES: [DI]. Update DI.

Algorithm:
ES:[DI] = AL
if DF = 0 then
o DI = DI + 1
else
DI = DI - 1
STOSB
No
operands
Example:
ORG 100h
LEA DI, a1
MOV AL, 12h
MOV CX, 5
REP STOSB
RET
a1 DB 5 dup(0)
CZSOPA
87
MPI

unchanged
Store word in AX into ES:[DI]. Update DI.

Algorithm:
ES:[DI] = AX
if DF = 0 then
o DI = DI + 2
else
DI = DI - 2
STOSW
No
operands
Example:
ORG 100h
LEA DI, a1
MOV AX, 1234h
MOV CX, 5
REP STOSW
RET
a1 DW 5 dup(0)
CZSOPA
unchanged
Subtract.
SUB
REG,
memory
memory,
REG
REG, REG
memory,
immediate
REG,
immediate
Algorithm:
operand1 = operand1 - operand2
Example:
MOV AL, 5
SUB AL, 1
; AL = 4
RET
CZSOPA
r r r r r r
88
MPI
Logical AND between all bits of two operands for flags

only. These flags are affected: ZF, SF, PF. Result is not
stored anywhere.
These rules apply:
TEST
REG,
memory
memory,
REG
REG, REG
memory,
immediate
REG,
immediate
1 AND 1 = 1
1 AND 0 = 0
0 AND 1 = 0
0 AND 0 = 0
Example:
MOV AL, 00000101b
TEST AL, 1
; ZF = 0.
TEST AL, 10b
; ZF = 1.
RET
CZSOP
0 r r 0 r
Exchange values of two operands.

Algorithm:
operand1 < - > operand2
XCHG
REG,
memory
memory,
REG
REG, REG
Example:
MOV AL, 5
MOV AH, 2
XCHG AL, AH ; AL = 2, AH = 5
XCHG AL, AH ; AL = 5, AH = 2
RET
CZSOPA
unchanged
XLATB
No
operands
Translate byte from table.

Copy value of memory byte at DS: [BX + unsigned AL] to
AL register.
89
MPI

Algorithm:
AL = DS:[BX + unsigned AL]
Example:
ORG 100h
LEA BX, dat
MOV AL, 2
XLATB ; AL = 33h
RET
dat DB 11h, 22h, 33h, 44h, 55h
CZSOPA
unchanged
Logical XOR (Exclusive OR) between all bits of two

operands. Result is stored in first operand.
These rules apply:
XOR
REG,
memory
memory,
REG
REG, REG
memory,
immediate
REG,
immediate
1 XOR 1 = 0
1 XOR 0 = 1
0 XOR 1 = 1
0 XOR 0 = 0
Example:
MOV AL, 00000111b
XOR AL, 00000010b ; AL = 00000101b
RET
CZSOPA
0 r r 0 r ?
90
MPI
1.7) Assembler Directives:

An assembler needs predefined alphabetical strings called Assembler directives. i.e
the required storage for a particular constant/variable. Constant/ variable Logical names
of segments
Types of different routines and modules end of file etc.
ASSUME:
The ASSUME directive is used to tell the assembler the name of the logical
segment it should use for a specified segment.
Ex: Assume DS: Data, CS: code
It tells the assembler that, the inst. for a program car in logical segment code and in
segment named data.
If Ex: MOV AX, [BX]; after Assume
It will know that the memory location referred by [BX] is in logical segment
DATA. If we used stack in the program, then this statement should be included.
Assume SS: STACK-HERE
For string instructions which use DI, the assembler must be told that about ES
ASSUME ES; string Destination
DB: Define Byte
The DB directive is used to declare a byte -type variable.
Ex:
1. PRICES DB 49, 98H, 29H declare array of 3 bytes named PRICES and initialize 3
bytes as shown.
2. NAME DB `THOMAS'; Declare an array of 6 bytes and initialize with ASCII
codes for letters in THOMAS.
3. TEMP DB 100 DUP (?): Set a side 100 bytes of storage in memory named TEMP
and leave it uninitialized.
4. STORE DB 20H DUP (0): put 0 in all 20H locations.
DD: Define Double word
Ex:
ARRAY=PTR
DD
25629261
LES DI, ARRAY-PTR
The Low word of this double word 9261 is copied to DI, 2562 - ES.
91
MPI
DQ: Define Quad word

To reserve 4 words in memory.
Ex: STORAGE DQ 100 DUP (0)
DT: Define Ten Bytes
Ex: RESULTS DT 20H DUP (0): Declares an array of 20H blocks of 10 bytes each and
initialize all 320 bits to 00.
DW: Define word
Ex: WORD DW 1234H, 3456 H, 5678 H.
Declare an array of 3 words and initialize with specified values.
END: End program
It is put after the last statement of a program to tell the assembler that this is the end of
the program module.
A carriage return is required after the END directive.
ENDP: End Procedure
This is used along with the name of the procedure to indicate the end of a procedure to
assembler.
SQUARE PROC: Start a Procedure
SQUARE ENDP: End of a procedure
ENDS: End Segment
Ex: CODE SEGMENT
CODE ENDS
EQU: Equate
It is used to give a name to some value or symbol.
Each time the assembler fords the given name in the program, it will replace the
name with the value or symbol you equated with that name.
Ex: CONTROL - WORD EQU 11001001; Replacement
MOV AL, CONTROL- WORD; Assignment
EVEN:
Align on even memory address. The EVEN directive tells the assembler to
increment the location counter to the next even address if it is not already at an
even address.
92
MPI
The 8086 can read a word from memory in one bus cycle if word is at even
address, two bus cycles, if word is at Odd address. A NOP instruction is
inserted in the location incremented over.
Ex:
Average
EVEN
Record
Data ends
Data Segment
DB
DW
DUP
(?)
100
DUP
(0)
EXTRN: External
This is used to tell the assembler that the names or labels following the
directive are in some other assembly module.
Ex: For calling a procedure which is in a program module assembled at a
different time, you must tell the assembler that the procedure is external.
The assembler will then put the information in the object code file so that the
linker can connect the two modules together.
1. For Variables type (should be specified)
Ex: EXTRN DIVISOR: BYTE
2. for constant ABS
(Defined with EQU in another module)
2. For a Label -+ near/far
Names/ Labels referred to as external in one module must be declared public

with the PUBLIC directive.
EXTRN Statements should usually be bracketed with ENDS directive
ex:
PROCEDURE SEGMENT
EXTRNSMART:FAR
PROCEDURE ENDS
GLOBAL:
Declare symbols as PUBLIC or Extern.
The PUBLIC directive is used to tell the assembler that a specified name r label will be
accessed from other modules.
Ex: PUBLIC DIVISOR, DIVIDEND
93
MPI

SEGMENT:
It is used to indicate the start of the segment.
Ex:
Code Segment
Here code is name of the segment
CODE segment word
This statement tells the assembler that we want the contents of this segment located on
the next available word (even) address.
CODE Segment PUBLIC
GROUP:
Group Related Segments.
The GROUP directive is used to tell the assembler to group the logical segments
named after the directive into one logical group segment.
Ex:
SMALL Group Code, data, stacks.
Assume CS: Small, DS: Small, SS: Small
Include: Include source code form file.
It is used to tell the assembler to inset a block of source code form the named file into
the current source module.
LABEL:
As the assembler assemblers a section of data declarations or inst. statements,

it uses a location counter to keep track of how many bytes it is form the start of
a statement at any time.
The Label directive is used to give a name to the current value in the location
counter.
It should be followed by a term which specifies the type.
Label used as destination:

In jumps call
To refer data item:
far/near
byte/word
Ex: for Jump address:

Entry- point LABEL far; can jump to here from another segment
For data reference:
Stack Seg segment Stack
94
MPI

DW 100 DUP (0)
Stack - top LABEL word; given name to next location after last word in stack.
Stack- seg Ends.
Name:
It is used to give a specific name to each assembly module. Ex: Name PC-Board
ORG:
It tells the assembler to set the location counter to a desired value at any point
in the program.
Ex:
ORG 2000H
Org $ + 100
Current value
Ex:
ORG 2000H
RG $+100
$+100 is the current value
PROC: Procedure:
It is used to identify the start of a procedure.
Ex: SMART PROC FAR;
Here SMART is the name of procedure.
The procedure is FAR.
For ending it ENDP is used.
Operators:
PTR:
The PTR operator is used to assign a specific type to a variable or to a label.
Ex:
1. INC [BX]
It will not know whether to increment byte/word. INC BYTE PTR [BX]
2. Array of words:
WORDS DW 437AH, OB927H, 7C41 H for accessing a byte in the array
MOV AL, BYTE DTR WORDS
3. for Jump Instructions:
JMP [BX]
JMP BYTE PTR [BX]
95
MPI

OFFSET:
It is used to determine the offset/ displacement of a named data or proc form
the start of the segment.
Ex: MOV BX, OFFSET Prices
ADD AX, [BX]
SHORT:
It is used to tell the assembler that only a 1-byte displacement is needed to code
a jump inst.
If the jump destination is after Jump inst, it automatically reserves 2-bytes for
the displacement.
JMP LABEL
PC
2 bytes
JMP
PC
Short
Label
The short operator saves 1 byte of memory by telling that it needs to reserve only 1
byte for this particular jump.
1 byte
TYPE:
It tells the assembler to det. The type of a specified variable.
TYPE
For
byte
Word - 2
Double Word-> 4
Ex: MOV AL, TYPE Array
-1
Length:
(Not implemented in MASM)
No. of elements in some named data item.
Ex: MOV C , Length String 1
It produces the no, of bytes in the string if declared as bytes.
96
MPI
1.8) Procedures, and macros:

1.8.1) Procedures:
Procedure is a part of code that can be called from your program in order to make
some specific task.
Procedures make program more structural and easier to understand. Generally
procedure returns to the same point from where it was called.
The syntax for procedure declaration:
Name
PROC
;
;
here
of
goes
the
the
procedure
code
...
RET
name ENDP
Name - is the procedure name, the same name should be in the top and the
bottom; this is used to check correct closing of procedures.
Probably, you already know that RET instruction is used to return to operating
system.
The same instruction is used to return from procedure (actually operating system
sees your program as a special procedure).
PROC and ENDP are compiler directives, so they are not assembled into any real
machine code. Compiler just remembers the address of procedure.
CALL instruction is used to call a procedure.
Here is an example:
ORG 100h
CALL m1
MOV AX, 2
RET
; return to operating system.
97
MPI

m1 PROC
MOV BX, 5
RET
m1
; return to caller.
ENDP
END
The above example calls procedure m1, does MOV BX, 5, and returns to the next
instruction after CALL: MOV AX, 2.
There are several ways to pass parameters to procedure, the easiest way to pass
parameters is by using registers, here is another example of a procedure that
receives two parameters in AL and BL registers, multiplies these parameters and
returns the result in AX register:
ORG 100h
MOV AL, 1
MOV BL, 2
CALL
CALL
CALL
CALL
m2
m2
m2
m2
RET
m2 PROC
MUL BL
RET
m2 ENDP
; AX = AL * BL.
; return to caller.
END
98
MPI
In the above example value of AL register is update every time the procedure is
called, BL register stays unchanged, so this algorithm calculates 2 in power of 4,
so final result in AX register is 16 (or 10h). Here goes another example,
that uses a procedure to print a Hello World! message:
ORG 100h
LEA SI, msg
; load address of msg to SI.
CALL print_me
RET
;
==========================================================
; this procedure prints a string, the string should be null
; terminated (have zero in the end),
; the string address should be in SI register:
print_me PROC
next_char:
CMP b.[SI], 0 ; check for zero to stop
JE stop
;
MOV AL, [SI]
; next get ASCII char.
MOV AH, 0Eh

; teletype function number.
INT 10h
; using interrupt to print a char in AL.
ADD SI, 1
; advance index of string array.
JMP next_char ; go back, and type another char.

stop:
RET
; return to caller.
print_me ENDP
; ==========================================================
99
MPI

Msg
DB Hello World! 0 ; null terminated string.
END
"b." - prefix before [SI] means that we need to compare bytes, not words. When you need
to compare words add "w." prefix instead. When one of the compared operands is a
register it's not required because compiler knows the size of each register.
1.8.2) Macros:
Macros are just like procedures, but not really. Macros look like procedures, but they
exist only until your code is compiled, after compilation all macros are replaced with
real instructions.
If you declared a macro and never used it in your code, compiler will simply ignore it.
Emu8086.inc is a good example of how macros can be used; this file contains several
macros to make coding easier for you.
Macro definition:
Name MACRO [parameters...]
<instructions>
ENDM
Unlike procedures, macros should be defined above the code that uses it, for example:
My Macro
MACRO p1, p2, p3
MOV AX, p1
MOV BX, p2
MOV CX, p3
ENDM
ORG 100h
100
MPI

My Macro 1, 2, 3
My Macro 4, 5, DX
RET
The
above
code
MOV
MOV
MOV
MOV
MOV
MOV
is
AX,
BX,
CX,
AX,
BX,
CX,
expanded
into:
00001h
00002h
00003h
00004h
00005h
DX
Some important facts about macros and procedures:

i)
When you want to use a procedure you should use CALL instruction, for
example: CALL MyProc.
When you want to use a macro, you can just type its name. For example:
ii)
MyMacro.
iii)
Procedure is located at some specific address in memory, and if you use the same
procedure 100 times, the CPU will transfer control to this part of the memory. The
control will be returned back to the program by RET instruction. The stack is used to
keep the return address. The CALL instruction takes about 3 bytes, so the size of the
output executable file grows very insignificantly, no matter how many time the procedure
is used.
iv)
Macro is expanded directly in program's code. So if you use the same macro 100
times, the compiler expands the macro 100 times, making the output executable file
larger and larger, each time all instructions of a macro are inserted. You should use stack
or any general purpose registers to pass parameters to procedure.
v)
To pass parameters to macro, you can just type them after the macro name. For
example: My Macro 1, 2, 3.
vi)
To mark the end of the macro ENDM directive is enough.
vii)
To mark the end of the procedure, you should type the name of the procedure
101
MPI

before the ENDP directive.
Macros are expanded directly in code; therefore if there are labels inside the macro
definition you may get "Duplicate declaration" error when macro is used for twice or
more.
To avoid such problem, use LOCAL directive followed by names of variables, labels
or procedure names. For example:
Mymacro2 MACRO
LOCAL label1, label2
CMP AX, 2
JE label1
CMP AX, 3
JE label2
label1:
INC AX
label2:
ADD AX, 2
ENDM
ORG 100h
MyMacro2
MyMacro2
RET
If you plan to use your macros in several programs, it may be a good idea to place all
macros in a separate file. Place that file in Inc folder and use INCLUDE file-name
directive to use macros.
102
MPI

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CSE III B.Tech I SEMESTER

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1.1) An over view of 8085:

1) Block diagram of 8085 microprocessor:

Fig1.1: Block Diagram of 8085 microprocessor

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Fig1.2: 8085 bus structure

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These registers are identified as B, C, D, E, H, and L.

Fig 1.3: 8085 Registers

A) Sign Flag (S):

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4) Timing and Control unit:

5) Interrupt Control Unit:

It receives hardware interrupt signals and sends an acknowledgement for receiving

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The processor executes an interrupt service routine (ISR) addressed in program

ii) Hardware Interrupts:

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TRAP interrupt is edge and level triggered.

(2) RST 7.5:

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6) 8085 PIN DIAGRAM:

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AD0 - AD7 (input/output; 3-state)

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ALE (output) - Address Latch Enable.

RD (output 3-state, active low) - Read memory or IO device.

WR (output 3-state, active low) - Write memory or IO device.

IO/M (output) - Select memory or an IO device.

It is used to know the type of current operation of the microprocessor.

v) Interrupts and externally initiated operations:

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On receipt of an interrupt, the microprocessor acknowledges the interrupt by the

vi) Direct Memory Access (DMA):

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When E is low, Q enters a high impedance state; high impedance means it is

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1.2) ARCHITECTURE OF 8086 MICROPROCESSOR:

BUS INTERFACR UNIT:

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1.3) Special functions of General purpose registers:

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CSE III B.Tech I SEMESTER