LPC2148 I2C

Two Wire Interface (I2C)

Features:

Standard I2C compliant bus interfaces that may be configured as Master, Slave, or
Master/Slave

Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

Programmable clock to allow adjustment of I2C transfer rates

Bidirectional data transfer between masters and slaves.

Serial clock synchronization allows devices with different bit rates to communicate
via one serial bus.

Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

The I2C bus may be used for test and diagnostic purposes.
Registers:
I2C0CONSET

I2C0 Control Set Register

I2C0CONCLR

I2C0 Control Clear Register

I2C0STAT

I2C0 Status Register

I2C0DAT

I2C0 Data Register

I2C0ADR

I2C0 Address Register

I2C0SCLH

I2C0 SCL Duty Cycle Register High Half Word

I2C0SCLL

I2C0 SCL Duty Cycle Register Low Half Word

I2C0 Control Set Register (I2C0CONSET)

The I2CONSET registers control setting of bits in the I2CON register that controls
operation of the I2C interface. Writing a one to a bit of this register causes the corresponding
bit in the I2C control register to be set. Writing a zero has no effect.

AA: Acknowledgement bit .Writing logical 1 on this bit will cause ACK during the
acknowledge clock pulse on the SCL line on the following condition

The address in the Slave Address Register has been received.

The general call address has been received while the general call bit (GC) in I2ADR
is set.

A data byte has been received while the I2C is in the master receiver mode.

A data byte has been received while the I2C is in the addressed slave receiver mode.

SI: Interrupt Flag of I2C.Writing logical 1 on this bit will cause the low period of the serial
clock on the SCL line is stretched, and the serial transfer is suspended. This bit can be cleared
by writing one in SIC bit of I2C0CONCLR.
STO: STOP flag. Setting this bit causes the I2C interface to transmit a STOP condition in
master mode.
STA: START flag. Setting this bit causes the I2C interface to enter master mode and transmit
a START condition or transmit a repeated START condition if it is already in master mode.
I2EN: I2C Interface Enable. When I2EN is 1, the I2C interface is enabled. I2EN can be
cleared by writing 1 to the I2ENC bit in the I2CONCLR register. When I2EN is 0, the I2C
interface is disabled.
I2C0 Control Clear Register (I2C0CONCLR):
The I2CONCLR registers control clearing of bits in the I2CON register that controls
operation of the I2C interface. Writing a one to a bit of this register causes the corresponding
bit in the I2C control register to be cleared

AAC: One on this bit will cause NACK during master receive mode.
SIC: One on this bit will clear interrupt flag.
STAC: One on this bit will clear start condition.
I2ENC: One on this bit will disable I2C.
I2C0 Data Register (I2C0DAT):
This is 8 bit register, which hold the data that have been received, or are to be
transmitted.
I2C0 Address Register (I2C0ADR):

This is 8 bit register, which is used to hold the slave address during slave operating
mode.

GC: General call enable bit. One on this bit will cause I2C to recognize during general call.
Address: These bits will contain slave address which we are going to set.
I2C0 SCL Duty Cycle Register High/Low Half Word/(I2C0SCLH/I2C0SCLL)
These are 16 bit register contains value for calculating I2C frequency.

I2C0 Status Register (I2C0STAT):

The three least significant bits are always 0. Taken as a byte, the status register contents
represent a status code. There are 26 possible status codes. When the status code is 0xF8,
there is no relevant information available and the SI bit is not set. All other 25 status codes
correspond to defined I2C states. When any of these states entered, the SI bit will be set.
Status codes for
Master Transmit Mode:

Master Receiver Mode: