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In ModelSim, all designs are compiled into a library. New simulation in ModelSim is typically
started by creating a working library called "work". "Work" is the library name used by the
compiler as the default destination for compiled design units.
Loading the Simulator with the Design and Running the Simulation
With the design compiled, load the simulator with design by invoking the simulator on a
top-level module (Verilog) or a configuration or entity/architecture pair (VHDL). Assuming the
design loads successfully, the simulation time is set to zero, run command is used for beginning
simulation.
Figure 5.6 shows the Modelsim tool structure and flow. Figure 5.7 shows the simulations tasks.
CHAPTER 6
Xilinx ISE Tool for Synthesis and Place and Route
6.1 Xilinx ISE Tool Flow
Xilinx ISE Overview
The Integrated Software Environment (ISE) is the Xilinx design software suite that
allows you to take the design from design entry through Xilinx device programming. The ISE
Project Navigator manages and processes the design through the following steps in the ISE
design flow.
Design Entry
Design entry is the first step in the ISE design flow. During design entry, you create the
source files based on the design objectives. You can create the top-level design file using a
Hardware Description Language (HDL), such as VHDL, Verilog, or ABEL, or using a schematic.
You can use multiple formats for the lower-level source files in the design. If work starts with a
synthesized EDIF or NGC/NGO file, design entry and synthesis steps can be skipped and start
with the implementation process.
Synthesis
After design entry and optional simulation, you run synthesis. During this step, VHDL,
Verilog, or mixed language designs become netlist files that are accepted as input to the
implementation step.
Implementation
After synthesis, you run design implementation, which converts the logical design into a
physical file format that can be downloaded to the selected target device. From Project
Navigator, you can run the implementation process in one step, or you can run each of the
implementation processes separately. Implementation processes vary depending on whether you
are targeting a Field Programmable Gate Array (FPGA) or a Complex Programmable Logic
Device (CPLD).
Verification
You can verify the functionality of the design at several points in the design flow. You can
use simulator software to verify the functionality and timing of the design or a portion of the
design. The simulator interprets VHDL or Verilog code into circuit functionality and displays
logical results of the described HDL to determine correct circuit operation. Simulation allows
you to create and verify complex functions in a relatively small amount of time. You can also run
in-circuit verification after programming the device.
Device Configuration
After generating a programming file, you configure the device. During configuration, you
generate configuration files and download the programming files from a host computer to a
Xilinx device.
This project is uses Xilinx ISE tool for synthesis and FPGA implementation of the FFT
processor. The device chosen is Spartan3 XC3S400.
Synthesis using Xilinx can be done by following steps:
1. Now create a new project and select device VertexX2pro and then
2.
3.
4.
5.
6.
XC2VP40
Now add source code.
Go to Implementation
Synthesis XST
Now to change to Behavioral simulation
Run the source code
Spartan-3 generation includes 25 devices offering densities ranging from 50,000 to 5 million
system gates. Summary of Spartan-3A FPGSs is shown in Table 6.1
The Spartan-3 platform was the industrys first 90 nm FPGA, delivering more
functionality and bandwidth per dollar than was previously possible, setting new standards in the
programmable logic industry. The Spartan-3E platform builds on the success of the earlier
Spartan-3 platform by adding new features that improve system performance and reduce the cost
of configuration. The Extended Spartan-3A family builds on the success of the earlier Spartan-3E
platform by further enhancing configuration and reducing power to provide the lowest total cost.
The Spartan-3AN platform provides the additional benefits of non-volatility and large amounts
of on-board user flash. The Spartan-3A DSP platform extends the density range and adds
resources often required in digital signal processing (DSP) applications.
Because of their exceptionally low cost, Spartan-3 generation FPGAs are ideally suited to
a wide range of consumer electronics applications, including broadband access, home
networking, display/projection, and digital television equipment. The Spartan-3 generation
FPGAs provide a superior alternative to mask-programmed ASICs. FPGAs avoid the high initial
cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also,
FPGA programmability permits design upgrades in the field with no hardware replacement
necessary, an impossibility with ASICs.
Extended Spartan-3A Family Features
applications
Proven advanced 90-nanometer process technology
Dual-range VCCAUX supply at 2.5V or 3.3V simplifies the power supply design and
processor applications
Up to 373 Kbits of efficient distributed RAM
Up to eight Digital Clock Managers (DCMs)
Clock skew elimination (delay locked loop)
Frequency synthesis, multiplication, division
High-resolution phase shifting
Wide frequency range (5 MHz to over 300 MHz)
Eight global clocks, plus abundant low-skew routing
Eight additional clocks per each half of the device
Additional clock inputs for pinout flexibility and differential clocks
Configuration interface to low-cost Xilinx Platform Flash with JTAG
Configuration interface to industry-standard PROMs
Low-cost, space-saving SPI serial Flash PROM
x8 or x8/x16 parallel NOR Flash PROM
Configuration watchdog timer automatically recovers from configuration errors
Unique ID (Device DNA) in each device useful for copy protection algorithms
Device DNA authentication restricts copying
MultiBoot automatic reconfiguration between two files
Complete Xilinx ISE and WebPACK development system support
Low-cost Starter Kit development systems and advanced demo boards
32-bit MicroBlaze and 8-bit PicoBlaze embedded processor cores
Fully compliant 32-/64-bit 66 MHz PCI support
PCI Express PIPE endpoint and other IP cores
Supported by major EDA partners
Low-cost QFP and BGA packaging options
Common footprints support easy density migration within each platform (except designs
Configurable Logic Blocks (CLBs) contain flexible Look-Up Tables (LUTs) that implement
logic plus storage elements used as flip-flops or latches. CLBs perform a wide variety of logical
functions as well as store data.
Input/output Blocks (IOBs) control the flow of data between the I/O pins and the internal
logic of the device. IOBs support bidirectional data flow plus 3-state operation. Supports a
variety of signal standards, including several high-performance differential standards. Double
Data-Rate (DDR) registers are included.
Block RAM provides data storage in the form of 18-Kbit dual-port blocks.
Multiplier Blocks accept two 18-bit binary numbers as inputs and calculate the product. The
Spartan-3A DSP platform includes special DSP multiply-accumulate blocks.
Digital Clock Manager (DCM) Blocks provide self-calibrating, fully digital solutions for
distributing, delaying, multiplying, dividing, and phase-shifting clock signals.
These elements are organized as shown in Figure 6.2, using the Spartan-3A FPGA array
as an example. A dual ring of staggered IOBs surrounds a regular array of CLBs in the Spartan-3
and Extended Spartan-3A family. The Spartan-3E family has a single ring of inline IOBs. Each
block RAM column consists of several 18-Kbit RAM blocks. Each block RAM is associated
with a dedicated multiplier. The DCMs are positioned with two at the top and two at the bottom
of the device, plus additional DCMs on the sides for the larger devices.
The Spartan-3 generation features a rich network of traces that interconnect all five
functional elements, transmitting signals among them. Each functional element has an associated
switch matrix that permits multiple connections to the routing.
Flash
Spartan-3E and Extended Spartan-3A family FPGAs only
Slave Serial, typically downloaded from a processor
Slave Parallel, typically downloaded from a processor