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PROBLEM DESCRIPTION
1.) Given the Schematic Diagram in Figure 1 and its
corresponding device parameters, plot the load line for an
enhancement mode NMOS. The common gate and drain is
tied to a 5V supply.
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6.) Repeat Problem #5 now with
as shown in
L M 2 2
Figure 4. Discuss and analyze the results of both
Problem #5 and #6.
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W
Figure 3. With
.
2
L M 2
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W
Figure 4. With
L M 2 2