EletrnicaDigitalModernaeVHDL

VolneiA.Pedroni
Elsevier/Campus,SoPaulo,2010



Traduo(comreviso,atualizaoeampliao)de
DigitalElectronicsandDesignwithVHDL
Elsevier/MorganKaufmann,BurlingtonMA,USA,2008

Bookweb:www.elsevier.com.br/site/institucional/minhapaginaautor.aspx?seg=0&aid=75936

AmostrasdeCdigosVHDL(Captulos1924)

Osseguintescdigosconstamnestedocumento:
Exemplo19.1:Multiplexadorcombuffer
Exemplo19.4:Detectordeparidade
Seo20.2:FunoconversoradeBCDparaSSD
Seo20.3:Multiplexadorgenrico
Seo21.1:Somadorcarryripple
Seo21.5:ALU
Seo22.3:Timer
Seo23.2:Alarmeparacarro(primeiraparte)
Seo24.9:TestbenchtipoIV

Outroscdigos:Vejaosdocumentosabaixo.
AmostrasdeSoluesSelecionadasdaParteII(Captulos19a25)
ManualdeSoluesdosCaptulos19a25

Exemplo19.1:Multiplexadorcombuffer

1 ----------------------------------------------------
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 ----------------------------------------------------
5 ENTITY buffered_mux IS
6 PORT (a, b, c, d: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
7 sel: IN NATURAL RANGE 0 TO 3;
8 ena: IN STD_LOGIC;
9 y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
10 END buffered_mux;
11 ----------------------------------------------------
12 ARCHITECTURE myarch OF buffered_mux IS
13 SIGNAL x: STD_LOGIC_VECTOR(7 DOWNTO 0);
14 BEGIN
15 x <= a WHEN sel=0 ELSE --Mux
16 b WHEN sel=1 ELSE
17 c WHEN sel=2 ELSE
18 d;
19 y <= x WHEN ena='1' ELSE -Tristate buffer
20 (OTHERS => 'Z');
21 END myarch;
22 ----------------------------------------------------

Exemplo19.4:Detectordeparidade

1 ----------------------------------------------
2 ENTITY parity_detector IS
3 GENERIC (N: INTEGER := 8); --number of bits
4 PORT (x: IN BIT_VECTOR(N1 DOWNTO 0);
5 y: OUT BIT);
6 END parity_detector;
7 ----------------------------------------------
8 ARCHITECTURE structural OF parity_detector IS
9 SIGNAL internal: BIT_VECTOR(N1 DOWNTO 0);
10 BEGIN
 EletrnicaDigitalModernaeVHDL,VolneiA.Pedroni,Elsevier/Campus,2010.2

11 internal(0) <= x(0);

12 gen: FOR i IN 1 TO N1 GENERATE
13 internal(i) <= internal(i1) XOR x(i);
14 END GENERATE;
15 y <= internal(N1);
16 END structural;
17 ----------------------------------------------

Seo20.2:FunoconversoradeBCDparaSSD

1 -----Package:------------------------------------------------------
2 PACKAGE my_functions IS
3 FUNCTION bcd_to_ssd (SIGNAL input: INTEGER) RETURN BIT_VECTOR;
4 END my_functions;
5 -------------------------------------------------------------------
6 PACKAGE BODY my_functions IS
7 FUNCTION bcd_to_ssd (SIGNAL input: INTEGER) RETURN BIT_VECTOR IS
8 VARIABLE output: BIT_VECTOR(6 DOWNTO 0);
9 BEGIN
10 CASE input IS
11 WHEN 0 => output:= "1111110"; --decimal 126
12 WHEN 1 => output:= "0110000"; --decimal 48
13 WHEN 2 => output:= "1101101"; --decimal 109
14 WHEN 3 => output:= "1111001"; --decimal 121
15 WHEN 4 => output:= "0110011"; --decimal 51
16 WHEN 5 => output:= "1011011"; --decimal 91
17 WHEN 6 => output:= "1011111"; --decimal 95
18 WHEN 7 => output:= "1110000"; --decimal 112
19 WHEN 8 => output:= "1111111"; --decimal 127
20 WHEN 9 => output:= "1111011"; --decimal 123
21 WHEN OTHERS => output:= "1001111"; --"E"rror, decimal 79
22 END CASE;
23 RETURN output;
24 END bcd_to_ssd;
25 END my_functions;
26 -------------------------------------------------------------------

1 ------Main code:-------------------------------
2 USE work.my_functions.all;
3 -----------------------------------------------
4 ENTITY bcd_to_ssd_converter IS
5 PORT (x: IN INTEGER RANGE 0 TO 9;
6 y: OUT BIT_VECTOR(6 DOWNTO 0));
7 END ENTITY;
8 -----------------------------------------------
9 ARCHITECTURE decoder OF bcd_to_ssd_converter IS
10 BEGIN
11 y <= bcd_to_ssd(x);
12 END ARCHITECTURE;
13 -----------------------------------------------

Seo20.3:Multiplexadorgenrico

1 -----Package:-------------------------------------------------------
2 PACKAGE my_data_types IS
3 TYPE matrix IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF BIT;
4 END PACKAGE my_data_types;
5 --------------------------------------------------------------------

1 -----Main code:-----------------------------------------
2 USE work.my_data_types.all;
3 --------------------------------------------------------
4 ENTITY generic_mux IS
5 GENERIC (M: INTEGER := 4; --number of inputs
6 N: INTEGER := 3); --number of bits per input
7 PORT (x: IN matrix (0 TO M1, N1 DOWNTO 0);
8 sel: IN INTEGER RANGE 0 TO M1;
9 y: OUT BIT_VECTOR (N1 DOWNTO 0));
10 END generic_mux;
11 --------------------------------------------------------
12 ARCHITECTURE arch OF generic_mux IS
13 BEGIN
14 gen: FOR i IN N1 DOWNTO 0 GENERATE
15 y(i) <= x(sel, i);
16 END GENERATE gen;
17 END arch;
18 --------------------------------------------------------

 EletrnicaDigitalModernaeVHDL,VolneiA.Pedroni,Elsevier/Campus,2010.3

Seo21.1:Somadorcarryripple

1 -----------------------------------------------------
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 -----------------------------------------------------
5 ENTITY carry_ripple_adder IS
6 GENERIC (N : INTEGER := 8); --number of bits
7 PORT (a, b: IN STD_LOGIC_VECTOR(N1 DOWNTO 0);
8 cin: IN STD_LOGIC;
9 s: OUT STD_LOGIC_VECTOR(N1 DOWNTO 0);
10 cout: OUT STD_LOGIC);
11 END carry_ripple_adder;
12 -----------------------------------------------------
13 ARCHITECTURE structure OF carry_ripple_adder IS
14 BEGIN
15 PROCESS(a, b, cin)
16 VARIABLE carry : STD_LOGIC_VECTOR (N DOWNTO 0);
17 BEGIN
18 carry(0) := cin;
19 FOR i IN 0 TO N1 LOOP
20 s(i) <= a(i) XOR b(i) XOR carry(i);
21 carry(i+1) := (a(i) AND b(i)) OR (a(i) AND
22 carry(i)) OR (b(i) AND carry(i));
23 END LOOP;
24 cout <= carry(N);
25 END PROCESS;
26 END structure;
27 -----------------------------------------------------

Seo21.5:ALU

1 -------------------------------------------------
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 USE ieee.std_logic_unsigned.all;
5 -------------------------------------------------
6 ENTITY alu IS
7 PORT (a, b: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
8 cin: IN STD_LOGIC;
9 opcode: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
10 y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
11 END alu;
12 -------------------------------------------------
13 ARCHITECTURE alu OF alu IS
14 BEGIN
15 WITH opcode SELECT
16 --logic part:--------
17 y <= a WHEN "0000",
18 NOT a WHEN "0001",
19 b WHEN "0010",
20 NOT b WHEN "0011",
21 a AND b WHEN "0100",
22 a NAND b WHEN "0101",
23 a OR b WHEN "0110",
24 a NOR b WHEN "0111",
25 --arithmetic part:---
26 a+1 WHEN "1000",
27 b+1 WHEN "1001",
28 a+b WHEN "1010",
29 ab WHEN "1011",
30 a+b WHEN "1100",
31 ab WHEN "1101",
32 a+b+1 WHEN "1110",
33 a+b+cin WHEN OTHERS;
34 END alu;
35 -------------------------------------------------

Seo22.3:Timer

1 ---------------------------------------------------------
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 ---------------------------------------------------------
5 ENTITY timer IS
6 GENERIC (fclk: INTEGER := 2); --clock frequency
7 PORT (clk, rst, ena: IN STD_LOGIC;
8 full_count: OUT STD_LOGIC;
9 dig1, dig2: OUT STD_LOGIC_VECTOR (6 DOWNTO 0));
10 END timer;
11 ---------------------------------------------------------
 EletrnicaDigitalModernaeVHDL,VolneiA.Pedroni,Elsevier/Campus,2010.4

12 ARCHITECTURE timer OF timer IS

13 BEGIN
14 PROCESS(clk, rst, ena)
15 VARIABLE count0: INTEGER RANGE 0 TO fclk; --for 1Hz
16 VARIABLE count1: INTEGER RANGE 0 TO 10; --for dig1
17 VARIABLE count2: INTEGER RANGE 0 TO 7; --for dig2
18 BEGIN
19 -----counters:----------------------
20 IF (rst='1') THEN
21 count0 := 0;
22 count1 := 0;
23 count2 := 0;
24 full_count <= '0';
25 ELSIF (count1=0 AND count2=6) THEN
26 full_count <= '1';
27 ELSIF (clk'EVENT AND clk='1') THEN
28 IF (ena='1') THEN
29 count0 := count0 + 1;
30 IF (count0=fclk) THEN
31 count0 := 0;
32 count1 := count1 + 1;
33 IF (count1=10) THEN
34 count1 := 0;
35 count2 := count2 + 1;
36 END IF;
37 END IF;
38 END IF;
39 END IF;
40 -----SSD drivers:-------------------
41 CASE count1 IS
42 WHEN 0 => dig1 <= "1111110"; --126
43 WHEN 1 => dig1 <= "0110000"; --48
44 WHEN 2 => dig1 <= "1101101"; --109
45 WHEN 3 => dig1 <= "1111001"; --121
46 WHEN 4 => dig1 <= "0110011"; --51
47 WHEN 5 => dig1 <= "1011011"; --91
48 WHEN 6 => dig1 <= "1011111"; --95
49 WHEN 7 => dig1 <= "1110000"; --112
50 WHEN 8 => dig1 <= "1111111"; --127
51 WHEN 9 => dig1 <= "1111011"; --123
52 WHEN OTHERS => dig1 <= "1001111"; --79 ("E")
53 END CASE;
54 CASE count2 IS
55 WHEN 0 => dig2 <= "1111110"; --126
56 WHEN 1 => dig2 <= "0110000"; --48
57 WHEN 2 => dig2 <= "1101101"; --109
58 WHEN 3 => dig2 <= "1111001"; --121
59 WHEN 4 => dig2 <= "0110011"; --51
60 WHEN 5 => dig2 <= "1011011"; --91
61 WHEN 6 => dig2 <= "1011111"; --95
62 WHEN OTHERS => dig2 <= "1001111"; --79 ("E")
63 END CASE;
64 END PROCESS;
65 END timer;
66 ---------------------------------------------------------

Seo23.2:Alarmeparacarro(primeiraparte)

1 ----------------------------------------------------------------
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 ----------------------------------------------------------------
5 ENTITY car_alarm IS
6 PORT (clk, rst, remote, sensors: IN STD_LOGIC;
7 siren: OUT STD_LOGIC);
8 END car_alarm;
9 ----------------------------------------------------------------
10 ARCHITECTURE fsm OF car_alarm IS
11 TYPE alarm_state IS (disarmed, armed, intrusion);
12 ATTRIBUTE enum_encoding: STRING;
13 ATTRIBUTE enum_encoding OF alarm_state: TYPE IS "sequential";
14 SIGNAL pr_state, nx_state: alarm_state;
15 SIGNAL flag: STD_LOGIC;
16 BEGIN
17 -----Flag:------------------
18 PROCESS (remote, rst)
19 BEGIN
20 IF (rst='1') THEN
21 flag <= '0';
22 ELSIF (remote'EVENT AND remote='0') THEN
23 flag <= NOT fl ag;
 EletrnicaDigitalModernaeVHDL,VolneiA.Pedroni,Elsevier/Campus,2010.5

24 END IF;
25 END PROCESS;
26 -----Lower section:---------
27 PROCESS (clk, rst)
28 BEGIN
29 IF (rst='1') THEN
30 pr_state <= disarmed;
31 ELSIF (clk'EVENT AND clk='1') THEN
32 pr_state <= nx_state;
33 END IF;
34 END PROCESS;
35 -----Upper section:---------
36 PROCESS (pr_state, fl ag, remote, sensors)
37 BEGIN
38 CASE pr_state IS
39 WHEN disarmed =>
40 siren <= '0';
41 IF (remote='1' AND fl ag='0') THEN
42 nx_state <= armed;
43 ELSE
44 nx_state <= disarmed;
45 END IF;
46 WHEN armed =>
47 siren <= '0';
48 IF (sensors='1') THEN
49 nx_state <= intrusion;
50 ELSIF (remote='1' AND fl ag='1') THEN
51 nx_state <= disarmed;
52 ELSE
53 nx_state <= armed;
54 END IF;
55 WHEN intrusion =>
56 siren <= '1';
57 IF (remote='1' AND fl ag='1') THEN
58 nx_state <= disarmed;
59 ELSE
60 nx_state <= intrusion;
61 END IF;
62 END CASE;
63 END PROCESS;
64 END fsm;
65 ----------------------------------------------------------------

Seo24.9:TestbenchtipoIV

Nota:Ocdigoabaixoempregaatcnicadecomparaointensiva.Paraoutrastcnicas,vejaassoluesdos
exercciosdocaptulo24.Descriesmaisdetalhadasestodisponveisemwww.vhdl.us.

1 ----Test file (test_clock_divider.vhd):-----------------

2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 --------------------------------------------------------
5 ENTITY test_clock_divider IS
6 END ENTITY;
7 --------------------------------------------------------
8 ARCHITECTURE testbench OF test_clock_divider IS
9 ----component declaration:-----
10 COMPONENT clock_divider IS
11 PORT (clk, ena: IN STD_LOGIC;
12 output: OUT STD_LOGIC);
13 END COMPONENT;
14 ----signal declarations:-------
15 SIGNAL clk: STD_LOGIC := '0';
16 SIGNAL ena: STD_LOGIC := '0';
17 SIGNAL output: STD_LOGIC;
18 SIGNAL template: STD_LOGIC;
19 BEGIN
20 ----component instantiation:---
21 dut: clock_divider PORT MAP (clk, ena, output);
22 ----generate clock:------------
23 PROCESS
24 BEGIN
25 WAIT FOR 30 ns;
26 clk <= NOT clk;
27 END PROCESS;
28 ----generate enable:-----------
29 PROCESS
30 BEGIN
31 WAIT FOR 60 ns;
32 ena <= '1';
33 WAIT; --optional
 EletrnicaDigitalModernaeVHDL,VolneiA.Pedroni,Elsevier/Campus,2010.6

34 END PROCESS;
35 ----generate template:---------
36 PROCESS
37 BEGIN
38 WAIT FOR 339 ns;
39 WHILE ena='1' LOOP
40 template <= NOT template;
41 WAIT FOR 300 ns;
42 END LOOP;
43 END PROCESS;
44 ----verify output:-------------
45 PROCESS
46 BEGIN
47 WAIT FOR 10 ns;
48 ASSERT (output=template)
49 REPORT "Output differs from template!"
50 SEVERITY FAILURE;
51 IF NOW=2000ns THEN
52 ASSERT FALSE
53 REPORT "Output is OK! (end time 2us)"
54 SEVERITY NOTE;
55 END IF;
56 END PROCESS;
57 END ARCHITECTURE;
58 --------------------------------------------------------