Analogue Electronics Complete Course Summary Notes With Examples HD

ECE2061 - Analogue Electronics Summary
Notes
Contents
Equivalent
Circuits .......................................................................................
..................... 5
Thevenin
Equivalent ..................................................................................................
............. 5
Norton
Equivalent ..................................................................................................
................ 5
Analogue Signal
Amplification ...............................................................................
........... 6
Amplifier Frequency
Response .............................................................................................. 6
Tolerance
Modelling ....................................................................................
..................... 7
Ideal
Amplifiers ...................................................................................
............................. 7
Differential Amplifier
Model .................................................................................................. 7
Input and Output
Resistances ................................................................................................
7
Unity Gain
Buffer .........................................................................................................
........... 8
Summing
Amplifier ....................................................................................................
............. 8
Difference
Amplifier ....................................................................................................
........... 8
Finn Andersen, 2012 1

Instrumentation
Amplifier ....................................................................................................
.8
Integrator ...................................................................................................
............................ 9
Differentiator...............................................................................................
........................... 9
Non-Ideal Operational
Amplifiers ...................................................................................
10
Feedback ....................................................................................................
.......................... 10
Classic Feedback
Systems .....................................................................................................
10
Non-Ideal Operational
Amplifier .......................................................................................... 10
Non-zero output
resistance .................................................................................................
11
Finite Input
Resistance ..................................................................................................
....... 11
Summary ...................................................................................................
........................... 11
Feedback Amplifier
Categories: ........................................................................................... 12
Blackmans
Theorem ....................................................................................................
........ 13
Series-Shunt Feedback
Model .............................................................................................. 13
Shunt-Shunt Feedback
Model .............................................................................................. 16
Series-Series Feedback
Model ............................................................................................. 17
Shunt-Series Feedback
Model .............................................................................................. 18

Successive Voltage and Current
Injection ............................................................................ 19
Distortion Reduction through use of
Feedback ................................................................... 21 DC Error Sources
and Output Range
Limitations .................................................................22
Common-Mode Rejection and Input
Resistance ................................................................. 23
Frequency Response and Bandwidth of Op-
Amps .............................................................. 24
Slew Rate and Full Power
Bandwidth .................................................................................. 27
Operational Amplifier
Applications ................................................................................
. 28
Cascaded
Amplifiers ...................................................................................................
.......... 28
Instrumentation
Amplifier ...................................................................................................
28
Switched-Capacitor
Circuits ................................................................................................. 29
Digital to Analogue Converters
(DACs) ................................................................................ 30
DAC
Circuits .........................................................................................................
............. 31
Analogue to Digital
Conversion ............................................................................................ 32
ADC
Errors ...........................................................................................................
............. 33
AD Conversion
Techniques .............................................................................................. 34
Oscillators ..................................................................................................
........................... 37
Circuits Using Positive
Feedback .......................................................................................... 38

Solid State
Electronics ..................................................................................
.................. 40
Drift Currents and
Mobility ..................................................................................................
41
Impurities in
Semiconductors .........................................................................................
..... 42
Electron and Hole Concentrations in Doped
Semiconductors............................................. 43
Mobility and Resistivity in Doped
Semiconductors ............................................................. 44
Diffusion
Current .......................................................................................................
........... 44
Total
Current .......................................................................................................
................. 45
Energy Band
Model .........................................................................................................
..... 45
Integrated Circuit
Fabrication ..............................................................................................
46
Solid-State
Diodes ........................................................................................
.................. 47
I-V Characteristics of a
Diode ............................................................................................... 48
Diode
Biasing .......................................................................................................
................. 49
Diode Reverse
Bias ............................................................................................................
... 50
Schottky Barrier
Diode .........................................................................................................
51

Diode Circuit
Analysis ......................................................................................................
..... 51
Multiple Diode
Circuits .......................................................................................................
.. 52
Diodes in Reverse
Breakdown ..............................................................................................
53 Half-Wave Rectifier
Circuits .................................................................................................54
Full-Wave Rectifier
Circuits .................................................................................................. 57
Full-Wave Bridge
Rectification .............................................................................................
58
Rectifier
Summary ...................................................................................................
............. 58
Diode Dynamic Switching
Behaviour ................................................................................... 58
Photo Diodes, Solar Cells,
LEDs ............................................................................................ 59
Bipolar Junction
Transistors ..................................................................................
.......... 60
Physical
Structure ....................................................................................................
............. 60
Transport Model for npn
Transistor..................................................................................... 60
The pnp
Transistor ...................................................................................................
............ 61
Equivalent Circuit
Representations ......................................................................................
62
The i-v Characteristics of
BJT ................................................................................................ 62

Operating
Regions ......................................................................................................
.......... 63
Transport Model
Simplifications ..........................................................................................
63
Non-Ideal BJT
Behaviour ...................................................................................................
... 64
Practical Bias Circuits for
BJT ................................................................................................ 65
Tolerances in Bias
Circuits ....................................................................................................
66
Field-Effect
Transistors ..................................................................................
................. 67
MOS
Capacitor.....................................................................................................
................. 67
The NMOS
Transistor ...................................................................................................
........ 68
PMOS
Transistors ..................................................................................................
............... 73
MOSFET Circuit
Symbols .....................................................................................................
. 74
Capacitances in MOS
Transistors ......................................................................................... 75
MOS Transistor
Scaling .......................................................................................................
.. 75
Biasing
NMOSFET ...................................................................................................
.............. 76
The Junction Field-Effect Transistor
(JFET) .......................................................................... 78

Small Signal Modelling and Linear
Amplification ............................................................. 80
BJT
Amplifier ....................................................................................................
..................... 80
MOSFET
Amplifier ....................................................................................................
............ 81
Coupling and Bypass
Capacitors........................................................................................... 81
Circuit Analysis using DC and AC Equivalent
Circuits ........................................................... 82
Small-Signal
Modelling ...................................................................................................
...... 83 Small-Signal Models for
BJT .................................................................................................84
Common-Emitter
Amplifier ..................................................................................................
86
Limits and Model
Simplifications .........................................................................................
87
Small-Signal Models for
FETs ............................................................................................... 87
Summary of BJT and FET
Differences ................................................................................... 89
Common-Source
Amplifier ...................................................................................................
90
Input and Output
Resistances ..............................................................................................
90
Common-Emitter and Common-Source
Summary .............................................................. 91
Amplifier Power and Signal
Range ....................................................................................... 91
Single Transistor
Amplifiers ...................................................................................
......... 93

Inverting Amplifiers - Common
Emitter/Source .................................................................. 94
Follower Circuits - Common-
Collector/Drain ....................................................................... 96
Non-inverting Amplifiers Common-
Base/Gate ................................................................. 98
Amplifier
Comparison ................................................................................................
.......... 99
Coupling and Bypass Capacitor
Design .............................................................................. 101
Multi-stage AC-Coupled
Amplifiers .................................................................................... 102

Equivalent Circuits
Thevenin Equivalent 1. Apply KCL atoutput node

.
Finding voltage:
defined as output voltage with no load
Substitute and re-arrange:
Finding Resistance:
1. Cut out independent voltage/current sources. If dependent ones
exist, add in test voltage:
1. Thevenin equivalent
resistance equal to:

2. Do KCL at output node, solve
for
Norton Equivalent
No current flows because of resistor
3. Apply short circuitacross output,

current flowing here is Norton
equivalent current.
4. Apply KCL to solvenfor i
Analogue Signal Amplification

For input signal:
After a linear amplifier, output has same frequency but different
amplitude and phase:
Gain (phasor notation):

Negative gain is equivalent to 180
phase shift
Amplifier model:
Power gain:
Convert to decibel scale:
Amplifier Frequency Response

Amplifiers can be designed to amplify specific frequency ranges.
Tolerance Modelling
Components have manufacturing tolerances, e.g Resistors with 5%
tolerance.
Leads to nominal and worst case circuit situations.

Maximimise/minimize appropriate values to achieve max/min vo.
Ideal Amplifiers
Differential Amplifier Model
Amplifies the voltage difference of two inputs.

Input and Output Resistances

For basic amplifier,
Apply test current, turn off independent sources, determine voltage.
( 2) 2


Unity Gain Buffer
Has a gain of 1 (no change in voltage)
Does not draw current from input
terminal, does not provide load to input
circuit.
Summing Amplifier
Sums input signals
Difference Amplifier
2
( 2 )

2 2
Instrumentation Amplifier
Virtual ground at R1. R1 can be changed
to change gain instead of altering
resistor pairs.
4 2
( ) ( 2 )
3
Infinite input resistance
Zero output resistance

Integrator
Integrates the input voltage.
Capacitor initially starts out as an effective short circuit

Gains resistance as it charges
Infinite resistance when fully charged, output voltage reaches saturated level,
determined by supply rails.
If alter nating signal is applied:
Capacitor is charged and discharged

Results in sawtooth waveform output
Waveform output dependent on RC time constant

Differentiator
Capacitor and resistor reversed.

,

Non-Ideal Operational Amplifiers

Feedback
Effects:
Gain stability Reduces sensitivity of gain to variations in values of

transistor parameters and circuit elements
Input and Output Impedances Feedback can determine input
and output resistances of amplifier
Bandwidth (range of frequencies that the amplifier is most
effective at amplifying), can be extended using feedback
Nonlinear Distortion Reduces effects of nonlinear distortion
Classic Feedback Systems

Closed- loop gain:
Feedback Factor Open- loop gain
Non- Ideal Operational Amplifier

Various forms of error arise in practical operational amplifiers due to non-
ideal behaviour:

Finite open loop gain causes gain error
Nonzero output resistance
2
Finite input resistance

DC errorsources (
)
2
Output voltage and current limits
( )
Finite Open
- Loop Gain
( )
2
( )

( )

2
( )

2 2
( 10
)

Non-zero output resistance

Output resistance calculation circuit is identical for both amplifiers.

Shunt/Parallel Feedback ||( 2)

In most cases
( 2 ),
Finite Input Resistance

Non-Inverting Amplifier Inverting Amplifier

Approaches infinity for large Since Rid is large, can be
approximated:
Summary
Feedback Amplifier Categories:

There are 4 different types of amplifiers based on feedback configuration.
Type Config. Diagram Purpose
High input
resistance
Voltage Low output
Amplifier resistance
Series-
Shunt
Voltage
Voltage

Transimpedance Low input
Amplifier resistance
Shunt- Low output
Shunt resistance
Current
Voltage
Low input
Current resistance
Amplifier High
Shunt- output
Series resistance
Current
Current
Transconductan High input

ce resistance
Amplifier High
Series- output
Series resistance
Voltage
Current
For all feedback configurations:
Blackmans
RX = resistance of the closed-loop feedback amplifier
Theorem
looking into one of its ports (terminal pair), X = in,
out, etc.
RXD = resistance looking into same terminal pair

Input and output with feedback loop disabled. (set Ao = 0,
resistances occur effectively remove amplifier) TSC = loop-gain with
between one of short-circuit applied across terminals TOC = loop
amplifier terminals gain with port open-circuited.
and ground.

Series-Shunt Feedback Model
The non-inverting amplifier has been redrawn to clearly show the series
and shunt connections between the amplifier and feedback network.
So there is series feedback at the input because the amplifier input

and feedback network voltages are in series.
So amplifier output and feedback network are connected in parallel (same

voltage) Closed-Loop Gain Calculation
T=
loop gain
To find T, disable feedback network by setting the value of in source
( now accounts for non

- ideal resistance effects)
Input Resistance Calculations

Use Blackmans Theorem
.
Disable feedback loop (remove amplifier).
TSC found by shorting input terminals, circuit becomes

identical to one used to find loop gain T previously,
SC = T T
For TOC , no current can flow through

id,vid
R = 0 and OC
T = 0.
Output Resistance Calculations
(A0) to find
Disable feedback loopo =
Connecting output terminal to ground shorts the

feedback loop soSCT= 0.
Summary
Expressions are identical to those shown in summary table earlier, but

now use the input and output resistances and loop gain of the amplifier
including effects of all resistances in circuit.
Example
Find:
Closed- loop gain

Closed Loop Input resistance
Closed loop Output resistance
4
Open loop gain = 80dB = 10
Input resistance = 25
k
Output resistance = 1k

Cir cuit for finding input resistance:
Resistance between input and

ground:
||( 2 )
36
Circuit for finding output resistance:
Resistance between output and

ground:
||( 2 ( )| | )
99
Find Thevenin Equivalent1of

, R2R, Ro and output:
Assume idv = 1 in source and solve for

actual vid:

Shunt- Shunt Feedback Model
Input:

So amp and feedback network are in

parallel (equal voltage)
Output:

Also parallel feedback at output
Input Resistance Calculations

To find loop-gain T, disable feedback loop by setting vid = 1V in dependent
source, independent source ii is set to zero (open circuit), actual vid at
input is calculated.
To find , disable feedback, look through above circled node:
When input terminals are shorted for TSC, inverting input is grounded, Tsc =
0.
When input terminals are opened, circuit becomes same as one used
above to find loop gain T.

Output Resistance Calculations
Series- Series Feedback Model
Input:

So amp and feedback network are in

series (add voltages)
Output:

Also series feedback at output
Closed- Loop GainCalculation
Input Resistance Calculation
When input terminals are shorted,

i is cut
v
out, circuit becomes identical to one used to
find T above,SCT= T
When terminals opened, no current through
Rid , vid = 0, TOC = 0.

Output Resistance Calculation
Shorting output terminal to ground creates

circuit same as one used to findSCT,
=T T.
If output is open circuited, no current flows,
TOC = 0.
Summary
Shunt-Series Feedback Model
Input:

So parallel (shunt) feedbackinput

at
Output:

Series feedback at output
Closed- Loop Gain Calculation

Input Resistance Calculation
TSC = 0, TOC = T
Output Resistance Calculation
TSC = T, TOC = 0
Summary
Successive Voltage and Current Injection

Method used to find loop gain without opening the feedback loop.
In some cases, loop cannot be opened to measure gain because

closed loop is required to maintain correct DC operating point.
Method:
1. Voltage source vx inserted into loop at arbitrary point P, two voltages

on either side are measured, and Tv is calculated

RA and RB are the resistances looking to the
left and right respectively from the test
source vx. They vary with each situation
depending on op-amp configuration and
chosen point P.
In case shown above:
2. Voltage source removed, a current source ix injected into same point

P (from ground), find two currents produced.
Combine two equations:

Distortion Reduction through use of Feedback
Voltage Transfer Characteristic of amplifier

Ideal (+/- 10V rails) Realistic (+/- 15V rails)
Nonlinearities in realistic op-amp operation introduce distortion into the

output.
Feedback can be used to significantly reduce distortion

For non-inverting amplifier of input , output will have both
desired output frequency as well as unwanted signal components at
other frequencies due to distortion.
-second harmonic, third

harmonic, etc
This distortion behaviour can be modelled by inserting an error voltage
source in series with

op amp output.
Therefore distortion is reduced by

factor which can be very large
depending on feedback arrangement.
Total Harmonic Distortion (THD):
22 32 42

%

DC Error Sources and Output Range Limitations
Input-Offset Voltage
When the inputs of an amplifier are both zero, the output is not truly zero,
but rests at some nonzero DC voltage offset level.
Due to mismatches in transistors in the input stage of the Op-amp, a

small dc voltage seems to have been applied to the input, equal to:
Vos varies randomly from amplifier to amplifier.

Offset-Voltage Adjustment
A variable resistor can be used to manually
adjust the offset voltage of an IC op-amp to
zero.
Input-Bias and Offset Currents

For the transistors in an Op-amp to operate,
a small but non-zero DC bias current must
be supplied to each input terminal (ideally infinite resistance so no

current though device). Can be modelled by similar but not identical
current sources connected to inputs:
The input bias currents produce an undesired

voltage at the amplifier output.
IB1 does not affect circuit, shorted out by

other connection to ground.
Inverting input is virtual ground, current
through 1R is zero. Therefore B2I is supplied
by amplifier output through
2. R
This output voltage error can be reduced by placing a bias current
compensation resistor RB in series with non-inverting input (previously
grounded).
If set R
B to parallel combination 1ofand
R R2:
Output Voltage and Current Limits

For many real op-amps, output voltage range is limited to less than the
power supply range.
Commercial op-amps also contain circuits that restrict the magnitude

of the current in the output terminal to protect amplifier from
accidental short circuit by limiting power dissipation.

Common-Mode Rejection and Input Resistance
Amplifier realistically responds to the signal that is common to both inputs
(not just difference), and so output contains these components as well as
the scaled replica of the input voltage Common-mode input voltage:
An ideal op-amp would only amplify the differential-mode input

voltage (Vid) and reject the common-mode input signal, so Acm = 0.
Equation can be rewritten to factor out A:
CMRR common mode rejection ratio. Higher value = better.

Common-Mode Input Resistance
Rid = resistance presented to a purely differential input voltage vid
More resistors need to be added to model the common-mode input
resistance of the amplifier.

When purely common - mode signalicvis
applied (v
id =0) , resistance presented to
source is parallel combination of the two
2 resistors.
Ric = equivalent resistance presented to
common- mode source ( common mode
input resistance)
.
Purely differential
- mode input:

Power Supply Rejection Ratio
PSRR indicates how the offset voltage changes in response to a change in
the power supply voltages.
Frequency Response and Bandwidth of Op-Amps

Capacitances within real-world electronic components act to limit the
bandwidth of the opamp.
Most general purpose amplifiers are low-pass designed to have high

gain at DC and a single-pole frequency response described by:
A0 = DC Open loop gain

= Open loop bandwidth of op-amp (freq at which gain is 3 dB lower than
A0)
Unity gain frequency (freq. at which

Open- loop frequency response:
For , gain is constant at DC value

0. A
At
Non- Inverting Amplifier Frequency Response
Substitute variable expression for OL gain A:
Dividing by something gives:
Similar to equation for open

- loop response.
upper cutoff frequency, closed .
- loop equivalent of
At low frequencies, the gain is set by the feedback

At high frequencies, follows gain of amplifier
( )
Loop gain:
Gain- Bandwidth Product (GBW)

Inverting Amplifier Frequency Response
At low frequencies,
v A is set by resistor ratio, identical
For
bandwidth expression as-noninverting amp.
Non- inverting amplifier will have slightly greater bandwid

because of difference in relation between
Feedback to Control Frequency Response
Amplifier with cut-off frequencies and midband gain A0:
Substitute frequency-dependent voltage gain expression for A:

Slew Rate and Full Power Bandwidth
Nodes of op-amp cant respond instantly to voltage change at input.
Slew-Rate = max rate of change of voltage at output
At low frequencies, v A is set by resistor

ratio, identical bandwidth expression as
non- inverting amp.
Non- inverting amplifier will have slightly
greater bandwidth because of differenc
in relation between
Open Loop Parameters Closed-loop Parameters

Operational Amplifier Applications
Cascaded Amplifiers
Joined in series to meet design specifications not achievable using a single
op-amp.
Can be represented using the two-port model:
Ideally, if Rout = 0 for each op-amp,
Instrumentation Amplifier
Consists of 3 amplifiers:
2 non-inverting amplifiers with outputs becoming

the inputs of: A difference amplifier
Provides higher gain and lower input resistance.

Switched-Capacitor Circuits
Eliminate resistors in filters by replacing them with capacitors and
switches.
Switches controlled by clock time function
Switched-Capacitor Integrator
(inverting)
Phase 1 Phase 2

Input voltage is sampled (stored in Output changes to reflect sampled
C1) voltage in phase 1 (Q1 transferred
to C2 each clock period T)
Output constant
When clock is positive, charge

stored in C1:
Change in charge stored on C2:
V1 = voltage stored on C1 at end of

sampling interval
After n clock cycles:
SC circuits used instead of filters containing resistors, high resistance

resistors are physically large and not ideal for ICs.
Charge through resistor R over time T: Equate to charge
stored in capacitor:
Non-inverting SC Integrator
Digital to Analogue Converters (DACs)

An input n-bit binary word is combined with the DC reference
voltage VREF to produce output of DAC.

Least significant bit
Full scale voltage

VFS or currentIFS
K or G often set to 1
VOS is offset voltage value at output when input = 0 (usually set to 0)

Minimum voltage change possible = resolution = when LSB (last bit in
word) changes from 0 to 1.
Maximum output is always 1 LSB smaller than VFS
DAC Errors
Gain error
represented by deviation in slope
Offset error
output of DAC for input of 0
Can be circuit mismatches which cause output to no
longer be perfectly linear.

( Integral) Linearity error difference between ideal
output and actual output (in termsLSB
of) V
Overall error for DAC = magnitude of largest err
Good = <0.5 LSB

Differential linearity error
is difference between
actual step size and step size of 1. V
LSB
Non- monotonic when one ou tput value is lower

than the last
Always has differential linearity error > 1 L

001: ILE =- 0.2 (VLSB) , DLE =- 0.2 (VLSB)
010: ILE = 0(VLSB) , DLE = +0.2
(VLSB)
100: ILE =+0.5
(VLSB) , DLE = +1.0
(VLSB)
DAC Circuits
Weighted
- Resistor DAC
Resistors are used to weight
the binary
V , bn has 2-n
inputs (2R for1 b means REF
weighting as required)
Errors occur when resistor ratios are not
perfectly maintained.
Difficult to maintain ratios over

very wide range of resistor values
R-2R Ladder is alternative design which avoids problem of wide range of

resistor values.
Contribution of each bit is reduced

by factor of 2 going from MSB to
LSB.
However, currents in resistor
network of these two designs
change as input changes (error)
Inverted R-2R Ladder - used to avoid problem of input-dependent

current in resistor network.

Inherently Monotonic DAC
DAC consisting of long resistor string which
forms voltage divider between
REF V
and
ground.
Output cannot be non

- monotonic with
this configuration
Switched Capacitor DACs

Weighted
- Capacitor DAC:
C-2 C Ladder DAC

:

Analogue to Digital Conversion

Electrical signal Digital data (binary)
Output is -n bit number which is a binary fraction
representing ratio between unknown input voltage
and converters full
- scale voltageFS.
V
Because of the step- like progression, the output first
underestimates the input voltage then overestimates
it.
This error called quantization error

This error means that for a given output code, we
only know that the input voltage lies somewhere
Q uantization error
Example
8-bit ADC with VFS = 5V.
1. Binary output for input of 1.2V?

Voltage Fraction = 1.2/5 = 0.24. Max 8-bit binary is 255, binary fraction:
2. 1LSB Voltage range?

256 steps for 8-bit so 5/256 = 0.0195 = 19.5mV
ADC Errors

Q uantization error of previous graph.
LSB voltage range for

- bitn ADC:

2
Non- ideal Code transition Integral Linearity Error
2 ) (
Ideally, each code step has width of 1 LSB of converter
Differential linearity error
difference between actual code step width and 1 LSB.
Missing code can occur if DLE is above 1

Integral linearity error
Deviation of code transition positions from ideal
All these errors are temperature dependent
.
AD Conversion Techniques General simple model:
Counting Converter
Input voltage Vs is an unknown

fraction of
VFS of ADC.
This Vs is compared to a reference
voltage which starts low
A clock pulse and counter gradually increases the value of the
reference voltage using a DAC
Eventually the reference voltage will exceed the analogue input
voltage and trigger the comparator
This stops the binary counter, which at that point holds the digital
value (binary fraction) corresponding to input analogue voltage.
Digital value
of counter
after
comparator
switches
( Corresponds
to smallest
DAC voltage
that is larger
than
unknown
input)
Pulse is used to reset counter output to zero and begin conversion
Length of conversion cycle (time taken to complete conversion) is

proportional to Vs. Max conversion time occurs for Vs = VFS,
equal to 2n clock periods
Successive Approximation ADC

Much faster than counter ADC, uses logic to converge on value closest to
input voltage.
Requires n clock periods for n-bit conversion

Star ts at MSB or 2 6
( about half way
along voltage range spectrum)
Example:
For 3 bit ADC with
FS=V 7V and 3.2V input
:
1 00 4 /7 > 3.2/7 so clear bit0to
Next lower bit:
010 2 /7 < 3.2/7 so keep bit1at
Next lower bit:
011 3 /7 < 3.2/7 so keep bit1at
All bits checked, output is 011
Slowly varying input is

acceptable if it does not
change by more than:

5
2
During conversion
time.

So sinusoidal input signal
with App = VFS must have
frequency less than:
Single Slope ADC

Slope voltage generated using
integrator + constant voltage.
Max conversion timenT=2
C
when V =
s FSV .
After N clock pulses (counter
value), V>V
S and output given
by:
Voltage slope depends on integrator which

depends on RC product, which is influenced by
Finn Andersen, 2012variation or aging. 2
temperature

K = slope gradient2 =


Input voltage itself is integrated over known
Dual Slope ADC
time period T
1.
2
Known reference voltage is then integrated
and inverted over variable time
2 until
T output
reaches 0 again.
2
Two expressions for maximum output voltage
are then equated to find
x V
This setup eliminates the effect

of absolute values of R and C on
operation.
Digital output represents average

value of input during first
integration phase, so input can
change during cycle and output
value can still be valid.
Is a widely used converter because of excellent differential and integral

linearity.
Parallel/Flash ADC
Operate very quickly rates as high as 109 conversions/second.
comparators and reference voltages (2n resistors)
are needed, cost of implementing high resolution converters grows
rapidly.

Delta-Sigma ADCs
Widely used, require minimum precision
components, easily implemented in switched
capacitor form.
The internal ADC samples the

integrator output at much higher
rate oversampled ADC.
Input is integrated, and based on
result, is increased or decreased
by summing withREF +Vor VREFto
change the integrator input and
bring result toward zero.
Switch will spend N clock periods
connected to- VREF and M- N clock
periods connected toREF.
+V
Larger observation in
terval (M) =
greater resolution
Oscillators
Feedback circuits used for signal generation.
For sinusoidal oscillator, want poles of closed-loop amplifier to be

located at frequency . For positive feedback system:

For sinusoidal oscillations, denominator must be zero for a particular
frequency
In order for this condition to be satisfied:

Phase of
Circuits Using Positive Feedback

Comparators provide output saturated at Vcc or VEE depending on
whether input is above or below a reference voltage.
However for a noisy signal, there can be multiple transitions as

the input signal crosses the reference level:

Schmitt Trigger is used to solve this problem.
Reference voltage changes depending on output.

For input voltage increasing from below
REF , V
output
= Vcc and .
When input crossesREF V , output =-VEE, VREF drops to

so that it cant be easily crossed again by
noisy signal.
No ise must be greater than for

trigger to respond.
Astable Multivibrator
Uses combination of positive and negative feedback to generate
rectangular output

waveform.
If

V- increases towardsCCV
- reaches (
When V capacitor charging) the
comparator output switches state and:

V- decreases towards
VEE
When V
- drops belowVEE , the output switches again
For symmetrical power supply voltages, output is a square wave with

period T:
Can be used to generate other waveforms:
Monostable Multivibrator
Generates single pulse of set duration after a trigger signal.

Rests in stable state of

If trigger is less than voltage at node 2:
, D1 is cut off.
Capacitor voltage 7
Node 3 > Node 2 so output
When triggered with positive vT, Node 2 > Node 3 so

Node 2 = D1 cuts off
Capacitor charges from
until it reaches and again Node 3 > Node 2 so output
Circuit should not be retriggered until capacitor returns to VD (after Tr)
Solid State Electronics

Silicon has 4 electrons in outer shell and forms a
single- crystal material by covalent bonding of
each silicon atom with 4 others.
At very low temperatures, electrons reside in
covalent bonds, none free for conduction

Density of free electrons intrinsic
is carrier behaves as insulator
.
density , determined by material properties
At higher temperature, thermal energy added,
and temperature:
some bonds break, some electrons freed for
conduction.
3

When covalent bond is broken and electron is freed, it forms another
charge carrier by leaving behind a vacancy.
Electron with charge q and vacancy with charge +q

Other electrons can then fill this vacancy, creating another vacancy,
effectively allowing vacancy to move through crystal.
Moving vacancy behaves as moving particle with charge +q, called
hole.
Drift Currents and Mobility

Charged particles move or drift in response to an electric field, resulting
current is drift current.
Mobility
At low fields, carrier drift velocity (v) is proportional to electric field E,
with constant mobility .
Positive charges drift in same direction as electric field, negative

charges opposite
Electrons can move freely about crystal but holes can only move through
covalent bond structure, so electron mobility is higher.

Velocity Saturation
Velocity of carriers cannot increase
indefinitely; the mobility
relationship is onlyvalid for fields
below 5000V/cm.
As field increases, velocity of

holes and electrons begins to
saturate (reach maximum).
Places upper limit on
frequency response of solid
state devices
Resistivity of Intrinsic Silicon

Drift current densities:
= electrical conductivity
Impurities in Semiconductors
Impurities are added to semiconductor materials, called doping, to create
a doped semiconductor.
Doping changes the

resistivity For silicon:
Donor Impurities Acceptor Impurities
From column 5 of periodic table (1 From column 3 of table, have 1 less
more valence electron than silicon). electron than silicon.
4/5 electrons fill covalent Vacancy exists in bond
bond structure, extra electron structure
is easily freed for conduction Easy for nearby electrons to
Atom becomes ionized with move into vacancy
charge +q, represents Creates hole with +q charge
immobile fixed charge in that can move through lattice
lattice Impurity atom becomes
ionized with charge q and is
immobile.

Electron and Hole Concentrations in Doped Semiconductors
Depending on type of impurity added, the electron and hole
concentrations are no longer equal.
If donor added, n > p, material is n-type

If acceptor added, p > n, material is p-type
Carrier with larger population is majority carrier Semiconductor must
remain charge neutral:
n-Type Material (ND>NA)

Substituting above two equations for p gives:
n-Type Material (NA>ND)

Mobility and Resistivity in Doped Semiconductors
Impurities reduce the mobility of carriers in the material.
Majority carrier concentration controls the conductivity of the material:
Diffusion Current
Semiconductor doping is often not uniform, there will be gradients in the
electron and hole concentrations.
These gradients cause a second

current flow mechanism diffusion.
Free carriers move (diffuse) from
regions of high concentration to
regions of low concentration.
Diffusion current densities are
proportional to negative carrier gradient:
DP and DN are the hole and electron diffusivities, related to mobility by:

= thermal

voltage,
aprox. 0.025V at room temperature.
Total Current
Currents in semiconductor have both drift and diffusion components.
Add both together to find total electron and hole current densities:
Can be combined with Gauss Law to analyse behaviour of

semiconductors.
Energy Band Model

Quantum mechanics predicts that the highly regular crystalline structure
of a semiconductor produces periodic distinct ranges of allowed and
disallowed energy states for electrons around atoms in the crystal.
Ev = highest possible energy for valence electron

EC = lowest available energy in conduction band
Bands shown as continuums but actually closely spaced discrete
energy levels
Electrons not permitted to assume values of energy between Ec and
Ev

Energy Band Model for Doped
Semiconductor
If donor atoms are added to a semiconductor, they introduce new
localized energy levels within the bandgap at a donor energy level ED
near conduction band edge.
Takes very little energy to promote extra electrons from donor

sites into conduction band
At room temperature, essentially all available donor electrons are
free for conduction (elevated to conduction band)
When acceptor atoms are added, they introduce energy levels within the
bandgap at the acceptor energy level EA near the valence band edge.
Takes very little energy to promote electrons from valence band

into holes at acceptor energy levels.
A compensated semiconductor contains both acceptor and donor
impurities. Figure 2.15 shows compensated semiconductor with more
donor atoms than acceptors.
Electrons seek the lowest energy states available, fall from donor
sites, filling acceptor sites.
Remaining free electron population (ones which can elevate to
conduction band) is:
Integrated Circuit Fabrication

Integrated pn diode top view: Side
view:

Solid-State Diodes
Diode is formed by joining an n-type
semiconductor with a p-type semiconductor.
Creates an interface between the n and

p regions called the pn junction.
The concentration gradient in the junction causes diffusion currents:
Particles diffuse from regions of high concentration to low concentration

As mobile holes move from p-type material they leave behind immobile
negatively charged acceptor atoms, while mobile electrons from n-type
material leave behind immobile positively charged (ionized) donor
atoms causes drift current.

This space chargeregion (SCR)causes:
Varying charge densities

An electric field
Varyign electrostatic potential
As shown in graphs over page. Overall
diode must be charge neutral so:
Electric field is proportionalintegral

to
of space charge densityso will be zero
in the neutral regions outside the
depletion region.
Electrostatic potential is integral of electric field E

Shows that a junction potential exists across the pn junction
space charge region
VT = thermal voltage

Total width of depletion region can be calculated in terms of junction

potential:
Electric field E points in direction that positive carrier will move. E is

negative at junction so:
Electrons drift toward positive x direction

Holes drift in negative x direction
Drift direction is opposite to diffusion direction of same carrier
Hole/electron diffusion is balanced by hole/electron drift
When a voltage is applied to the diode, the potential difference barrier

is modified and the delicate balances in above equations are
disturbed, resulting in current in diode terminals.
I-V Characteristics of a Diode

Behaves as a valve permits current flow in one direction, prevents
movement in the other.
Neutral regions have low resistance to

current, essentially all applied voltage
vD is dropped across
SCR.

Negative voltageP(v< vn) increases
potential barrier, results in very small
current.
Positive voltageP(v
> vn) reduces
potential barrier, current easily crosses
junction.
Belowturn- on voltage, diode is

essentially non
- conducting.
For negative voltages, current isnt
exactly 0 but approaches a very small
negative limiting avlue called reverse
saturation current
Is.
Diode Biasing
Reverse When . Effectively
Bias nonconductive, only small reverse
leakage current.
Exponential component negligible.
Zero Bias I-V characteristic passes through

origin,

Forward When . Highly
Bias conductive, -1 term becomes
negligible.
Diode Reverse Bias

Applied reverse voltage adds to the built-in potential of the junction.
Causes changes in electric field and depletion layer width

characteristics
Reverse Breakdown
If high enough reverse voltage is
applied, diode will enter
breakdown region.
Voltage depends on doping

level of more lightly doped
side of junction
More doping smaller Vz
Two different breakdown
mechanisms:
Avalanche Breakdown
Occur in diodes with breakdown
voltages >
5.6 V.
Reverse bias
depletion later width increases
electric field increases
Free carriers accelerated
Collide with fixed atoms
Break covalent bonds
More carriers created and chain
reaction can ensue. Zener Breakdown
Occurs only in heavily doped, low breakdown voltage diodes.
Results in very narrow depletion-region width

Reverse bias causes carriers to tunnel directly between conduction
and valence bands
Causes rapidly increasing reverse current in diode
Zener diodes designed to be operated in reverse breakdown
Schottky Barrier Diode

In a p+n junction diode, the p-side is highly doped and a conductor, and
can be replaced with a metallic layer.
Turns on at much lower voltage than pn-junction counterpart
Diode Circuit Analysis

Common objective is to find quiescent operating point (Q-Point) or bias
point
Consist of ID and VD required for operation
Equation represents a constraint

placed on diode operating point by the
circuit elements.
Diode I-V characteristic graph also
represents allowed values of I and V by
diode itself.
Simultaneous solution defines Q-point.

Load- Line Analysis
Use when- i v characteristic ofiode

d is
given in graphical form.
Mathematical Model Analysis

Use diode equation and substitute ID into previous equation.
Resulting expression is a transcendental equation that cannot be

readily solved, so trial and error can be used by initially guessing a value
of VD and see if it satisfies.
Constant Voltage Drop Model
Piecewise linear approximations can be applied to the diode i-v
characteristic.
On is modelled by constant voltage to account for voltage drop

Off modelled by open circuit
Ideal diode does not have the
6 7
voltage drop Forward bias:
( 94 , 6 )
Reverse Bias:
( , )

Multiple Diode Circuits 3 diodes means
3
2 = 8 possible states for the circuit
!
First assume all diodes are on:
So reiterate again with

2 D modelled as being off
Diodes in Reverse Breakdown

Reverse breakdown voltage is nearly independent of current, can be used
as a voltage regulator or voltage reference.
In below circuit, applied voltage is reverse polarised and above the

Zener voltage rating so diode will operate in reverse bias
Choose twoDV and corresponding DI

values and plot on
- i v characteristic graph
When in reverse breakdown, current

flowing in reverse direction, diode
current ID is negative. Zener current
equal to negative diode current:
Piecewise Linear Model

Diode can be modelled as below (opposing voltage source VZ and resistor),
only valid for breakdown region operation.

When zI > 0, voltage across load resistor will be kept at
approximatelyzV
Voltage Regulation

Using simple Zener model with

z = 0,
R
Therefore regulation takes place in this circuit.

There is a corresponding minimum load resistance
required for diode to act as regulator.
Having ZR> 0 will increase voltage across
L R
Line and Load Regulation
Line Regulation Load Regulation
Characterizes how sensitive the Characterizes how sensitive the
output output voltage is to changes in load
(load) voltage is to input voltage current withdrawn from regulator.
changes. Equal to thevenin equivalence
looking into regulator from load
terminals.
Half-Wave Rectifier Circuits

Rectifier used to convert AC voltage to pulsating DC voltage, then filter
added to eliminate AC components and produce nearly constant DC
voltage.

Voltage magnitudes in output are actually Von lower than input during
conduction interval:
Rectifier Filter Capacitor

Unfiltered output of half-wave rectifier shown above is not suitable for
electronic devices which require constant DC supply. Filter capacitor is
added in place of resistor:
At peak of first input waveform, current through diode tries to reverse

direction because:
So diode cuts off, capacitor is disconnected and voltage remains
constant because there is no path to discharge.
When load is added, capacitor can discharge during time when diode is
off:
Diode only conducts for conduction interval , with angular equivalent

conduction angle
.
This causes ripple voltage

Vr.
Small ripple voltage is preferred
Diode Current
Pulses of current through the diode during time are required to
replenish the charge in the capacitor.

First a large surge current is required to initially charge the capacitor,
modelled by:
Each subsequent current pulse can be modelled as a triangle of

height IP and width Equating charge through diode =
charge lost by capacitor:

Series resistance in practical circuits causes peak surge current to be
reduced.
Also resistance increases capacitor time constant, if above input

period, may take multiple cycles to charge capacitor to steady state
voltage.
Peak-Inverse-Voltage (PIV) Rating
When diode is off, reverse bias = . can get as low as so diode
breakdown voltage must be greater than:
Diode Power Dissipation

Power dissipation due to diode on- Power dissipation due to diode
voltage: internal resistance RS:

Full-Wave Rectifier Circuits
Similar to half-wave rectifiers, but:
Reduce capacitor discharge time by half

Therefore only half filter capacitance is required to achieve given
ripple voltage
Centre-tapped transformer used to generate two voltages with equal
amplitudes but 180 out of phase.
Two diodes form a pair of alternating half-wave rectifiers

Load receives two current pulses per cycle
Capacitor discharge time reduced to less than T/2

Full-Wave Bridge Rectification
Centre-tapped transformer can be replaced by two additional diodes.
Rectifier Summary
Diode Dynamic Switching Behaviour

Due to capacitance in diode, diode voltage does not change
instantaneously.
When input becomes negative, diode current rapidly reverse direction, but
diode remains forward biased by charge stored in the diode capacitance.

Photo Diodes, Solar Cells, LEDs
If the diode depletion region is illuminated with light of sufficient
frequency:
Photons provide enough energy to cause electrons to jump

semiconductor bandgap
Creates electron-hole pairs
Incident photons must have an energy that exceeds bandgap of
semiconductor:
Incident optical signal can be converted to an electrical signal voltage:
Solar Cell Operation:

must be positive
to supply power to
external circuit.
Attempt to make cell
operate near pointmax
P
LEDs
When a hole and electron recombine, energy equal to the semiconductor
bandgap can be released in form of photon, generating light.
Materials other than silicon are used to have more efficient optical
emission process.

Bipolar Junction Transistors
Physica l Structure
Consist of three alternating layers
of n and -p type semiconductor
material.
Form the emitter, baseand
collector of the transistor.
Can be eithernpn or pnp
Base region is very thin, causes

coupling
between the two diodes.
Majority of current enters collector,
crosses base , exits fromemitter.
Small amount enters base and exits from
emitter.
Collector current is determined by base
current.
Transport Model for npn Transistor

Reverse Bias Condition
Collector and Emitter switch roles

Forward
common- Reverse
emitter current gain. Forward common-emitter current gain.
common-base current gain Reverse common-base current
gain
Transconductance 4 ,
Complete Transport Model Equations
Apply to arbitrary bias condition:
IS = T ransistor saturation
current
P roportional to cross
sectional area of
base region
Forward Characteristics
(VB>VE, VB VC):
Reverse Characteristics
(VB > VC, VB VE):
The pnp Transistor

Formed by interchanging n- and p-type regions.
Operates opposite to NPN current into emitter and out of collector

and base
NPN PNP

Forward Bias:
Forward Bias:
Reverse Bias:
Reverse Bias:
Equivalent Circuit Representations
The i-v Characteristics of BJT

Common-emitter output characteristics for npn transistor:

WhenBI = 0, transistor is non
-
conducting orcut- off.
In forward and reverse active region,
collector current is independent
CEof
. v
Forward activeregion when
Saturation region
when
and
Small voltage between C and E.

Same for pnp transistor but horizontal
axis is EC
V.
Common
- Base Output Characteristics
for
Forward active
For , collector current grows

exponentially in negative direction as
base- collector diode begins to
conduct.
Operating Regions

Transport Model Simplifications
Cutoff Region
Slight leakage current occurs which can usually be

neglected and transistor effectively acts ad open
switch.
Forward Active Region
(simpli
fied)
Collector current can be modelled as a voltage-controlled current
source controlled by base-emitter voltage, independent of collector
voltage.
Valid ONLY while in forward

- active:
Reverse Active Region
Early Effect and Voltage

In real transistor, there is slight positive
slope to characteristics instead of iC
reaching constant value as shown in i-v
characteristic diagram before.
Extrapolates back to Early voltage VA:
Saturation Region
Both junctions forward biased:
Typically operates with small voltage between collector and emitter,

called saturation
voltage

Fabricated Diode
Diode can be fabricated with a BJT by connecting base and
collector:
Non- Ideal BJT Behaviour

Emitter- base and collector
-b ase diodes have reverse
breakdown voltages
Capacitances associated with each diode, limits high frequency
response.
Minority Carrier Transport in Base
Region
BJT current mainly due to diffusion of minority carriers (electrons for npn,
holes for pnp) across base region
Base current consists of:
Hole injection back into emitter

Hole injection back into collector
Small additional current to replenish holes lost to recombination in
base
Practical Bias Circuits for BJT

Q-Point represents initial operating region of a transistor, and is different
for each required application of the transistor. Q-point defined in form

Logic inverter Amplifier
When vBE is small, transistor is cut Q-point located in forward-active

off, output is high (5v). region where high voltage/current
gain can be achieved.
When vBE > 0.7v, transistor
conducts, output drops (logic low) DC bias VBE is applied to establish Q-
point, then small AC signal vbe can
be amplified.
Amplified replica of input voltage
appears at collector.
Cut-off Forward active Saturation

Four Resistor Bias Network
Because of BJT exponential I-V relationship and
dependence on temperature, constant VBE form
of biasing is not practical. Instead, four-resistor
bias network can be used.
In order to solve, the power supply is split

into two equal voltages, Thevenin
equivalent of base-bias network is found

Design Objectives
Thevenin resistance REQ designed to be small enough to neglect voltage
drop of base current flowing through it.
Therefore IC and IE are set by VEQ, VBE and RE

VEQ designed to be large enough so that small variations in assumed
value of VBE will not greatly affect IE.
Tolerances in Bias Circuits

Components used to construct the bias circuit realistically have tolerances.
Values of circuit components also change with temperature and as

circuit ages
Worst-Cast Analysis
Values of components are pushed to extremes to determine worst possible
range of Q-point values.
To find max valueCof, Iuse V
EQ at max extreme and
ERat
min extreme.
To make EQ
V max, maximize
CCVand R1 and minimize2.R

Monte Carlo Analysis
Since it unlikely that all components will reach their corresponding
extremes at the same time, the worst case analysis will overestimate
the extremes of circuit behaviour.
Randomly selected version of a given circuit consisting of

components with random values of their possible tolerance range is
taken.
Circuit analysed, repeated for many test cases
Creates error distribution plot
Field- Effect Transistors Used to induce charge at interface

MOS Capacitor between the semiconductor and oxide.
At heart of MOSFET is
MOS capacitor. Top electrode is low
- resistivity
material, typically aluminium
called
gate (G)
Thin ins ulating layer, typically silicon
dioxide
Semiconductor region acts as second
electrode with substantial resistivity
and limited supply of holes and
electrons.
This enables the semiconductor to be depleted of carriers so the
capacitance of this structure is a nonlinear function of voltage.
There different operating regions:
VTN = threshold voltage, voltage required to just begin formation of

inversion layer
Higher hole density than
originally in the p-type
Accumulat substrate
ion
As gate voltage increased,

holes are repelled until
density is reduced below
Depletion
original substrate doping
level region is depleted
of free carriers.

As voltage increases
further, electrons are
attracted to surface, until
electron density exceeds
Inversion hole density. Surface has
inverted from p-type
polarity to an n-type
inversion layer directly
underneath top plate.
Different operation regions change effective separation of capacitor

plates. Total capacitance can be modelled as series combination of
fixed oxide capacitance and voltage dependent depletion-layer
capacitance .

At voltages well below threshold, capacitance is
high and determined almost entirelyoxide
by
thickness
.
In depletion region, effective separation of
capacitor plates increases, capacitance decreases.
When V
G > VTN , capacitance again determined by
oxide thickness an d rapidly increases.
The NMOS Transistor
Formed by adding two heavily doped n-type regions to the MOS
capacitor, resulting in structure below:

The n- type regions source
( ( S) anddrain( D))
supply electrons that can readily move unde
the gate and terminals that can be used to
apply a voltage and cause a current in the
channel region of the transistor.
Provide a supply of carriers so the

inversion layer can rapidly form in
response to gate voltage
Source = electron source (conventional
current opposite direction)
Voltages which are positive during
normal
Substrate represents a fourth terminal called
operation of MOSFET:
body terminal (B)

So: ,
This keeps pn junctions between source and drain and substrate

reverse biased
Provides isolation between junctions and substrate, and between
adjacent MOSFETs For all other terminals being grounded:
When VG << VTN, back to back pn junctions exist between source and
drain, only small leakage current flows between them
When VG < VTN, depletion region forms beneath gate, merges with
depletion regions of source and drain. Region is devoid of free
carriers, still no current between source and drain
When VG > VTN, electrons flow from source and drain to form
inversion layer that connects source region to drain.
If positive voltage then applied between drain and source (vD > vS),
electrons in inversion layer will drift, creating current in terminals.
Conventional current enters drain, travels along channel, exits from

source.
Gate terminal is insulated from channel, iG = 0
Drain-base and source-base junctions must be reversed biased so
assume iB = 0 So:

Triode Region Characteristics
Triode region is when the resistive channel Electron charge per unit length at any
directly connects source and drain point in channel:
S ince Gi =0 and Bi = 0:

( )
Where v(x) is v oltage at any point x from
the source.
At source, v(x) = 0
At drain, v(x) =DSv
Electron drift current:
Integrating from 0 to L yields:
Average charge per unit length Average channel voltage Drift velocity
On Resistance
For small drain-source voltages , FET behaves like a
variable resistor

between drain and source.
Virtual resistor value controlled by

- gate
source voltage
Calledon- resistance
Symbol for when

SBv= 0
Relationship is not perfectly linear for lower values of vGS and higher values
of vDS.
Saturation of the i-v Characteristics
As drain-source voltage in above situation in increased, the current does
not continue to increase but saturates at a constant max value.
While , MOSFET operates in triode region with constant

channel.
When , channel width decreases to just disappear at the
drain
When , channel width decreased further

When electrons coming from
source reach pinch
- off point, they
are injected into the depletion
region and the electric field there
sweeps them onto the drain.
Once channel has reached

pinch- off, voltage drop
across channel is a constant
so drain current
becomes constant.
Region referred to as saturation region or pinch-off region.

Mathematical Model in Saturation
(Pinch-off) Region For saturation region
condition:
The square-law relationship explains the spreading out of the curves

for drain-source current depending on vGS.
Graph forGS
v = 3v:
Triode region equation:
Models inverted parabola for:

( )
Maximum drain voltage must not exceed
Zener breakdown voltage of the drain
-
substrate pn junction diode.

Transconductance
Relates change in drain current to change in gate-source voltage. For
saturation region:
Higher transconductance = more gain from amplifier that utilizes
the transistor.
Channel
- Length Modulation Instead of being completely linear,-v-thecurve
i in
saturation region has a small posit
ive slope since the L in:
Decreases asDSv increases, so current increases.
Transfer Characteristics
Transfer Characteristic graphical format plots drain current vs gate-
source voltage for fixed drain-source voltage. Below shows two different
NMOS transistors in saturation region:
No current flows when

GS <
v VTN.
After vGS > VTN , exponential relationship:

Possible to fabricate NMOS transistors with called depletion-
mode MOSFETs. Ntype channel is implanted to connected source and
drain, negative voltage must be applied to deplete the region and
eliminate current path.
Body/Substrate Effect
With vSB = 0, MOSFET behaves as a 3-terminal device. Nonzero value of vSB
changes the
value of the threshold voltage.
Mathematical Model Summary
PMOS Transistors
Built by using p-type source and drain regions and n-type as substrate.
Behaviour is essentially the same but voltage and current polarities

are reversed Gate-source voltage must be more negative than
threshold voltage VTP.

PMOS Transistor Mathematical Model Summary

Enhancement mode PMOS:
Depletion
- mode PMOS:
Charge carriers in channel are holes, current proportional to hole

mobility.
Hole mobility typically 40% of electron mobility

PMOS device will conduct only 40% fo current of NMOS device
Thus NMOS devices are preferred in many applications

MOSFET Circuit Symbols
Shorthand variation uses:
thin line instead of dash for

enhancement - mode
Thick line instead of solid line
for depletion
- mode.
Circle put on gate plate for
PMOS
Body arrow removed.
Capacitances in MOS Transistors

Total gate-channel capacitance CGC = capacitance per area* area of gate:
Linear/Triode Region Saturation Region

Gate-drain capacitance equal sum Portion of channel beyond pinch-off
of: disappears.
gate-channel capacitance CGC

Drain and gate overlap
capacitance CGS0
Capacitances of reverse-biased pn Cutoff Region

junctions consist of components Channel region is gone:
Proportional to bottom area of
source/drain
Small capacitance appears between
sidewall component gate and bulk (body) terminal:
proportional to perimeter
MOS Transistor Scaling

If physical dimension is reduced by factor , voltage across that
dimension must also be decreased by the same factor to maintain
constant electrical field. If W, L and TOX are all reduced by factor :
KN is increased by scale factor

ID, CGC, (time constant of capacitance) is decreased by scale factor

Total power supplied to circuit decreased by 2, power per unit area
constant
High electric field problem arises if dimensions are scaled down with
constant voltage supply.
Biasing NMOSFET
Biasing used to establish well-defined Q-point for MOSFET in a
particular region of operation (cutoff, triode or saturation).
To be used as a logic inverter, Q-point is set to be in either cutoff

region (off) or triode region (on).
For logic inverter:

When input VGS is low (VGS < VTN), MOSFET is off, output is 5V (high).
As VGS increases, output drops and reaches on-state low voltage.
For amplifier:
Q-point is located in region of high slope (high gain), saturation region.

Variation in total gate-source voltage vGS causes drain current to
change, amplified replica of AC input voltage appears at drain
Load line determines permissible values of ID and VDS as determined by

external circuit.
Ignore channel-length modulation for hand analysis and Q-point design.

Load- Line Analysis for-Q
Point
Use KVL to find load line equation:
Substitute values and plot two points on

i- v characteristic graph to construct line.
Determine intersection with
GS Vfor the
circuit.
Bias Analysis Approach

1. Assume an operation region (generally saturation region)
2. Use circuit analysis to find VGS
3. Use operating region models to find ID then VDS (Q-point)
4. Check validity of operation region assumptions
Cutoff Triode Saturation
5. Change assumption and analyse again if required

Four-Resistor Biasing
Addition of fourth resistor RS helps stabilize the MOSFET Q-point against
many types of circuit parameter variations.

Most often used to set transistor in saturation region of operation
for use as an amplifier.
Split voltage into two sources, find Thevenin equivalent of left side.
Check assumption!
The Junction Field-Effect Transistor

(JFET) Formed without insulating oxide,
uses pn junctions.
N-type block and two pn junctions that form the gate
Conventional current enters at drain, exits

from source.
Resistance of channel controlled by

changing width of channel through
modulation of depletion layers
surrounding pn junctions between gate
and channel.
In triode region, acts as voltage controlled resistor:

Application of reverse bias to gate-channel diodes will widen depletion
layers, decreasing current.
JFET voltage applied to turn device off

MOSFET voltage applied to turn device on
Reverse bias across gate-channel junction is larger at the drain end,

depletion layer wider at drain end.
Increasing vDS increases depletion layer width at drain end, until

channel pinches off
near drain at
Triode Saturation Cutoff

Small Signal Modelling and Linear Amplification
Transistors said to be operating in active region when biased to be used
as amplifier
Forward-active region for BJT

Saturation region for FET
Q-point used to bias transistor to operate in active region. Q-point also
controls:
BJT Amplifier
BJT biased in active region with small sinusoidal signal
voltage:
Load line equation
5 5
33
From load line, Q-point is for VBE = 0.7 V

Can be seen on right diagram that when VBE is high, VCE is low
Also represented on first waveform diagram
Emitter connected to ground, so this is a common-emitter inverting

amplifier.

MOSFET Amplifier
VGS sets Q-point
Source is grounded, circuit known as common-source inverting

amplifier.
Coupling and Bypass Capacitors

Used to introduce input AC signal and extracting output signal without
disturbing Q-point bias.
Capacitors used to have negligible impendences in frequency range

of interest
Provide open circuits at DC so Q-point is not disturbed

Bypass capacitor maintains ac ground at emitter (emitter voltage
constant)
Circuit Analysis using DC and AC Equivalent Circuits

To simplify analysis, separate DC and AC circuit analysis is performed.
Use DC equivalent to find Q-point o Capacitors

Open circuit o Inductors Short circuit
AC equivalent circuit to find circuit response o
Capacitor reactance is negligible

, Capacitors Short circuits o Inductor
impedance is large , inductors
Open circuits o Nodes connected to DC
voltage source are represented as grounds. o
DC current sources Open circuits DC
Analysis
1. Find DC equivalent circuit using above assumptions
2. Replace transistor with appropriate large-signal model to find Q-
point
AC Analysis
3. Find AC equivalent circuit by using above assumptions.

4. Replace transistor with its small-signal model (depends on Q-
point)

5. Analyse AC characteristics, combine with results from step 2 of DC
analysis to find totals (rarely done since AC behaviour is of most
interest)
Small- Signal Modelling

Signal voltages and currents must be small enough to ensure that the AC
circuit behaves in a linear manner.

Small- Signal Behaviour of Diode
For small changes, they are
linearly related by
diode
conductance:
gD is slope of diode characteristic

around Q- point( tangent)
Diode equation:
Substituting expressions for
iD and vD and lots of messing
around leads to:

Small- Signal Models for BJT
Two- port representation model:
Hybrid
- Pi Model:
R characterizes relationship between changes

BE and
in vib. Ro can often be ignored to
simplify circuit analysis if:
R characterizes relationship between
ce and
v ci.

R , Ro and gm are all related to
C I and so controlled by- point.
Q
Same current vs voltage graph with Q-point and

transconductance slope as diodes shown previously, but IC vs
VBE with slope = gm.

Voltage-controlled source can be written as current-controlled source:
Small Signal Current Gain

Small signal current gain o:
In real transistor, DC current gain F is not constant but a function of
operating current:
From expression for small-signal current gain it can be seen that:

In practice, difference between is usually ignored and they are
commonly assumed to be the same.
Intrinsic Voltage Gain
Maximum voltage gain that transistor can provide, amplification factor.
Does not change with operating point
Small Signal for BJT
If small signal: then:
A 5mv change in vBE corresponds to 20% deviation in IC from Q-point value!

Common-Emitter Amplifier
Circuit where the emitter is grounded, which is clear in the AC
equivalent circuit.
Assume Q-point is found (DC analysis done)
AC equivalent:
Replace transistor with small-signal model:
Emitter is common connection between input (base) and output

(collector)
Base Input Resistance:

Resistance looking into base terminal:
Voltage Gain:
Negative sign
indicates that
this is an inverting amplifier.
Voltage divider to find expression for vB in terms of vi:
Emitter Resistance:
If there is a resistor between emitter and ground:
Limits and Model Simplifications
If:

This fraction is often around 1/3 and with 1/VT = 40:
Upper Bound on Gain

If somehow , then gain approaches the intrinsic gain, typically
several thousand.
Small-Signal Models for FETs

For saturation region :
To show gms dependence on current:

For
Intrinsic Voltage Gain

Unlike BJT, intrinsic voltage gain of MOSFET varies with operating point
For
Small Signal Condition

MOSFET can handle much larger values of input vGS than BJT can.
A change of in vGS results in 40%

deviation in IDS from Q-point.
Body Effect in 4-Terminal MOSFET
If body is not connected to source terminal , there is a back-
gate transconductance gmb.
Drain current is dependent on vSB:
Parameter:

Small Signal Models
Small signal model for NMOS and PMOS are same.
Small signal model for npn and pnp BJT are same.
Small Signal Model for JFET

Small signal model is identical to MOSFET except for:
Summary of BJT and FET Differences

Common-Source Amplifier Terminal Voltage Gain:
Equivalent of Common-Emitter BJT
Amplifier.
So:
Assume Q-point is found,

Signal Source Voltage Gain:
Simplified AC circuit:
Limit for total gain is
MOSFET voltage gain is usually much
lower than BJT.
Design Guide:
Assuming:
Replace with small signal model: 3,

2
,

Input and Output Resistances

Input Resistances
In each case, defined as total resistance looking into amplifier at coupling
capacitor C1.
BJT Common-Emitter MOSFET Common-Source

Usually
Output Resistances
Defined as equivalent resistance looking into output at coupling capacitor
C2 .
BJT Common-Emitter MOSFET Common-Source
Voltage across Voltage across

So usually and So usually and
Output resistances are similar, limited by RC and RD.
Common-Emitter and Common-Source Summary
Amplifier Power and Signal Range

Q-point also determines level of power dissipation and maximum linear
signal range at output.
Power Dissipation
Can be determined from DC equivalent circuits.
BJT MOSFET

Power dissipated in transistor: Power dissipated in transistor:
Total power supplied:

Total power supplied:
Rest of supplied power is dissipated in resistors

Signal Range
In following circuit: 5 9 , 2
So 38
Bypass capacitor at emitter forces
constant emitter voltage, total
so
resultant CvE:

AC signal voltage at
collector.
To remain in active region:
So 3
Also, since voltage drop across
C R
cannot be negative:
Coupling these two conditions:
Similar conditions for MOSFET:
To be in saturation region,
Also cannot exceed DC voltage drop across RD:

In total:
Single Transistor Amplifiers

Previously considered the common-emitter BJT amplifier and the
common-source amplifiers, however there other configurations:
Since the currents in a forward-active BJT depend on the base-emitter

voltage:
And currents in a pinch-off FET depend on the gate-source voltage:

Only the base and emitter or gate and source are useful as signal
insertion points.
IC and iE currents are much greater than iB, so voltage across their
corresponding resistors is higher.
Collector/emitter and drain/source are useful points for signal
removal
Inverting Amplifiers - Common Emitter/Source
R6 in the 4-resistor bias configuration is split into two parts, with only one
bypassed by a capacitor.
Provides flexibility in setting voltage gain, input and output

resistance by not bypassing all resistance at emitter/source.
for
Omit transistor output resistance
simplification
Terminal Voltage Gain:
Decrease ER increase gain
Input Resistance Output Resistance

Looking into base terminal: Looking into collector terminal:
Looking in just after load resistor:

Overall, looking in just after RI:
Total Signal Source Voltage Gain:
Design Notes/Simplifications
Zero emitter resistance: Large emitter resistance:
Small Signal Limit: Vb and Ve will have DC offset of 0.7V

but AC signal voltage will be about
same:
FET Common-Source Variations

Gate terminal input resistance is infinite so total signl source voltage
gain:

Summary
FET C-S amp has much higher Input resistance and input signal range.
Follower Circuits - Common-Collector/Drain
Collector/drain bypassed directly to ground common terminals.
Circuit simplification
| |

| |
Terminal Voltage Gain:

for
This almost unity gain should be expected since vb and ve differ by

constant DC voltage of
0.7 so AC signal voltages should be approximately the same.
Output should almost mirror input with DC shift between signals.

Expressions are same for FET as BJT unless specified:
Looking into base terminal: Looking into emitter/source terminal:
Overall, looking in just after RI:

Looking in just after load resistor:
Total Signal Source Voltage Gain
FET C-S infinite input resistance:
Characteristics:
Provide voltage gain of approximately 1

High input resistance
Low output resistance
Input signals can be quite large without exceeding small-signal limits
Summary

Non-inverting Amplifiers Common-Base/Gate
AC signal injected into emitter/source, extracted from collector/drain.
Base/gate connected to AC ground through bypass capacitor.

Neglectingo,r terminal voltage gain
:

Input Current:

Looking into base terminal: Looking into collector/drain terminal:
Overall, looking in just after RS: Looking in just after load resistor:
Total Signal Source Voltage Gain
Substituting
(expressions same for FET)

Design Notes
Summary
Amplifier Comparison
Range

Signal source gains have same form assuming small source resistance
RI:
Where R
L and R
E vary for each case:
C-E C-C C-B
R6 = bottom right (emitter) bias || 3 6|| 3 || 3
resistor
6|| 3 | | 6

R3 = resistor added to measure output across
Simplified:
FET Amplifiers

Range

Simplified:

Coupling and Bypass Capacitor Design
Impedance of capacitor increases with decreasing frequency.
Coupling and bypass capacitors generally reduce gain

at low frequencies. Common-Emitter/Source Amplifiers
Coupling Capacitors:
C1 C2
Impedance must be smaller than Impedance/reactance must be

equivalent resistance that appears smaller than equivalent resistance at
at terminals: terminals:

Bypass Capacitor
C3: Equivalent resistance at terminals of
C3:
4|| ( )

So:
Common
- Base/Gate
Common-Collector/Drain
Multi-stage AC-Coupled Amplifiers

Often single transistor amplifier cannot meet all specifications of required
amplifier design.
Three-Stage Coupled Amplifier
Signals are coupled from one stage to the next through use of coupling
capacitors.
Capacitors also provide DC isolate between stages permits

independent design of bias circuitry of individual stages.

The DC equivalent circuit and therefore Q-point biasing can be found by
open-circuiting the capacitors.
AC equivalent by replacing capacitors with short circuits:
High input resistance High voltage gain Low output resistance

Modest voltage gain Buffers high-gain
stage 2
Small Signal Model:
Equivalent Resistances:
Voltage Gain:
Input and Output Resistance

R out looking back in
from capacitor6:C
3 | | 3
3
3
3 3
3 = Thevenin
equivalent source
resistance of stage 3:
3 2 | |
2
Current and Power Gain:
Estimating Lower Cutoff Frequency
RiS = resistance at terminals of i-th capacitor Ci.
Replace all other capacitors with short circuit while

analysing one capacitor. DO for every capacitor (C1 to C6
in this example)

Analogue Electronics Complete Course Summary Notes With Examples HD

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ECE2061 - Analogue Electronics Summary

Finn Andersen, 2012 1

Finn Andersen, 2012 2

Finn Andersen, 2012 3

Finn Andersen, 2012 4

Finn Andersen, 2012 5

Finn Andersen, 2012 6

Finn Andersen, 2012 7

Finn Andersen, 2012 8

Thevenin Equivalent 1. Apply KCL atoutput node

defined as output voltage with no load

Substitute and re-arrange:

3. Apply short circuitacross output,

Analogue Signal Amplification

Gain (phasor notation):

Convert to decibel scale:

Amplifier Frequency Response

Leads to nominal and worst case circuit situations.

Finn Andersen, 2012 10

Input and Output Resistances

Apply test current, turn off independent sources, determine voltage.

Finn Andersen, 2012 11

Finn Andersen, 2012 12

Integrates the input voltage.

Capacitor initially starts out as an effective short circuit

If alter nating signal is applied:

Capacitor is charged and discharged

Finn Andersen, 2012 13

Capacitor and resistor reversed.

Non-Ideal Operational Amplifiers

Gain stability Reduces sensitivity of gain to variations in values of

Feedback Factor Open- loop gain

Non- Ideal Operational Amplifier

Finn Andersen, 2012 14

Non-zero output resistance

Finite Input Resistance

Finn Andersen, 2012 15

Feedback Amplifier Categories:

Finn Andersen, 2012 16

Transconductan High input

RXD = resistance looking into same terminal pair

Finn Andersen, 2012 17

So there is series feedback at the input because the amplifier input

So amplifier output and feedback network are connected in parallel (same

( now accounts for non

Input Resistance Calculations

Finn Andersen, 2012 18

TSC found by shorting input terminals, circuit becomes

For TOC , no current can flow through

Output Resistance Calculations

Connecting output terminal to ground shorts the

Expressions are identical to those shown in summary table earlier, but

Closed- loop gain

Finn Andersen, 2012 19

Resistance between input and

Circuit for finding output resistance:

Resistance between output and

Find Thevenin Equivalent1of

Assume idv = 1 in source and solve for

Finn Andersen, 2012 20

So amp and feedback network are in

Also parallel feedback at output

Input Resistance Calculations