1S-10
A Real-time Permutation Entropy Computation for EEG Signals
Xiaowei Ren, Qihang Yu, Badong Chen, Nanning Zheng and Pengju Ren
Institute of Articial Intelligence and Robotics, Xian Jiaotong University
No.28 Xianning West Road, Xian Shaanxi, China, 710049
Email: {renxiaowei66, pengjuren}@gmail.com
Abstract In this paper, we implement a recong-
urable FPGA accelerator which could compute mul-
tiscale permutation entropy for 128 EEG signals si-
multaneously in real time. When it works at 150MHz
and the window size is 256, compared with C code
running on a 3GHz Intel(R) Core(TM) i5-2320 CPU,
the average speedup is 3748.
I. Introduction
Scientists nd that the change of EEG signals com-
plexity could be used to predict the onset of brain dis-
eases [1] and multiscale permutation entropy (MPE) is a
method which could quantify the complexity of physio-
logic time series. Compared with traditional permutation
entropy [2], MPE takes the multiple time scale of physio-
logic dynamics into consideration. So MPE could separate
healthy and pathologic groups much more robustly.
In [3], we implemented a recongurable FPGA acceler-
ator for the evaluation of traditional permutation entropy
(i.e. the time scale factor is set to 1 constantly). There-
fore, in this paper, we improve the design of [3] by allow-
ing dierent values for time scale factor. When it works
at 150MHz and the window size is 256, our platform is
3748 times faster on average than the C code running on
a 3GHz Intel(R) Core(TM) i5-2320 CPU.
II. Multiscale Permutation Entropy
Assuming the time series {yt }N t=1 , determined by dier-
ent scale factor , we can construct coarse-grained time
series, {x }, according to the following formula:

j {xi+1 , xi+2 , ..., xi+T } are the ith and (i + 1)th window re-
xj = 1/ yi , 1 j N/ (1)
i=(j1)+1
Then we need to compute the permutation entropy for
{x }. If embedding dimension and time delay are n and
respectively, the time-delayed embedding representation
of time series {x } is Xt,n, = {xt , xt+ , ..., xt+(n1) }.
If we set = 1 here for simplicity, the time series has
T (n + 1) subvectors Xt,n,1 = {xt , xt+1 , ..., xt+n1 },
which have n! possible permutation types (representing
the unique orderings of n dierent numbers). Then, the
permutation entropy of embedding dimension n 2 could
be dened as:

n!
H(n) = p(i ) log p(i ) (2)
i=1
978-1-4799-7792-5/15/$31.00 2015 IEEE
Where log is with base 2, i is one of the n! permutation
types {i }n!
i=0 and p(i ) is dened as:
{t|t T n + 1, type(Xt,n ) = i }
p(i ) = (3)
T n+1
Where . denotes the cardinality of a set.
III. Hardware Implementation
A. Input Data Processing
This part is used to construct the coarse-grained time
series according to dierent value of scale factor. When
the number of added data equal to the scale factor, the
next input should add with zero and the sum of adder is
divided by scale factor. If not, every input datum contin-
ues to add one by one. The result of divider is sent to the
subsequent circuitry to compute the permutation entropy
of coarse-grained time series.
B. Permutation Type Generation
Permutation type generation is used to generate per-
mutation type i for every subvector according to dier-
ent embedding dimensions. Every new input datum is
compared with its former four inputs through compara-
tors, which results are right shifted to comp result1 to
comp result4 respectively. Furthermore, according to dif-
ferent values of embedding dimension, which could be 2,
3, 4, and 5 for our design, some bits of these four shift
registers are selected out to form the permutation type.
C. Permutation Entropy Calculation
If we analyze the time series with a sliding window,
which contains T sample data, {xi , xi+1 , ..., xi+T 1 } and
spectively. Its obvious that only xi and xi+T could lead
to the dierence of permutation entropy between these
two sliding windows. In order to make full use of the
overlapping part, we denote the permutation types of sub-
vectors Xi,n and Xi+T ,n
(n1) as decrease and increase
respectively and update the value of permutation entropy
like section III.B of [3]. As the section III.B of [3] said, two
operations are conducted for every decrease and increase ,
so the clock domain 2 should be two times faster than
clock domain 1. Meanwhile, beneting from dual ports of
the LogFILE, we could process decrease and increase in
parallel, accelerating the computation rate.
IV. Evaluation
The FPGA we used is Xilinx Virtex-7 XC7V2000T
which works at 150MHz. By instantiating our processing
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 1S-10

Input Data Processing Permutation Type Generation Permutation Entropy Calculation

window_size
Delay

scale_factor Input comp_result4 embedding Ctrl Delay

COMP
Buf5 dimension Unit
4

accum_operation
Logarithm
comp_result3

out_en
Input LUT
COMP
Add_A_Src Buf4
3 wr_en1
0 pe_type data_in1 DIV MULT
out_Src1
Fix
Input comp_result2 in_Src1
COMP to
Buf3 Float
2 Output
MUX Log
ADD ACCUM
ADD FILE
rd_en
Input Input comp_result1 Logarithm
COMP
Buf2 LUT
1 wr_en2
FIFO data_in2 DIV MULT
out_Src2
Int in_Src2
Input Fix
to DIV
Buf1 wr_en to
Float
Float

Clock Domain 1 Clock Domain 2

Fig. 1. The Microarchitecture of Pipeline

element 128 times, we implement a parallel platform to TABLE III

implementation result of fpga platform
process 128 EEG signals simultaneously. The EEG data
Resources Utilized Available Utilization Rate(%)
are provided by the CNEL of UFL. The C code runs on FF 461184 2443200 18.88
a 3GHz Intel(R) Core(TM) i5-2320 CPU. For every com- LUT 454656 1221600 37.22
Memory LUT 1280 344800 0.37
bination of window size and embedding dimension, scale I/O 67 1200 5.58
factor is changed from 1 to 4. BRAM 640 1292 49.54
DSP48 1280 2160 59.26
A. Accuracy of Hardware Design BUFG 3 128 2.34
MMCM 1 24 4.17
TABLE I
calculation error of fpga platform
Window Embedding Maximum Average C. Implementation Result
size dimension error(%) error(%)
3 0.150 0.058 Table III shows that our design consumes only 18.88%
256 4 0.256 0.135 Flip-Flop (FF) and 37.22% Lookup Table (LUT), which
5 0.363 0.206
3 0.116 0.063 are two main resources of FPGA. So we can denitively
512 4 0.188 0.119 conclude that we implement this platform at very low
5 0.231 0.159
3 0.085 0.037
hardware cost.
1024 4 0.115 0.080
5 0.138 0.093
V. Conclusion
At very low hardware cost, we implement a recong-
We quantize the logarithmic function into a lookup ta- urable parallel FPGA platform which could compute per-
ble, so we want to testify the accuracy of our design rstly. mutation entropy for 128 dierent EEG signals simulta-
Compared with C code, Table 1 shows that most average neously in real time. When it works at 150MHz and the
errors are less than 0.15% and the maximum errors are all window size is 256, its 3748 times faster on average than
so small that they are negligible. Therefore, our FPGA C code for dierent parameters.
implementation satises the accuracy standard perfectly.
Acknowledgments
B. Speedup Analysis
This work was partially funded by 973 program
TABLE II
speedup versus c language
(No.2015CB351703) and NSFC grant No.610303036,
Window Embedding FPGA C Average China Postdoctoral Science Foundation No.2012M521777
size dimension (s) (ms) Speedup and Specialized Research Fund for the Doctoral Program
3 28.230 97.518 3454
256 4 28.230 104.299 3695 of Higher Education of China No.20130201120024.
5 28.230 115.584 4094
3 28.230 91.523 3242 References
512 4 28.230 98.023 3472
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1024 4 28.230 82.096 2908 search, vol. 77, no. 1, pp. 7074, 2007.
5 28.230 87.658 3105
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window size is 256, 512 and 1024 respectively, correspond-
[3] X. Ren, P. Ren, B. Chen, J. C. Principe, and N. Zheng, A
ing average speedup for dierent parameters are 3748, recongurable parallel acceleration platform for evaluation of
3481 and 2888. Because the number of EEG data is xed permutation entropy, in 36th Annual International Conference
at 4200 and the FPGA accepts one datum per cycle, the of the IEEE Engineering in Medicine and Biology Society, 2014.
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