Documente Academic
Documente Profesional
Documente Cultură
December 1992
CMOS Dual Monostable Multivibrator
Features Description
High Voltage Type (20V Rating) CD4098BMS dual monostable multivibrator provides stable
retriggerable/resettable one shot operation for any fixed volt-
Retriggerable/Resettable Capability
age timing application.
Trigger and Reset Propagation Delays Independent of
RX, CX An external resistor (RX) and an external capacitor (CX)
control the timing for the circuit. Adjustment of RX and CX
Triggering from Leading or Trailing Edge provides a wide range of output pulse widths from the Q and
Q and Q Buffered Outputs Available Q terminals. The time delay from trigger input to output
transition (trigger propagation delay) and the time delay from
Separate Resets reset input to output transition (reset propagation delay) are
Wide Range of Output Pulse Widths independent of RX and CX.
100% Tested for Quiescent Current at 20V Leading edge triggering (+TR) and trailing edge triggering
(-TR) inputs are provided for triggering from either edge of
5V, 10V and 15V Parametric Ratings
an input pulse. An unused +TR input should be tied to VSS.
Standardized Symmetrical Output Characteristics An unused -TR input should be tied to VDD. A RESET (on
low level) is provided for immediate termination of the output
Maximum Input Current of 1A at 18V Over Full Pack-
pulse or to prevent output pulses when power is turned on.
age Temperature Range; 100nA at 18V and +25oC
An unused RESET input should be tied to VDD. However, if
Noise Margin (Over Full Package/Temperature Range) an entire section of the CD4098BMS is not used, its RESET
- 1V at VDD = 5V should be tied to VSS. See Table 9.
- 2V at VDD = 10V In normal operation the circuit triggers (extends the output
- 2.5V at VDD = 15V pulse one period) on the application of each new trigger
Meets All Requirements of JEDEC Tentative Standard pulse. For operation in the non-retriggerable mode, Q is
No. 13B, Standard Specifications for Description of connected to -TR when leading edge triggering (+TR) is
B Series CMOS Devices used or Q is connected to +TR when trailing edge triggering
(-TR) is used.
Applications The time period (T) for this multivibrator can be
approximated by: TX = 1/2RXCX for CX 3 0.01F. Time
Pulse Delay and Timing periods as a function of RX for values of CX and VDD are
Pulse Shaping given in Figure 8. Values of T vary from unit to unit and as a
function of voltage, temperature, and RXCX.
Astable Multivibrator The minimum value of external resistance, RX, is 5k. The
maximum value of external capacitance, CX, is 100F.
Figure 9 shows time periods as a function of CX for values of
RX and VDD.
Pinout
CD4098BMS The output pulse width has variations of 2.5% typically, over
TOP VIEW the temperature range of -55oC to +125oC for CX = 1000pF
and RX = 100k.
CX1 1 16 VDD
For power supply variations of 5%, the output pulse width
RXCX (1) 2 15 CX2 has variations of 0.5% typically, for VDD = 10V and 15V
RESET (1) 3 14 RXCX (2) and 1% typically, for VDD = 5V at CX = 1000pF and
+TR (1) 4 13 RESET (2)
RX = 5k.
-TR (1) 5 12 +TR (2) The CD4098BMS is supplied in these 16-lead outline packages:
Q1 6 11 -TR (2) Braze Seal DIP H4T
Q1 7 10 Q2 Frit Seal DIP H1F
Ceramic Flatpack H6W
VSS 8 9 Q2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. File Number 3332
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
7-482
CD4098BMS
Functional Diagram
CX1
RX1
VDD
1 2 RXCX (1)
4 6
+TR Q1
5
-TR MONO 1
3 7
RESET Q1
12 10
+TR Q2
11
-TR MONO 2
13 9
RESET Q2
15 14 RXCX (2)
VDD
RX2
VDD = 16 CX2
VSS = 8
7-483
Specifications CD4098BMS
Absolute Maximum Ratings Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V Thermal Resistance . . . . . . . . . . . . . . . . ja jc
(Voltage Referenced to VSS Terminals) Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA Maximum Package Power Dissipation (PD) at +125 C o
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
Package Types D, F, K, H For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Linearity at 12mW/oC to 200mW
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for For TA = Full Package Temperature Range (All Package Types)
10s Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS (NOTE 1) SUBGROUPS TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25 oC - 2 A
2 +125oC - 200 A
VDD = 18V, VIN = VDD or GND 3 -55oC - 2 A
Input Leakage Current IIL VIN = VDD or GND VDD = 20V 1 +25o C -100 - nA
2 +125oC -1000 - nA
VDD = 18V 3 -55oC -100 - nA
Input Leakage Current IIH VIN = VDD or GND VDD = 20V 1 +25oC - 100 nA
2 +125oC - 1000 nA
VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10A 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10A 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH > VOL < V
VDD/2 VDD/2
VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC
Input Voltage Low VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V
(Note 2)
Input Voltage High VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V
(Note 2)
Input Voltage Low VIL VDD = 15V, VOH > 13.5V, 1, 2, 3 +25oC, +125oC, -55oC - 4 V
(Note 2) VOL < 1.5V
Input Voltage High VIH VDD = 15V, VOH > 13.5V, 1, 2, 3 +25oC, +125oC, -55oC 11 - V
(Note 2) VOL < 1.5V
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit
implemented. is 0.050V max.
2. Go/No Go test with limits applied to inputs.
7-484
Specifications CD4098BMS
7-485
Specifications CD4098BMS
LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 7.5 A
N Threshold Voltage VNTH VDD = 10V, ISS = -10A 1, 4 +25oC -2.8 -0.2 V
7-486
Specifications CD4098BMS
LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
N Threshold Voltage VTN VDD = 10V, ISS = -10A 1, 4 +25oC - 1 V
Delta
P Threshold Voltage VTP VSS = 0V, IDD = 10A 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage VTP VSS = 0V, IDD = 10A 1, 4 +25oC - 1 V
Delta
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH > VOL < V
VDD/2 VDD/2
VDD = 3V, VIN = VDD or GND
Propagation Delay Time TPHL VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x ns
TPLH +25oC
Limit
NOTES: 1. All voltages referenced to device GND. 3. See Table 2 for +25oC limit.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record
MIL-STD-883
CONFORMANCE GROUP METHOD GROUP A SUBGROUPS READ AND RECORD
Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6 Sample 5005 1, 7, 9
Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
7-487
Specifications CD4098BMS
OSCILLATOR
FUNCTION OPEN GROUND VDD 9V -0.5V 50kHz 25kHz
Static Burn-In 1 6, 7, 9, 10 1-5, 8, 11-15 16
Note 1
Static Burn-In 2 6, 7, 9, 10 1, 8, 15 2-5, 11-14, 16
Note 1
Dynamic Burn- - 1, 4, 8, 12, 15 2, 14, 16 6, 7, 9, 10 5, 11 3, 13
In Note 1
Irradiation 2, 6, 7, 9, 10, 14 1, 8, 15 3-5, 11-13, 16
Note 2
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V 0.5V
RETRIGGERABLE MODE
PULSE WIDTH (+TR MODE) TX
NON-RETRIGGERABLE MODE
PULSE WIDTH (-TR MODE) TX
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
488
CD4098BMS
Logic Diagram
VDD
4 (12) * D Q
+TR
C
5 (11) * R1 R2
-TR
VDD
3 (13) *
RESET
* 2 (14)
RXCX
1 (15)
8 VSS
VSS
16 VDD
Q
6 (10)
7 (9)
Q
VDD
NOTE:
SCHEMATIC SHOWN IS 1/2 OF TOTAL
PACKAGE. TWO SETS OF TERMINAL *ALL INPUTS ARE PROTECTED
NUMBERS ARE SHOWN. TERMINALS BY CMOS PROTECTION
NETWORK
1, 8, AND 15 ARE ELECTRICALLY
CONNECTED INTERNALLY.
VSS
20 10.0
10V
15 7.5
10V
10 5.0
5 2.5
5V 5V
0 5 10 15 0 5 10 15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS CHARACTERISTICS
7-489
CD4098BMS
-10 -5
-15
-10V -10V
-20 -10
-25
-15V -15V
-30 -15
FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS CHARACTERISTICS
10V
100 100
15V 10V
5V
50
FIGURE 6. TYPICAL PROPAGATION DELAY TIME vs LOAD CA- FIGURE 7. TRANSITION TIME vs LOAD CAPACITANCE FOR
PACITANCE, TRIGGER INTO Q OUT (ALL VALUES RX = 5k-10000k AND CX = 15pF-10000pF
OF CX AND RX).
RX = 10K
EXTERNAL RESISTANCE (RX) ()
6 VDD = 3V
4
CX = 15pF = 5V
2 106 = 10V, 15V, 18V
106
8 CX = 100pF
6
4 105
CX = 0.1 F
2
105 CX = 1000pF
8
104
6
4 CX = 0.01F
RX = 100K
2 103
4 RX = 5K
10 RX =1M
8 VDD = 3V
6
4 = 5V 102
2 = 10V, 15V, 18V RX = 10M
VDD = 3V, 5V VDD = 5V, 10V, 15V, 18V
103 10
2 4 68 2 4 68 2 4 68 2 4 68 2 4 68 24 68 24 68
10-1 1 10 102 103 104 105 106 10-1 1 10 102 103 104 105 106
PULSE WIDTH (PW) (s) PULSE WIDTH (PW) (s)
FIGURE 8. TYPICAL EXTERNAL RESISTANCE vs PULSE FIGURE 9. TYPICAL EXTERNAL CAPACITANCE vs PULSE
WIDTH WIDTH
7-490
CD4098BMS
1058
6
AMBIENT TEMPERATURE (TA) = +25oC
2
SUPPLY VOLTAGE (VDD) = 5V
1038
6
4
1028
6 10V
4
2 15V
10
2 4 6 8 2 4 6 8 2 4 6 8 2 4 6 8
10 102 103 104 105
EXTERNAL CAPACITANCE (CX) (pF)
FIGURE 10. TYPICAL MINIMUM RESET PULSE WIDTH vs EXTERNAL CAPACITANCE
106 AMBIENT TEMPERATURE (TA) = +25oC
AVERAGE POWER - DISSIPATION FOR 100%
105 0.1F 1F
6 cycle:
4 T
2 tm P100 where m = one shot pulse
104
P= ( T
) width
6
4
T = trigger pulse period
2
e.g. For m = 600s, tT = 1000s. CX = 0.01mF
103
6
4
VDD = 5V m
VDD = 5V
600 103 W = 600W (see dotted line on
102
2 = 10V
= 15V
P1 = ( 1000
) graph)
2 4 68 2 4 68 2 4 68 2 4 68 2 4 68
1 10 102 103 104 105
ONE-SHOT PULSE WIDTH (m) (s)
Applications
VDD VDD
RX1 RX2
CX1 CX2
1 2 Q -TR 15 14 Q
+TR 4 6 11 10
MONO 1 OUTPUT
5 VSS 12 MONO 2
VDD
3 VDD 13
RX1 CX1
T1
2
INPUT PULSE
RX2 CX2
T2
T1 T2 2
OUTPUT PULSE
CX 0.01F
7-491
CD4098BMS
Applications (Continued)
VDD
VDD IDD
SUPPLY
RX1 RX2
CX1 CX2
IDD, TX vs RX
IDD TX
RX (AVG.) (T1 + T2) VDD
+TR 1 2 Q1 -TR 15 14 Q2
4 6 11 9 10k 1mA 3.8s 5V
VDD 5 MONO 1 VSS 12 MONO 2
R Q1 R Q2 OUTPUT 0.05mA 0.5s
3 8 13 10
2.5mA 3.2s 10V
VSS
0.5mA 0.5s
5mA 3s 10V
RUN
VDD
VDD VDD 10M
SUPPLY 0 1mA 0.5s
VSS
RESET RESET* NOTES:
1. All values are typical.
T2 T1 T2 2. CX range: 0.0001F to 0.1F
* TO ENSURE RESTART, APPLY RESET
(NEGATIVE PULSE) AFTER VDD
SUPPLY VOLTAGE HAS REACHED Q2
ITS VDD LEVEL
TX
IDD
7-492