Phase locked loop frequency synthesizers

SMDP Instructional Enhancement Program

Nagendra Krishnapura

Department of Electrical Engineering

Indian Institute of Technology, Madras
Chennai, 600036, India

13-24 Nov 2006

Nagendra Krishnapura Phase locked loop frequency synthesizers

Local oscillator requirements

Generate equally spaced frequencies from an input

reference frequency
Waveform shape not very important
Spurious output must be sufficiently low
Noise must be sufficiently low

Nagendra Krishnapura Phase locked loop frequency synthesizers

Frequency divider

Vref

R
fref fref/N
Vref/N N
R(N-1) frequency
divider

Digital frequency divider can generate multiple frequencies

Frequencies not equally spaced
Reference frequency higher than output frequencies

Nagendra Krishnapura Phase locked loop frequency synthesizers

Voltage multiplier
voltage difference
zero, at steady state
Vref K1Vctl+Vo Vout
+ K2 dt +
- Vctl + R

Vout/N -

R(N-1)

Vout/N = Vref at steady state

A controlled source to generate the output voltage
Divided output voltage subtracted from the reference to
generate error
Output source controlled by the integral of the error
Nagendra Krishnapura Phase locked loop frequency synthesizers
Frequency multiplier

frequency difference
zero, at steady state

cos(2freft) fref Vctl KvcoVctl+fo

frequency cos(2foutt) slope = Kvco
measure + K2 dt
fout
-
fout/N fo
frequency
measure N
Vctl

cos(2fout/N t)
fout/N = fref at steady state

A controlled source to generate the output frequency

A voltage controlled oscillator
Divided output frequency subtracted from the reference
frequency to generate error
Output source controlled by the integral of the frequency
error

Nagendra Krishnapura Phase locked loop frequency synthesizers

Phase and frequency

Sinusoid cos((t))
Phase: (t)
1 d(t)
Instantaneous frequency fi = 2 dt
Typically expressed as fi = fo + fe (t) where fo is the
average frequency and fe is the instantaneous frequency
error
R
Phase (t) = 2fo t + o + 2 fe (t)dt
Phase (t) = 2fo t + o + (t)
o : phase offset
(t): instantaneous phase

Nagendra Krishnapura Phase locked loop frequency synthesizers

Frequency multiplier
phase difference

cos(2freft) fref Vctl KvcoVctl+fo

frequency cos(2foutt)
measure K2 dt +
-

dt
K2
fout/N
frequency
measure N

cos(2fout/N t)
fout/N = fref at steady state

Integration before subtraction

Integral of the frequency is phase
Integrator+subtractor measures phase difference between
the reference input and the divided output (feedback)

Nagendra Krishnapura Phase locked loop frequency synthesizers

Frequency multiplierPhase locked loop

Vctl = Kpd(ref-out/N)
cos(2freft+ref) Vctl KvcoVctl+fo
phase cos(2foutt)
detector

fout/N
N

cos(2fout/N t + out/N)
fout/N = fref at steady state

Use a phase detector to generate the control voltage

Nagendra Krishnapura Phase locked loop frequency synthesizers

Voltage controlled oscillator
slope = Kvco
fout

Vctl fout=KvcoVctl+fo fo

Vctl

2fot

Vctl + vco
+
2Kvco dt

fvco = fo + Kvco Vctl

R
vco = 2fo t + 2Kvco Vctl dt
Kvco : VCO gain in Hz/V
Nagendra Krishnapura Phase locked loop frequency synthesizers
Phase detector

1 Kpd(1-2)
phase
2 detector

Kpd: phase detector gain

Kpd : Phase detector gain in V/radian
Ideal phase detector: assumed to have an output
Vpd = Kpd (1 2 )

Nagendra Krishnapura Phase locked loop frequency synthesizers

Phase locked loop model
2fot

2freft+ref Vctl + 2fout t+out

+
+ Kpd 2Kvco dt
-

2fout/N t+vco/N
1/N

Vctl = 2(fref-fout/N)t + ref - out/N

At steady state, fref=fout/N; Vctl = ref - out/N

Modelled in terms of phases of signals

At steady state (lock), Vctl is a constant fref = fout /N .
The loop locks with
Vctl = Kpd (ref out /N) = (Nfref fo )/Kvco This is the
operating point of the circuit

Nagendra Krishnapura Phase locked loop frequency synthesizers

Phase locked loop model

2fot

2freft+ref+ref Vctl+vctl + 2fout t+out+out

+
+ Kpd 2Kvco dt
-

1/N
2fout/N t+out/N+out/N

An increment ref in the input phase causes increments

out , vctl

Nagendra Krishnapura Phase locked loop frequency synthesizers

Phase locked loop modelincremental picture

ref vctl out

+ Kpd 2Kvco dt
-

out/N
1/N

An increment ref in the input phase causes increments

out , vctl
Type-I loopOne integrator in the loop

Nagendra Krishnapura Phase locked loop frequency synthesizers

Phase locked loop modelfrequency domain

ref(s) vctl(s) 2Kvco out(s)

+ Kpd
s
-

out(s)/N
1/N

Loop gain L(s) = 2Kpd Kvco /Ns

Transfer function out (s)/ref (s) = N/(1 + Ns/(2Kpd Kvco )
Type-I loopOne integrator in the loop

Nagendra Krishnapura Phase locked loop frequency synthesizers

Type-I PLLlimitations

Phase error when locked (fout = Nfref ):

ref out /N = (Nfref fo )/Kvco Kpd
< ref out /N <
fo Kpd Kvco < fout < fo + Kpd Kvco
Lock range limited by periodicity of phase detector (period
of all phase detectors not necessarily )
Kpd Kvco large for wide lock range

Nagendra Krishnapura Phase locked loop frequency synthesizers

XOR phase detector
Tref

+1
reference
-1
reference
pdout
+1
divider o/p
divider o/p
-1

+1
pdout Average value = 2/-1
-1 Output periodic at 2fref

Tref/2
= ref-div

 
2  4 X n
Vout (f ) = (f )+ sinc ejn (f 2nfref )
2
n=1
 
2  4 n
sinc
X
Vout (t) = + cos(4nfref tn)
2
n=1

Nagendra Krishnapura Phase locked loop frequency synthesizers

XOR phase detector

Output average value = 2/ 1 = 2/( /2)

Kpd = 2/
Phase detector offset = /2
Loop locks with ref out /N = /2 for Nfref = fo
Output range = /2 around an offset of /2
PLL lock range = fo /2Kpd Kvco < fout < fo + /2Kpd Kvco
Output contains 2fref and its harmonics
P
Output = 2/( /2) + n an cos(4nfref t + n ))
Periodic signal in addition to Kpd
All real phase detectors have a periodic error in addition
to the dc term proportional to phase error

Nagendra Krishnapura Phase locked loop frequency synthesizers

XOR phase detector-Error spectrum

1.5
ref div = /2

0.5

0
0 5 10 15 20

1.5
ref div = /4

0.5

0
0 5 10 15 20
f/f
ref

Nagendra Krishnapura Phase locked loop frequency synthesizers

PLL with XOR phase detector
n ancos(4nfreft+n) ("error")

ref + vctl out

+ + Kpd 2Kvco dt
- -
/2 (offset)
vco/N
1/N

Error E(t) added to the input of the phase detector

Disturbances in the vco phase out (t), even with a perfect
reference (ref (t) = 0)
VCO output: cos(2Nfref t + Nref /2 + out (t))
VCO output not periodic at Nfref
Nagendra Krishnapura Phase locked loop frequency synthesizers
PLL with XOR phase detector

70
ideal phase
error
60 phase with error

50

40

30

20

10

10
0 2 4 6 8 10

Nagendra Krishnapura Phase locked loop frequency synthesizers

PLL with XOR phase detectorfrequency domain

E(s) E(j2f) = n an ejn (f-2nfref)

ref(s) + vctl(s) 2Kvco out(s)

+ + Kpd
s
- -
/2 (offset)
vco(s)/N
1/N

ref(s) = 0 for a perfectly periodic reference

Transfer function from the error to the output

out (s)/E(s) = out (s)/ref (s) = N/1 + Ns/(2Kpd Kvco )
P
E(j2f ) = n an exp(jn )(f 2nfref )

Nagendra Krishnapura Phase locked loop frequency synthesizers

Type-I PLL

out (s) out (s)

= (1)
E(s) ref (s)
2Kpd Kvco /Ns
= N (2)
1 + 2Kpd Kvco /Ns
1
= N (3)
1 + sN/2Kpd Kvco
(4)
Loop gain
2Kpd Kvco
L(s) = (5)
Ns
Closed loop bandwidth
Kpd Kvco
f3dB = (6)
N
Nagendra Krishnapura Phase locked loop frequency synthesizers
Type I PLL

dB

loop gain |L|

2KpdKvco/N

L/(1+L)
|out/ref|
dB
20log(N)

2KpdKvco/N

(loop bandwidth)

Nagendra Krishnapura Phase locked loop frequency synthesizers

Feedback system
In our system,

out (s) 2Kpd Kvco /Ns

= N (7)
E(s) 1 + 2Kpd Kvco /Ns

In general, in a feedback system with a loop gain L(s)

L(s)
Hclosedloop (s) = Hideal (s) (8)
1 + L(s)
(9)

Where Hideal (s) is the ideal closed loop gain (with L = ). This
can be approximated as

Hclosedloop (s) = Hideal (s)L(s) |L|  1 (10)

= Hideal (s) |L|  1 (11)

Nagendra Krishnapura Phase locked loop frequency synthesizers

PLL with XOR phase detectorOutput signal

Output phase error (constant phase offsets ignored)

X
(j2f ) = an H(j4nfref ) exp(jn )(f 2nfref ) (12)
n

X
= bn exp(jn )(f 2nfref ) (13)
n=1

X
(t) = bn cos(4nfref t + n ) (14)
n=1

X
Vout (t) = cos(2Nfref t + bn cos(4nfref t + n )) (15)
n=1

Nagendra Krishnapura Phase locked loop frequency synthesizers

PLL with XOR phase detectorOutput signal
Considering only the term at 2fref , and b1  1

Vout (t) = cos(2Nfref t + b1 cos(4fref t + 1 )) (16)

= cos(2Nfref t) cos(b1 cos(4fref t + 1 )) (17)
sin(2Nfref t) sin(b1 cos(4fref t + 1 )) (18)
cos(2Nfref t) b1 cos(4fref t + 1 ) sin(2Nfref(19)
t)
= cos(2Nfref t) b1 /2 sin(2(N + 2)fref t + 1 ) (20)
b1 /2 sin(2(N 2)fref t + 1 ) (21)

Spurious tones in the output at 2fref from the desired

frequency
Reference feedthrough
In general, spurious tones will be present at nfref from the
desired PLL output
Nagendra Krishnapura Phase locked loop frequency synthesizers
Reference feedthrough

b1 = a1 |H(j4fref )| (22)
 
 Kpd Kvco /j2Nfref 
= a1 N 
  (23)
1 + Kpd Kvco /j2Nfref 
 
 Kpd Kvco 
a1 N 
  (24)
j2Nfref 
4 f3dB
N (25)
2fref

Nagendra Krishnapura Phase locked loop frequency synthesizers

Reference feedthroughexample

To generate 1 GHz from 1 MHz reference

b1 = 102 (spurious tones 46 dB below the oscillation level
N = 103
f3dB /fref = /2 105 f3dB = 5 Hz
Lock range = Nf3dB 50 kHz
Lock range is too small; It cant switch to the next channel
which is 1 MHz away!

Nagendra Krishnapura Phase locked loop frequency synthesizers

Relationship between magnitude and phase [Bode]
dB
poles
-20dB/dec zeros

-40dB/dec

-20dB/dec

p1 p2 z1 p3

-60dB/dec

p1 p2 z1 p3
0

-/2

-3/2

-2

Nagendra Krishnapura Phase locked loop frequency synthesizers

Relationship between magnitude and phase [Bode]

All poles and zeros of the network assumed to be real and in

the left half plane.
The magnitude plot(log-log) consists of segments of slope
20k dB/decade
Poles and zeros form breakpoints between segments
At each pole the slope increments by -20 dB/decade
At each zero the slope increments by +20 dB/decade
Phase at poles/zeros will be m/4 radians
Derivative of phase is positive at a zero and negative at a
pole

Nagendra Krishnapura Phase locked loop frequency synthesizers

Stability criteria for negative feedback loops
dB
poles
-20dB/dec zeros

-40dB/dec

-20dB/dec

p1 p2 z1
u p3

-60dB/dec

p1 p2 z1 p3
0
o
>45 phase margin
-/2

-3/2

-2

Nagendra Krishnapura Phase locked loop frequency synthesizers

Stability criteria for negative feedback loops

All poles and zeros of the loop gain function assumed to be real
and in the left half plane.
Phase margin should be greater than a specified
amount (assume 45 )
Phase lag at u should be less than 125
At u , the Bode plot should have a slope of -20 dB/decade

Nagendra Krishnapura Phase locked loop frequency synthesizers

Increasing the lock range of the phase detector-I

increased KpdKvco (dc)

=> increased lock range
increased loop bandwidth
(faster switching)
|vco/ref|
dB, loop gain dB, closed loop gain
20log(N)
0dB ref
2KpdKvco/Ns

2KpdKvco/N
2KpdKvco/N
increased KpdKvco
=> increased lock range
2KpdKvco/Ns
0dB increased
reference
feedthrough
L/(1+L)

Increase Kpd Kvco at all frequencies

Causes increased reference feedthrough

Nagendra Krishnapura Phase locked loop frequency synthesizers

Increasing the lock range of the phase detector-II
dB, loop gain
increased KpdKvco (dc)
=> increased lock range
|vco/ref|
dB, closed loop gain
20log(N)
2Kpd,IKvco/Ns2
0dB ref

2KpdKvco/Ns

2KpdKvco/N

(2KpdKvco/N)1/2
-40dB/decade at
unity loop gain
=> instability!
0dB
L/(1+L) decreased
2KpdKvco/N

(2KpdKvco/N)1/2
reference
feedthrough

Increase Kpd Kvco only at dc (steady state phase error

reduces)
In the limit, use an integrator Kpd,I /s steady state phase
error reduces to zero
Two integrators in a loop unstable system
Increased attenuation slope can reduce reference
feedthrough
Nagendra Krishnapura Phase locked loop frequency synthesizers
Increasing the lock range of the phase detector-III
dB, loop gain
increased KpdKvco (dc)
|vco/ref|
dB, closed loop gain
=> increased lock range
20log(N)
ref
2Kpd,IKvco/Ns2

2KpdKvco/N
-20dB/decade at unity loop gain
2KpdKvco/Ns
=> stable system

L/(1+L) decreased
2KpdKvco/N
zero at Kpd,I/Kpd

(2KpdKvco/N)1/2

reference
feedthrough

Increase Kpd Kvco only at dc (steady state phase error

reduces)
In the limit, use an integrator Kpd,I /s steady state phase
error reduces to zero
Maintain 20 dB/decade slope at unity loop gain
introduce a zero before u
Introduce a pole beyond u to increase attenuation of
reference feedthrough
Nagendra Krishnapura Phase locked loop frequency synthesizers
Type II PLLwith two poles and a zero
zero at
steady state 2fot
Kpd,I dt
2freft+ref + Vctl + 2fout t+out
+
+ 2Kvco dt
- +
Kpd

2fout/N t+out/N
1/N

dVctl/dt 2(fref-fout/N)t + ref - out/N

At steady state, fref=fout/N; ref - out/N = 0;

At steady state, reference input and divider output have the

same frequency and phase
The integrators output stabilizes to the value required to
make the VCO to oscillate at Nfref
At steady state, Vctl = (Nfref fo )/Kvco

Nagendra Krishnapura Phase locked loop frequency synthesizers

Type II PLLAdditional attenation poles

zero at poles beyond

steady state 2KpdKvco/N 2fot
Kpd,I dt
2freft+ref + Vctl + 2fout t+out
+
+ filter 2Kvco dt
- +
Kpd

2fout/N t+out/N
1/N

dVctl/dt 2(fref-fout/N)t + ref - out/N

At steady state, fref=fout/N; ref - out/N = 0;

Additional poles beyond the unity loop gain frequency to

reduce reference feedthrough

Nagendra Krishnapura Phase locked loop frequency synthesizers

Type II PLLFrequency domain

p1 > 2KpdKvco/N
Kpd,I more poles can be used
s
ref(s) + vctl(s) 1 Vctl 2Kvco out(s)
+
1+s/p1 s
- +
Kpd

out(s)/N
1/N

Nagendra Krishnapura Phase locked loop frequency synthesizers

Type II PLLImplementation

Tref
reference
iout reference
iout
+1
reference
-1 divider o/p + divider o/p +
R1 proportional R1
= ref-div proportional
output
+1 + integral
divider o/p -
output
-1 C1 C2
reference
iout
+Icp
pdout -
divider o/p +
-Icp C1 integral
output
proportional +IcpR
output
-
-IcpR

integral
slope=Icp/C
output

XOR gate with a current output (Icp )

Integral term Kpd,I /s: Current flowing into a capacitor C1
Proportional term Kpd : Current flowing into a resistor R1
Series RC to obtain the sum
Additional capacitor C2 to introduce the second pole

Nagendra Krishnapura Phase locked loop frequency synthesizers

Type II PLL with an XOR phase detector

error: 50% duty cycle at 2fref

n ancos(4nfreft+n) ("error")
Kpd,I dt

ref + + vctl out

+ + 2Kvco dt
- - +

/2 Kpd
out/N
1/N

Loop locks with /2 offset between ref and vco /N for all
frequencies
Periodic error E(t) is a 50% duty cycle square wave at 2fref
n
sinc
X
E(t) = 2 cos(4nfref t n/2)
2
n=1

Nagendra Krishnapura Phase locked loop frequency synthesizers

Type II PLL with an XOR phase detector-Frequency
domain

E(j2f) = n an ejn (f-2nfref)

E(s) Kpd,I
s
ref + + vctl 2Kvco out
+ +
s
- - +

/2 Kpd
out/N
1/N

Nagendra Krishnapura Phase locked loop frequency synthesizers

Type II PLL with an XOR phase detector

Lock range is not limited by phase detector

Large error signal even under lock significant reference
feedthrough
XOR output sensitive to duty cycle of inputs
Better to have a phase detector with zero output for zero
phase error
Better to have a phase detector sensitive only to the edges
Loop bandwidth can be widened while maintaining low
reference feedthrough

Nagendra Krishnapura Phase locked loop frequency synthesizers

Tri state phase detector

1 QA
A A D Q
A
ref RST
B -1 0 +1 A
B RST
div
QB
B B 1
D Q

output=QA-QB

Output +1, 1, 0
+1 if reference leads divider output
1 if reference lags divider output
0 if reference coincides with divider output

Nagendra Krishnapura Phase locked loop frequency synthesizers

Tri state phase detector-waveforms

Tref Tref

+1 +1
A -1
A -1

+1 +1
B B
-1 -1

+1 +1
QA QA
+1 +1
QB QB

= ref-div = ref-div

A leading B A lagging B

Flip flops assumed to be reset instantaneously

Nagendra Krishnapura Phase locked loop frequency synthesizers

Tri state phase detector-reset path delay

Tref Tref

+1 +1
A -1
A -1

+1 +1
B B
-1 -1

+1 +1
QA QA
+1 +1
QB QB
QA and QB
= ref-div
simultaneously
on
A leading B A lagging B

QA and QB simultaneously high for a short duration

QA QB proportional to

Nagendra Krishnapura Phase locked loop frequency synthesizers

Tri state phase detector with charge pump

Vdd

Icp

1 QA (UP)
D Q
A
ref RST iout
R1 C2

B RST
div
QB (DN)
D Q
1

Icp

C1

QA and QB drive a charge pump

Average current driven into the loop filter is Icp /2

Nagendra Krishnapura Phase locked loop frequency synthesizers

Tri state phase detector implementation

1
D Q CLK Q
CLK RST

D latch with reset and D="1"

CLK S Q Q
R Q

Q S RESET
Q R

(D input with "1" implicit)

Realization using SR latches
RESET
Realization using NOR gates

D flip flops with reset implemented using SR latches

Nagendra Krishnapura Phase locked loop frequency synthesizers

Tri state phase detector-Current source mismatch
Vdd phase offset
in steady state
= ref-div Tref
Icp+I
+1
1 QA (UP) A -1
D Q
A
ref RST iout +1
R1 C2 B
-1

B RST QA
div QB
QB (DN)
D Q Icp+I
1 Itop
Icp-I
Icp-I Ibot

C1 iout
(zero average)

Ideally = 0 under lock in a type-II loop no reference

feedthrough (loop filter input = 0)
Mismatch between top and bottom current sources causes
a non zero = 0 and reference feedthrough

Nagendra Krishnapura Phase locked loop frequency synthesizers

Type-II PLL: transfer functions

2Kpd,I Kvco
L(s) = (1 + sKpd /Kpd,I ) (26)
Ns 2
out (s) 1 + sKpd /Kpd,I
= N (27)
ref (s) K
s2 N
+ s pd + 1
2 Kpd,I Kvco Kpd,I
out (s) N sKpd /Kpd,I
= (28)
Vn,ctl (s) Kpd 2 K
s N
+ s pd + 1
2 Kpd,I Kvco Kpd,I
N
s2
out (s) 2 Kpd,I Kvco
= (29)
vco (s) N Kpd
s2 +s +1
2 Kpd,I Kvco Kpd,I

Nagendra Krishnapura Phase locked loop frequency synthesizers

Type-II PLL: transfer functions

L(s) 1 + sKpd /Kpd,I

= (30)
1 + L(s) K
s2 N
+ s pd + 1
2 Kpd,I Kvco Kpd,I

2 poles and a zero

Zero z1 = Kpd,I /kpd
p
Natural frequency n = 2Kpd,I Kvco /N
p
Quality factor Q = p NKpd,I /2Kvco /Kpd , damping factor
= 1/2Q = Kpd /2 NKpd,I /2Kvco
For well separated (real) poles, p1 Kpd,I /kpd,
p1 2Kpd Kvco /N + Kpd,I /kpd,
Pole zero doublet p1 , z1 ; p1 at a slightly higher frequency
than z1

Nagendra Krishnapura Phase locked loop frequency synthesizers

Type-II PLL: Reference input

2KpdKvco/N
|out/ref|
dB, closed loop gain S(f) dBc/Hz

Kpd,I/Kpd
20log(N)

pole-zero
doublet at

2KpdKvco/N
Kpd,I/Kpd
reference oscillator
phase noise

pll phase noise

out (s) 1 + sKpd /Kpd,I

= N (31)
ref (s) K
s2 N
+ s pd + 1
2 Kpd,I Kvco Kpd,I

Low pass response; Reference noise attenuated at high

frequencies
Low frequency gain of N, -3 dB bandwidth of 2Kpd Kvco /N
Pole zero doublet p1 z1 = Kpd,I /kpd; p1 at a slightly
higher frequency than z1
Nagendra Krishnapura Phase locked loop frequency synthesizers
Type-II PLL: Noise added to control node
dB, loop gain

|out/Vctl|
dB(radians/V)
20log(N/Kpd)

2KpdKvco/N

2KpdKvco/N
zero at Kpd,I/Kpd

Kpd,I/Kpd
+20dB/dec
-20dB/dec

out (s) N sKpd /Kpd,I

= (32)
Vctl (s) Kpd K
s2 N
+ s pd + 1
2 Kpd,I Kvco Kpd,I

radians/Volt
Bandpass response
Mid band gain of N/Kpd
Lower cutoff at Kpd,I /kpd, Upper cutoff at 2Kpd Kvco /N
Nagendra Krishnapura Phase locked loop frequency synthesizers
Type-II PLL: VCO noise
vco phase noise
-30dB/dec.(1/f3)

2KpdKvco/N
|out/vco|
dB S(f) dBc/Hz
-20dB/dec.(1/f2)

Kpd,I/Kpd
+20dB/dec
pll phase noise

0dB

2KpdKvco/N
Kpd,I/Kpd
+10dB/dec

N
s2
out (s) 2 Kpd,I Kvco
= (33)
vco (s) K
s2 N
+ s pd + 1
2 Kpd,I Kvco Kpd,I

Second order highpass response

Feedback loop effectively inactive beyond 2Kpd Kvco /N

Nagendra Krishnapura Phase locked loop frequency synthesizers

Type-II PLL phase noise example

S(f) dBc/Hz S(f) dBc/Hz

total phase noise

2KpdKvco/N
due to vco

2KpdKvco/N
Kpd,I/Kpd

Kpd,I/Kpd
due to
reference oscillator

reference
dominated vco dominated

Nagendra Krishnapura Phase locked loop frequency synthesizers

LC oscillator
L L

C C

RP (GP) GP

-GN
GN GP
for sustained
oscillation
Lossless LC resonator sustains a sinusoidal voltage
indefinitely
LC resonator loss modeled using a parallel resistance Rp
Compensate the loss of a lossy LC resonator using a
parallel negative resistance
Oscillation frequency fo = 1/2 LC
Nagendra Krishnapura Phase locked loop frequency synthesizers
LC resonator losses

L Rs,L C Rs,C
L

C
L C

RP=RP,L||RP,C

RP,L = (L)2/Rs,L QL2 Rs,L RP,C = 1/(L)2Rs,C QC2 Rs,C

Capacitor and Inductor series resistances represented by

equivalent parallel resistances
Effective Rp is a parallel combination of losses from all
components

Nagendra Krishnapura Phase locked loop frequency synthesizers

Negative resistance-implementation

GNv
+
v -GN
-
GNv

transconductance GN
in positive feedback
Transconductor connected in positive feedback

Nagendra Krishnapura Phase locked loop frequency synthesizers

Negative resistance-implementation

-gm/2
-gm/2

gmv/2 gmv/2

v/2 -v/2

gm gm
Itail Itail Itail

Cross coupled differential pair

Negative conductance = gm /2 where gm is the
transconductance of each MOS device

Nagendra Krishnapura Phase locked loop frequency synthesizers

LC oscillator

Vdd
L

GP
-gm/2

Itail

Parallel LC tank with cross coupled differential pair

This and its variants are the most commonly used
topologies of CMOS integrated oscillators

Nagendra Krishnapura Phase locked loop frequency synthesizers

LC oscillator-amplitude

Vdd
L vp-vn

C M1 on
M2 off
GP M1 off
vp vn M2 on
M1 M2

Itail

Complete switching of MOS devices assumed

Equivalent to a square wave current of amplitude I/2
driving the parallel LC tank

Nagendra Krishnapura Phase locked loop frequency synthesizers

LC oscillator-amplitude
sinusoid at fo
Vdd Vdd Vdd
I I I + v(t) -
L L L L

C C C C

GP GP GP GP
vp vn
M1 off M1 on
I/2 I/2 0 M2 on I I M2 off 0 I/2
"bias" point
I/2
vp-vn To
2I/ 2IRP/
I/2
fundamental
driving component differential voltage
current

Nagendra Krishnapura Phase locked loop frequency synthesizers

LC oscillator-amplitude

Equivalent to a square wave current of amplitude I/2

driving the parallel LC tank
All components except the fundamental filtered out
Amplitude of the differential sinusoidal voltage = 2IRP /

Nagendra Krishnapura Phase locked loop frequency synthesizers

LC oscillator-tunability

a b
a b

n+ p+ n+ n+
n- well n- well
p- p-
a b
a b

Tunable using a varactor

Reverse biased p-n junction
MOS device in accumulationlarger tuning range; more
popular in CMOS ICs

Nagendra Krishnapura Phase locked loop frequency synthesizers

Accumulation MOS varactor
a
b
a b
n+ n+ n+ n+ n+
n- well
p-

Wfinger
n+ n+ n+ n+ n+

Lfinger

nMOS in n-well
Multi fingered structure to reduce gate, channel
resistance
W few microns
L > Lmin to reduce parasitics
Gate can be contacted at both ends to further reduce
resistance
Nagendra Krishnapura Phase locked loop frequency synthesizers
MOS varactor with differential excitation
ap
an
b

n+ n+ n+ n+ n+ n+ n+ n+ n+
n- well
p-

ap
an
b ap an

n+ n+
n- well b
p-

0V due to symmetry

Interdigitated fingersalternate ones connected to ap and

an
Region between gates connected to ap and an at 0 V due
to symmetry
All n+ contacts except the ones at the end can be
removed [5]
Smaller structure, lower series resistance, and smaller
parasitic capacitances
Nagendra Krishnapura Phase locked loop frequency synthesizers
On chip inductors

via

Planar inductor on one of the metal layers

Top level metal preferred
Farther from the substrate
Smaller parasitic capacitance
Lesser coupling to substrate, and hence, loss
Thicker top level metal ( 2 m) available in mixed signal
processes
Inductor values up Krishnapura
Nagendra to a couplePhase
of locked
tensloopoffrequency
nH practical
synthesizers on
Inductor loss mechanisms
distributed model: more sections can be added
C

L RS
1 2 1 2

C1 C2

R1 R2

substrate substrate

Winding resistance
R2 L/W
Effective R2 larger due to skin
effect
Copper: 2 m skin depth ( 1/ f ) at 1 ghz
Capacitive coupling to substrate and its resistance
Inductive coupling to (resistive) substrate
Quality factors upto 15 possible, typically 8-10
Use adequate thickness and number of vias during layout

Nagendra Krishnapura Phase locked loop frequency synthesizers

Differential inductor
vias

via via

Symmetrical differential inductor

More compact for a given differential inductance
Larger potential difference between turns larger effect of
interwinding parasitics
Symmetrically laid out single ended inductors
Greater area
Interwinding parasitic capacitance not very significant

Nagendra Krishnapura Phase locked loop frequency synthesizers

Inductor simulation

Some processes have scalable inductor library and models

Typically needs to be simulated from process
parametersmetal thickness, resistivity, intermetal
spacing etc.
Inductance value
FastHenry, Asitic etc.
Accurate estimation possible
Quality factor
FastHenry, Asitic etc.
Harder to accurately estimate losses due to substrate
coupling
Parasitic capacitance
First order parallel plate estimationOK for single ended
inductors
FastCap etc.
Use distributed models for accuracy

Nagendra Krishnapura Phase locked loop frequency synthesizers

VCO design: bias current and transistor sizing

Bias current is a function of tank losses and desired

amplitude
Maximize the inductance for a large amplitude from a small
current
Transistors typically minimum length at high
frequencieslonger to lower 1/f corner
Bias source: longer than minimum length to lower 1/f
noise
Minimize all parasitics to maximize tuning range from the
varactor
Transistor W /L to get the desired gm for startup in the
worst case
Large gm increased phase noise; So dont go crazy!

Nagendra Krishnapura Phase locked loop frequency synthesizers

5 GHz VCO in 0.18 m CMOS
Vdd
1x 5x

4nH differential Vdd

200uA 100 100
output

130fF Vc 130fF
vp vn V-bias

vp vn

L = 4 nH and C = 0.25 pF (differential) chosen

6 turn inductor on top metal layer, 140 m square
From inductor simulations, Q 6
Minimum length transistors

Nagendra Krishnapura Phase locked loop frequency synthesizers

5GHz VCO-inductor

Nagendra Krishnapura Phase locked loop frequency synthesizers

5GHz VCO layout

Nagendra Krishnapura Phase locked loop frequency synthesizers

5GHz VCO layout

Nagendra Krishnapura Phase locked loop frequency synthesizers

VCO (higher freq. version)-measured f vs. V
frequency vs Vctl curve
6.3

6.2

6.1
fvco(in GHz)

5.9

5.8

5.7

5.6
0.5 0 0.5 1 1.5 2
Vctl (V)

Nagendra Krishnapura Phase locked loop frequency synthesizers

VCO-simulated phase noise
Phase Noise
20

30 dB/decade
20
Phase Noise (dBc/Hz)

40

60

80

100 20 dB/decade

120

140 2 3 4 5 6 7
10 10 10 10 10 10
Frequency offset from carrier (Hz)

Nagendra Krishnapura Phase locked loop frequency synthesizers

Programmable divider-Synchronous counter

D Q

combinational logic
D Q

D Q
fin

All of the circuitry running at full speed

Very high power dissipation
Asynchronous operation preferred

Nagendra Krishnapura Phase locked loop frequency synthesizers

Programmable divider-Pulse swallow architecture
M A

fin output
P/P+1 M
fin/N

reset
N=MP+A

Dual modulus prescaler P/P + 1

Divide by P + 1 for A cycles
Divide by P for M A cycles
Full cycle = (P + 1)A + P(M A) = MP + A
Only the dual modulus prescaler running at full speed
Programmability using M and A
Nagendra Krishnapura Phase locked loop frequency synthesizers
References

Behzad Razavi, RF Microelectronics, Prentice Hall, 1998

Behzad Razavi (editor), Monolithic Phase Locked Loops
and Clock Recovery Circuits-Theory and Design, IEEE
Press, 1996.
Behzad Razavi (editor), Phase Locking in High
Performance Systems-From Devices to Architectures, IEEE
Press, 2003
Marc Tiebout, Low Power VCO Design in CMOS (Springer
Series in Advanced Microelectronics) , Springer 2005.
A. S. Porret et al., Design of high-Q varactors for
low-power wireless applications using a standard CMOS
process, IEEE Journal of Solid-State Circuits, pp. 337-345,
Volume 35, Issue 3, March 2000

Nagendra Krishnapura Phase locked loop frequency synthesizers