Aims and Objectives

The aim of this course is to introduce the basics of digital

integrated circuits design.
Introduction to Digital Integrated
Circuit Design After following this course you will be able to:
Comprehend the different issues related to the development of digital
integrated circuits including fabrication, circuit design, implementation
Peter Y K Cheung methodologies, testing, design methodologies and tools and future
Department of Electrical & Electronic Engineering trends.
Imperial College London
Use tools covering the back-end design stages of digital integrated
circuits.

URL: http://www.ee.ic.ac.uk/pcheung/teaching/ee4_asic/index.html
E-mail: p.cheung@imperial.ac.uk

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 1 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 2

Course Outline Recommended Books

Week Lectures Laboratory/Project N. H. E. Weste and D. Harris, CMOS VLSI Design: A Circuits and
Systems Perspective, 3rd Edition, Addison-Wesley, ISBN 0-321-
1 Introduction and Trends 14901-7, May 2004.
2 Basic MOS Theory, SPICE Simulation, CMOS Learning Electric & SPICE J. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits: A
Fabrication simulation Design Perspective 2nd Edition, Prentice Hall, ISBN 0131207644,
3 Inverters and Combinational Logic Learning Layout with Electric January 2003.
W. Wolf, Modern VLSI Design: System-on-Chip Design, 3rd Edition,
4 Sequential Circuits Switch-level simulation with
Prentice Hall, ISBN 0-13-061970-1, 2002.
IRSIM
M.J.S. Smith, Application-Specific Integrated Circuits, Addison-
5 Timing and Interconnect Issues Finishing the previous labs
Wesley, ISBN 0-201-50022-1, 1997.
6 Data Path Circuits Design Project L. A. Glasser and D. W. Dobberpuhl, The Design and Analysis of
7 Memory and Array Circuits Design Project
VLSI Circuits. Addison-Wesley, ISBN 0-201-12580-3, 1985. Detailed
analysis of circuits, but largely nMOS.
8 Low Power Design Design Project C. A. Mead and L. A. Conway, Introduction to VLSI Systems.
Package, Power and I/O Addison-Wesley, ISBN 0-201-04358-0, 1980. The first textbook in this
9 Design for Test Design Project subject, a bit old!
10 Design Methodologies and Tools Design Project
Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 3 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 4
 Supporting Material Design Project

Lectures notes - reference to textbooks if relevant Lab sessions: TBA, Mahanakorn Lab (Level 9)
Material for further reading Spend first 4 weeks learning CAD tools (Electric, IRSIM, SPICE)
Notes for laboratory/project Public domain tools links from course web-page
All tools are installed in the Departmental computers - you are encouraged to install
them on your PCs
Consult the course web-page: Spend the remaining weeks working in small groups to design a chip
Deadline for completion: Last day of Autumn term
Deadline for report: First day of Spring term
http://www.ee.ic.ac.uk/pcheung/teaching/ee4_asic/index
.html Report (one per group) should include:
description of circuit designed (full schematic and layout)
block diagram showing different module in chip
plot of the entire chip
evidence that it works (from simulation plots)
test strategy and testbench
a description of contribution from each member, signed by all!

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 5 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 6

Assessment

May/June examination (open-book) - 75%

Course work designing a chip in a group (3-4 people) - 25%

Topic 1
Introduction & Trends

Peter Y K Cheung
Department of Electrical & Electronic Engineering
Imperial College London

URL: http://www.ee.ic.ac.uk/pcheung/teaching/ee4_asic/index.html
E-mail: p.cheung@imperial.ac.uk

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 7 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 8
 Based on slides/material by Recommended Reading

J. Rabaey http://bwrc.eecs.berkeley.edu/Classes/IcBook/instructors.html J. Rabaey et. al. Digital Integrated Circuits: A Design Perspective:
Digital Integrated Circuits: A Design Perspective, Prentice Hall Chapter 1 (1.1 1.2), Chapter 8

D. Harris http://www.cmosvlsi.com/coursematerials.html Weste and Harris, CMOS VLSI Design: A Circuits and Systems
Weste and Harris, CMOS VLSI Design: A Circuits and Systems Perspective: Chapter 1 (1.1 1.2), Chapter 4 (4.9), Chapter 8 (8.5)
Perspective, Addison Wesley
M. Smith, Application Specific Integrated Circuits : Chapter 1
M. Smith
http://www-ee.eng.hawaii.edu/~msmith/ASICs/HTML/ASICs.htm
Application Specific Integrated Circuits, Addison Wesley

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 9 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 10

Outline Integrated Circuits

History Integrated circuits are made on a thin (a few hundred

microns thick), circular silicon wafer
Implementation methodologies Each wafer holds hundreds of die
Transistors and wiring are made from many layers built on
Design flow
top of one another
Technology scaling Each successive mask layer has a pattern that is defined
using a mask similar to a glass photographic slide
VLSI/IC economics First group of layers define transistors
The remaining layers define metal wires between transistors
Future trends (interconnect)

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 11 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 12
 A Brief History History of Integration

1958: First integrated circuit A gate equivalent is a NAND gate F = A B, or four transistors
Flip-flop using two transistors
Built by Jack Kilby at Texas Instruments small-scale integration (SSI, ~10 gates per chip, 60s)
2003 medium-scale integration (MSI, ~1001000 gates per chip, 70s)
large-scale integration (LSI, ~100010,000 gates per chip, 80s)
Intel Pentium 4 Processor (55 million transistors)
very large-scale integration (VLSI, ~10,000100,000 gates per chip,
512 Mbit DRAM (> 0.5 billion transistors)
90s)
53% compound annual growth rate over 45 years ultra-large scale integration (ULSI, ~1M10M gates per chip)
No other technology has grown so fast so long
Driven by miniaturization of transistors
Smaller is cheaper, faster, lower in power!
Revolutionary effects on society

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 13 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 14

History of Technology IP based SoC Design

bipolar technology and transistortransistor logic (TTL) preceded ...
metal-oxide-silicon (MOS) technology because it was difficult to make Platform 1
Product 3
Product 2
metal-gate n-channel MOS (nMOS or NMOS) Product 1 Product n

the introduction of complementary MOS (CMOS) greatly reduced power

The feature size is the smallest shape you can make on a chip and is
measured in or lambda Software,
hardware
trade-offs
$25m@90nm System, board,
chip optimization

Cell libraries Software

Analog IP Processors
Digital IP Testing
Packaging
Foundry Memory

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 15 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 16
 Annual Sales Any Device, Any Time, Anywhere

1018 transistors manufactured in 2003 Cellular: Voice + Data

100 million for every human on the planet

@ the Office 10/100/GbE

Global Semiconductor Billings

200 802.11b/a/g
Everywhere Else
(Billions of US$)

150
@ Hotspots
@ Home
100
802.11b/a/g Broadband
802.11b/a/g
10/100
50 Cellular

0
1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 Source: Greg Spirakis

Year 2010:
2010:1.5
1.5billion
billion interconnected
interconnectedPCs, PCs,
Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 17 Introduction & Trends 2.5 billion
Introduction interconnected
2.5 billion interconnected PDAs
to Digital Integrated Circuit Design PDAs Topic 1 - 18

Outline Implementation Methodologies

History Digital Circuit Implementation Approaches

Implementation methodologies

Design flow Custom Semi-custom

Technology scaling Cell-Based Array-Based

VLSI/IC economics
Standard Cells Macro Cells Pre-diffused Pre-wired
Future trends Compiled Cells (Gate Arrays) (FPGA)

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 19 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 20
 Full-custom Custom Design - Layout

All mask layers are customized in a full-custom IC.

Full-custom offers the highest performance and lowest part cost

(smallest die size) with the disadvantages of increased design time,
complexity, design expense, and highest risk.

Microprocessors were exclusively full-custom, but designers are

increasingly turning to semi-custom techniques in this area too.

Other examples of full-custom ICs are: high-voltage (automobile),

analog/digital (communications), or sensors and actuators.

Makes sense for performance critical parts or if there are no libraries

available.
Magic Layout Editor
(UC Berkeley)

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 21 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 22

Standard-CellBased ICs Full-custom Standard Cell

In datapath (DP) logic we may use a datapath compiler and a

datapath library. Cells such as arithmetic and logical units (ALUs)
are pitch-matched to each other to improve timing and density.

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 23 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 24
 Routing a Standard Cell-based IC Standard Cell Libraries

Use a design kit from the IC vendor

Buy an IC-vendor library from a library vendor

Build your own cell library

Routing a CBIC (cell-based IC)

A wall of standard cells forms a flexible block
metal2 may be used in a feedthrough cell to cross over cell rows that use
metal1 for wiring
Other wiring cells: spacer cells, row-end cells, and power cells
Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 25 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 26

Macrocell-Based Design Macrocell-Based Design Example

Macrocell
SRAM
Interconnect Bus

Routing Channel
SRAM Data paths

Routing Channel

Standard cells

Video-encoder chip
[Brodersen92]

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 27 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 28
 Gate-ArrayBased ICs Gate-ArrayBased ICs (cont)

A gate array, masked gate array, MGA, or prediffused array uses A channelless gate array (channel-
macros (books) to reduce turnaround time and comprises a base free gate array, sea-of-gates array,
array made from a base cell or primitive cell. There are three types: or SOG array)
Channeled gate arrays Routing uses rows of unused
transistors
Channelless gate arrays
Structured gate arrays

A channeled gate array An embedded gate array or

The interconnect uses predefined
structured gate array (masterslice
spaces between rows of base cells or masterimage)
Either channeled or channelless
Custom blocks (the same for each
design) can be embedded

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 29 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 30

Gate Array Approach - Example Prewired Arrays

Categories of prewired arrays (or field-programmable

polysilicon In1 In2 In3 In4
devices):
VD D
Fuse-based (program-once)
metal

GND
possible
contact Non-volatile EPROM based

Out RAM based

Committed
Uncommited
Cell
Cell
(4-input NOR)

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 31 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 32
 Programmable Logic Devices EPLD Block Diagram

Primary inputs Macrocell

PLA PROM PAL

Courtesy Altera Corp.

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 33 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 34

Field-Programmable Gate Arrays Fuse-based Interconnect

Programmed interconnection Input/output pin

I/O Buffers

Program/Test/Diagnostics
Vertical routes Cell
Antifuse
Standard-cell like
floorplan Horizontal
tracks
I/O Buffers

I/O Buffers

Rows of logic modules

Routing channels

I/O Buffers Vertical tracks

Programming interconnect using anti-fuses

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 35 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 36
 Field-Programmable Gate Arrays RAM-based RAM-based FPGA Basic Cell (CLB)

Combinational logic Storage elements

CLB CLB R
A D in R
Any function of up to
B/Q1/Q2 4 variables
F D Q1
switching matrix C/Q1/Q2
F
G
CE F
Horizontal D

routing
channel A
Any function of up to
B/Q1/Q2 4 variables
R
G
F
Interconnect point C/Q1/Q2 D Q2
G
D G
CE

CLB CLB E Clock

CE

Vertical routing channel

Courtesy of Xilinx

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 37 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 38

Outline Design Abstraction Levels

History SYSTEM

Implementation methodologies

MODULE
Design flow
+

Technology scaling GATE

VLSI/IC economics CIRCUIT

Future trends DE VICE

G
S D
n+ n+

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 39 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 40
 ASIC Design Flow ASIC Design Flow (cont)

A design flow is a sequence of steps to design an ASIC

Design entry.
Logic synthesis.
Pre-layout simulation.
Floorplanning.
Placement.
Routing.
Extraction.
Postlayout simulation.

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 41 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 42

Outline Moores Law

In 1965, Gordon Moore, co-founder of Intel, predicted the exponential growth of the
History
number of transistors on an IC (number of transistors per square inch in ICs to
double every year)
Implementation methodologies Predicted > 65,000 transistors by 1975!
In subsequent years, the pace slowed down a bit, but density has doubled
Design flow approximately every 18 months, and this is the current definition of Moore's Law.
Growth limited by power
Most experts, including Moore himself, expect
Technology scaling
Moore's Law to hold for at least another two
decades
VLSI/IC economics

Future trends

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 43 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 44
 Moores Law Intel Microprocessors Evolution in Complexity

Source: Intel
Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 45 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 46

Why ? Scaling

Why more transistors per IC? The only constant in VLSI/IC design is constant change
Feature size shrinks by 30% every 2-3 years
Smaller transistors
Transistors become smaller, faster, less power hungry, cheaper to
Larger dice manufacture
Why faster computers? Noise, reliability issues 10

Current density goes up 10

Smaller, faster transistors
6

Feature Size (m)

3
Wires do not improve
Better microarchitecture 1.5
(and may get worse) 1
1
0.8
Fewer gate delays per cycle Scale factorS =S 2
0.6
0.35
0.25
0.18
Typically 0.13
0.09
Technology nodes 0.1

1965 1970 1975 1980 1985 1990 1995 2000 2005

Year

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 47 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 48
 Scaling Implications Performance Improvement

10,000

Improved Performance
1,000 4004

Improved Cost 8008

8080

Clock Speed (MHz)

100 8086

Interconnect Woes 80286

Intel386

10 Intel486

Power Woes Pentium

Pentium Pro/II/III

1 Pentium 4

Productivity Challenges

Physical Limits 1970 1975 1980 1985 1990 1995 2000 2005

Year

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 49 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 50

Cost Improvement Interconnect Woes

In 2003, $0.01 bought you 100,000 transistors SIA made a gloomy forecast in 1997
Delay would reach minimum at 250 180 nm, then get worse
because of wires
But
Misleading scale
Global wires
100 kgate blocks ok

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 51 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 52
 Reachable Radius Dynamic Power

We cant send a signal across a large fast chip in one cycle anymore Intel VP Patrick Gelsinger
But the microarchitect can plan around this (ISSCC 2001)
Just as off-chip memory latencies were tolerated If scaling continues at
present pace, by 2005,
high speed processors
would have power
Chip size
density of nuclear
Scaling of
reactor, by 2010, a
reachable radius rocket nozzle, and by
2015, surface of sun.
Business as usual will
not work in the future.
Intel stock dropped 8% on
the next day
But attention to power is
increasing

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 53 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 54

Static Power Productivity

VDD decreases Transistor count is increasing faster than designer

Save dynamic power productivity (gates / week)
Protect thin gate oxides and short channels
Bigger design teams
No point in high value because of velocity sat.
Up to 500 for a high-end microprocessor
Vt must decrease to
More expensive design cost
maintain device performance
Pressure to raise productivity
But this causes exponential
Rely on synthesis, IP blocks
increase in OFF leakage Need for good engineering managers
Major future challenge

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 55 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 56
 Very Few Companies Can Design High-End ICs Less First Silicon Success and the Changing Rate of Failures

Logic/Functional 45%

Design productivity gap

62%

Noise / SI 10% 28%

10,000 100,000
1,000 10,000
Pow er Consumption 8% 22% First silicon success rates
Better
Logic transistors per 100 1000 Clocking
13%
18%
declining
chip 10 Gap 100 Productivity
Functional Verification

Trends are Decreasing

IC capacity (K) Trans./Staff-Mo.
Fast Path 17%
First Silicon OK
(in millions) 1 10
Noisein/ 2000
SI
Slow Path
48%
0.1 1 16%
39% in 2002
Clocking
productivity
0.01 0.1 Analog Tuning
23%
34% in 2003
Source: ITRS99
14%
IR Drops

Trends are Increasing

0.001 0.01 9%
IR Drops Third Silicon OK
14%
Worse
>90% in 2000

1995

1997

1999

2001

2003

2005
1981

1983

1985

1987

1989

1991

1993

2007

2009
Yield / Reliability 12%
>70%
Analog in Tuning
2002
Firmw are
10% >60% in 2003 Interface
Mixed-Signal
Designer productivity growing at slower rate Mixed-Signal
Interf ace 5%
14%
DFM (RET)
1981: 100 designer months ~$1M Other 4% 2003
Collett International Research:
2002: 30,000 designer months ~$300M RET 0%
3% 2001 2000, 2002 Functional Verification Studies;
2003 Design Closure Study, 01/04

0% 10% 20% 30% 40% 50% 60% 70%

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 57 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 58

Physical Limits Outline

Will Moores Law run out of steam? History

Cant build transistors smaller than an atom
Many reasons have been predicted for end of scaling Implementation methodologies
Dynamic power
Subthreshold leakage, tunneling Design flow
Short channel effects
Fabrication costs Technology scaling
Electromigration
Interconnect delay
VLSI/IC economics
Rumors of demise have been exaggerated

Future trends

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 59 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 60
 Integrated Circuits Economics Non-Recurring Engineering Costs (NRE)

Selling price Stotal Engineering cost

Stotal = Ctotal / (1-m) Depends on size of design team
Include benefits, training, computers
m = profit margin CAD tools:
Digital front end: $10K
Analog front end: $100K
Ctotal = total cost Digital back end: $1M
Nonrecurring engineering cost (NRE)
Recurring cost Prototype manufacturing
Fixed cost Mask costs: $500k 1M in 130 nm process
Test fixture and package tooling

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 61 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 62

Recurring Costs Fixed Cost

Fabrication Data sheets and application notes

Wafer cost / (Dice per wafer * Yield)
Wafer cost: $500 - $3000 Marketing and advertising
Dice per wafer: r2 2r
N =
Yield: Y = e-AD A 2A Yield analysis
For small A, Y 1, cost proportional to area
For large A, Y 0, cost increases exponentially

Packaging

Test

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 63 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 64
 New IC Design is Fairly Capital Intensive Cost Breakdown

Estimated capital to start a company to design a wireless communication IC

Digital designers (7): Support staff (5)

$70k salary $45k salary fab salary
$30k overhead $20k overhead 25% 26%
$10k computer $5k computer
$10k CAD tools Total: $70k * 5 = $350k
25%
Total: $120k * 7 = $840k Fabrication 11%
Back-end tools: $1M 4%
Analog designers (3) 9% overhead
Masks: $1M
$100k salary Total: $2M / year backendtools
$30k overhead computer
Summary
$10k computer
2 years @ $3.91M / year entry tools
$100k CAD tools
$8M design & prototype
Total: $240k * 3 = $720k

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 65 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 66

Outline Evolution of Intel Microprocessors

History

Implementation methodologies

Design flow

Technology scaling

VLSI/IC economics Intel Intel

Intel
Intel
Pentium486
4004
Pentium
Intel
8080
286III
II
Intel
IntelPentium
Itanium
Intel 2
Pentium IV
Transistor
Transistor
Transistor
Transistor
Transistor
Transistor count
count
count
countcount
=
countcount
Transistor = =1,200,000
2,300
3,200,000
= 7,500,000
=
6,000
134,000
28,000,000
= 221,000,000
= 42,000,000
Future trends
1971
1974 1982 1989 1993 1997 1999 2002
2000
Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 67 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 68
 Intel Microprocessors Summary Silicon in 2010

104 increase in transistor count, clock frequency over 30 years!

Density Access Time
(Gbits/cm2) (ns)
Die Area: 2.5x2.5 cm DRAM 8.5 10
Voltage: 0.6 V DRAM (Logic) 2.5 10
Technology:0.07 m SRAM (Cache) 0.3 1.5

Density Max. Ave. Power Clock Rate

(Mgates/cm2) (W/cm2) (GHz)
Custom 25 54 3
Std. Cell 10 27 1.5
Gate Array 5 18 1
Single-Mask GA 2.5 12.5 0.7
FPGA 0.4 4.5 0.25
Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 69 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 70

ITRS Summary

Semiconductor Industry Association forecast Integrated circuits are the faster growing technology the last 45 years
Intl. Technology Roadmap for Semiconductors
Different implementation methodologies
Trade-off: design and turn around time vs design density and performance

Abstraction is the basis of design flows and tools

The only constant in VLSI design is scaling

Moores Law and implications

The development of integrated circuits requires large investment

32nm in 2013, what next ?

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 71 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 72
 Journals and Conferences Further Reading

IEEE Journal of Solid State Circuits Original article by Moore

IEICE Transactions on Electronics (Japan)
IEEE Transactions on VLSI Systems
Article on Moores Law
International Solid-State and Circuits Conference (ISSCC)
VLSI Circuits Symposium International Technology Roadmap for Semiconductors (2003 Edition,
Custom Integrated Circuits Conference (CICC) 2004 Update)
European Solid-State Circuits Conference (ESSCIRC)
International ASIC Conference
Assignment: Analysis of ITRS 2003 Edition (or 2004 update)

Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 73 Introduction & Trends Introduction to Digital Integrated Circuit Design Topic 1 - 74