ISSN:2229-6093

P Srikanth et al ,Int.J.Computer Technology & Applications,Vol 3 (3), 1254-1259

Design of Ultra-low Leakage Power Sequential Circuits

P.Srikanth#1, Prof.R.Ramana Reddy#2

Department of ECE, MVGR COLLEGE OF ENGINEERING
Visakhapatnam, A.P., INDIA
1
srikanth3033@gmail.com
2
profrrreddy@yahoo.co.in

Abstract
Reduction in leakage power has become an important
concern in low-voltage, low-power, and high-
performance applications. International Technology
Roadmap for Semiconductors projects that leakage
power consumption may come to dominate total chip
power consumption as the technology feature size
shrinks. A novel approach for ultra-low leakage
CMOS circuit structure is Sleepy keeper. Sleepy
keeper uses traditional sleep transistors plus two
additional transistors driven by a gates already
calculated output to save state during sleep mode.
Dual Vth values can be applied to sleepy keeper in
order to dramatically reduce sub-threshold leakage
current. Unlike many other previous approaches,
sleepy keeper can retain logic state during sleep
mode while achieving ultra-low leakage power
consumption. For applications spending the vast
majority of time in sleep or standby mode, requires
low area, high performance and maintenance of
exact logic state, the sleepy keeper approach
provides a new weapon.
1. Introduction
Power consumption is one of the top concerns of
VLSI circuit design, for which CMOS is the primary
technology. In order to achieve high density and high
performance, CMOS technology feature size and
threshold voltage have been scaling down for
decades. Because of this technology trend, transistor
leakage power has increased exponentially. However,
there is no universal way to avoid tradeoffs between
power, delay, and area, and thus, designers are
required to choose appropriate techniques that satisfy
application and product needs. Power consumption of
CMOS consists of dynamic and static components.
Dynamic power is consumed when transistors are
switching and static power is consumed regardless of
transistor switching. Dynamic power consumption
was previously (at 0.18-m technology and above)
the single largest concern for low-power chip
designers since dynamic power accounted for 90% or
more of the total chip power. Therefore, many
previously proposed techniques, such as voltage and
frequency scaling, focused on dynamic power
reduction. However, as the feature size shrinks, e.g.,
to 0.09 and 0.065m, static power has become a great
challenge for current and future technologies.
There are several VLSI techniques to reduce leakage
power. Each technique provides an efficient way to
reduce leakage power, but disadvantages of each
technique limit the application of each technique. The
proposed new approach, provides a new choice to
low-leakage power VLSI designers. Previous
techniques are summarized and compared with new
approach are presented in this paper.
2. Methodology
This paper evaluates all considered approaches for
a D- Flip Flop and JK Master-Slave Flip Flop using
nand gates and inverters as a test case. The base case
for this test circuit is a basic Complementary Metal
Oxide Semiconductor (CMOS) implementation. In
all approaches, transistors are placed in-between two
parallel rows of continuous VDD and GND. For the
base case, a D-Flip Flop is implemented as the shown
in Fig (1). Different low power techniques are
applied on the same circuit and also on JK Master-
Slave flip flop circuit and the results are compared
for 0.18m, 0.09m, 0.065m & 0.045m
technologies.
3. Previous Work
In order to compare with the sleepy keeper
approach, this section explains several previous
leakage reduction approaches: transistor stacking,
source gating via sleep transistors, selective source
gating via alternating sleep transistors (the so-called
zigzag approach), and a combination of stack and
sleep approach called sleepy stack. Each technique is
described in detail below and the base case of the
nand gate is shown in Fig (2).

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Fig 1.Schematic diagram of D-flip flop (base case)
Fig 2. Two-input NAND gate (base case)
3.1. Sleep Approach
For the sleep approach, transistors gating VDD
and GND are added to the base case. The added
transistors cut off supply of power when in sleep
mode. Each added transistor is referred to as a sleep
transistor and takes the width of the largest
transistor in the base case. As shown in Fig (3) a
PMOS sleep transistor is placed between VDD and
the pull-up network, and an NMOS sleep transistor is
placed between GND and the pull-down network.
The sleep transistors are driven by Sleep (S) and
Sleep (S) signals.
The sleep transistors disconnect the circuit from
VDD and GND when the logic circuit is not in use
(i.e., when in sleep mode). By cutting off the power
source, this technique can reduce leakage power
effectively. However, output will be floating after
sleep mode, so the technique results in destruction of
state plus a floating output voltage.
3.2. Zig-zag Approach
To reduce the wake-up delay of the sleep
transistor technique, the zigzag technique is
introduced. The zigzag technique reduces the wake-
up overhead by choosing a particular circuit state and
then, for the exact circuit state chosen, turning off the
pull-down network for each gate whose output is
high while conversely turning off the pull-up network
for each gate whose output is low. If the output is 1,
then a pull-down sleep transistor is applied; if the
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output is 0, then a pull-up sleep transistor is applied.
By applying, prior to going to sleep, the particular
input pattern chosen prior to chip fabrication, the
zigzag technique can prevent floating.
Although the zigzag technique retains the
particular state chosen prior to chip fabrication, any
other arbitrary state during regular operation is lost in
power-down mode. The zigzag technique may need
extra circuitry to generate a specific input vector. By
using the zigzag approach, the nand gate schematic is
implemented as shown in Fig (4).
.
3.3. Stack Approach
In this every transistor in the base case network
is duplicated with both original and duplicate bearing
half the original transistor width as shown in Fig(5).
Duplicated transistors cause a slight reverse bias
between the gate and source when both transistors are
turned off. Because sub-threshold current is
exponentially dependent on gate bias, a substantial
current reduction is obtained .Since all transistors are
placed in-between two parallel rows of continuous
VDD and GND, stack approach design forces an
increase in row length because of an increase in the
number of transistors and decrease in transistor width
which increases the delay significantly and could
limit the usefulness of the approach.
3.4. Sleepy Stack Approach
The circuit of sleepy stack approach for low
leakage power design is shown Fig (6) below. The
sleepy stack approach has a structure combining the
stack and sleep approaches by dividing every
transistor into two transistors of half width and
placing a sleep transistor in parallel with one of the
divided transistor. As shown in Fig (6), sleep
transistors are placed in parallel to the divided
transistor closest to VDD for pull-up and in parallel
to the divided transistor closest to GND for pull-
down. The stacked transistors suppress leakage
current while saving state. While each sleep transistor
placed in parallel to the one of the stacked transistors,
reduces resistance of the path, so delay is decreased
during active mode. However, area penalty is a
significant matter for this approach since every
transistor is replaced by three transistors.
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P Srikanth et al ,Int.J.Computer Technology & Applications,Vol 3 (3), 1254-1259

4. Proposed Approach-Sleepy Keeper

The structure of the proposed sleepy keeper
approach is shown in the Fig (7) below. The basic
problem with traditional CMOS is that the transistors
are used only in their most efficient, and naturally
inverting, way: namely, PMOS transistors connect to
VDD and NMOS transistors connect to GND. It is
well known that PMOS transistors are not efficient at
passing GND; similarly, NMOS transistors are not
efficient at passing VDD.
Fig 3. Two-input NAND gate (Sleep)

Fig 4. Two-input NAND gate (Zig-Zag) Fig 7. Sleepy keeper approach

The advantages of this approach are Ultra-low

leakage with dual Vth, State-saving, less area penalty
and faster than sleepy stack approach. Sleepy keeper
approach for the design of the nand gate schematic is
as shown below in Fig (8). For the sleep, zigzag and
sleepy, dual Vth technology can be applied to obtain
greater leakage power reduction. Since high-Vth
results in less leakage but lowers performance, high-
Vth is applied only to leakage reduction transistors,
which are sleep transistors, and any transistors in
parallel to the sleep transistors; on the other hand,
low-Vth is applied to the remaining transistors to
maintain logic performance.

Fig 5. Two-input NAND gate (Stack)

Fig 6. Two-input NAND gate (Sleepy Stack) Fig 8. Sleepy Keeper approach for Nand gate

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P Srikanth et al ,Int.J.Computer Technology & Applications,Vol 3 (3), 1254-1259

5. Experimental Results Table 3. Results for D-flip flop (65nm)

In order to compare the results of proposed
approach with prior leakage reduction approaches 65nm De lay(s)
Static Dynamic
Are a(m 2 )
like, stack, sleep, zigzag, sleepy stack and leakage Powe r (W) Powe r (W)
Base Case 8.53E-11 3.53E-08 9.98E-07 1.25E+02
feedback approaches experiments are carried out
Stack 2.14E-10 4.92E-09 8.51E-07 2.93E+02
considering D-Flip Flop as a base case. The nand Sle e p 1.24E-10 1.19E-08 1.12E-06 2.41E+02
gate with sleepy keeper approach along with their Zigz ag 1.07E-10 1.34E-08 1.09E-06 1.89E+02
transistor sizes shown in Figure (8) is used in D-Flip Sle e py Stack 1.53E-10 7.66E-09 8.32E-07 4.61E+02
Flop in Fig (1) and JK Master-Slave flipflop in Sle e py Ke e pe r 1.37E-10 5.24E-09 6.01E-07 3.26E+02
Fig(9). Schematics are designed for all considered Sle e p dVth 2.60E-10 4.70E-11 1.30E-06 2.41E+02
Zigz ag dVth 1.96E-10 1.50E-10 1.31E-06 1.89E+02
techniques using TANNER EDA tool and netlists of
SS dVth 3.62E-10 1.13E-10 8.52E-07 4.61E+02
test circuits for different techniques are extracted SK dVth 3.07E-10 1.21E-10 6.97E-07 3.26E+02
from the schematics. The netlists are modified to fit
into all silicon technologies targeted using the
Table 4. Results for D-flip flop (45nm)
BPTM. HSPICE simulation is used to estimate delay
and power consumption. Experimental results for
Static Dynamic
delay, static power, dynamic power and area for D- 45nm De lay(s)
Powe r (W) Powe r (W)
Are a(m 2 )
Flip Flop are presented in Fig (10-13) and JK Master- Base Case 6.58E-12 1.83E-06 2.39E-06 5.98E+01
Slave flip flop in Fig (14-17). Stack 4.16E-11 2.96E-07 4.69E-07 1.40E+02
Sle e p 1.95E-11 6.07E-07 2.25E-06 1.16E+02
Zigz ag 9.74E-12 7.26E-07 2.35E-06 9.05E+01
Sle e py Stack 1.98E-11 4.42E-07 1.11E-06 2.21E+02
Sle e py Ke e pe r 1.97E-11 2.74E-07 1.09E-06 1.56E+02
Sle e p dVth 2.27E-11 1.59E-08 2.20E-06 1.16E+02
Zigz ag dVth 7.18E-12 3.16E-08 2.36E-06 9.05E+01
SS dVth 3.08E-11 2.12E-08 1.02E-06 2.21E+02
SK dVth 2.72E-11 1.18E-08 1.06E-06 1.56E+02

Fig 9. Schematic diagram of JK Master-Slave

Table 1. Results for D-flip flop (180nm)

Static Dynamic
180nm De lay(s) Are a(m 2 )
Powe r (W) Powe r (W)
Base Case 6.00E-11 8.22E-09 1.72E-05 8.71E+02
Stack 1.57E-10 6.84E-10 1.34E-05 2.04E+03
Sle e p 8.46E-11 1.14E-09 1.84E-05 1.68E+03
Zigz ag 7.25E-11 1.81E-09 1.89E-05 1.32E+03
Sle e py Stack 1.17E-10 1.19E-09 1.37E-05 3.21E+03 Fig 10. Propagation delay of D-flip flop
Sle e py Ke e pe r 1.02E-10 4.37E-10 1.04E-05 2.27E+03
Sle e p dVth 9.85E-11 1.95E-12 1.90E-05 1.68E+03
Zigz ag dVth 7.77E-11 1.65E-12 1.97E-05 1.32E+03
SS dVth 1.33E-10 2.48E-12 1.31E-05 3.21E+03
SK dVth 1.21E-10 4.20E-12 1.08E-05 2.27E+03

Table 2. Results for D-flip flop (90nm)

Static Dynamic
90nm De lay(s) Are a(m 2 )
Powe r (W) Powe r (W)
Base Case 5.71E-11 7.34E-09 1.54E-06 2.39E+02
Stack 1.46E-10 4.23E-10 1.34E-06 5.62E+02
Sle e p 8.20E-11 8.14E-10 1.66E-06 4.62E+02
Zigz ag 7.07E-11 1.38E-09 1.65E-06 3.62E+02 Fig 11. Static power of D-flip flop
Sle e py Stack 1.07E-10 7.46E-10 1.27E-06 8.83E+02
Sle e py Ke e pe r 9.52E-11 3.49E-10 9.54E-07 6.24E+02
Sle e p dVth 1.12E-10 9.80E-13 1.73E-06 4.62E+02
Zigz ag dVth 9.34E-11 9.17E-13 1.75E-06 3.62E+02
SS dVth 1.50E-10 2.17E-12 1.24E-06 8.83E+02
SK dVth 1.32E-10 2.03E-12 1.01E-06 6.24E+02

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P Srikanth et al ,Int.J.Computer Technology & Applications,Vol 3 (3), 1254-1259

Table 7. Results for JK Master-Slave (65nm)

Static Dynamic
65nm De lay(s) Are a(m 2 )
Powe r (W) Powe r (W)
Base Case 1.76E-10 9.55E-07 2.67E-06 3.42E+02
Stack 5.53E-10 4.11E-07 2.33E-06 7.49E+02
Sle e p 3.24E-10 2.43E-08 4.30E-06 5.70E+02
Zigz ag 2.72E-10 3.06E-08 2.59E-06 5.04E+02
Sle e py Stack 3.80E-10 1.43E-08 2.58E-06 1.28E+03
Sle e py Ke e pe r 3.29E-10 1.14E-08 1.52E-06 8.11E+02
Sle e p dVth 8.55E-10 9.00E-11 2.85E-06 5.70E+02
Zigz ag dVth 7.17E-10 2.74E-10 3.01E-06 5.04E+02
SS dVth 1.04E-09 3.00E-10 2.06E-06 1.28E+03
Fig 12. Dynamic power of D-flip flop SK dVth 8.42E-10 6.41E-11 1.85E-06 8.11E+02

Table 8. Results for JK Master-Slave (45nm)

Static Dynamic
45nm De lay(s) Are a(m 2 )
Powe r (W) Powe r (W)
Base Case 1.95E-11 2.32E-05 4.14E-06 1.64E+02
Stack 6.87E-11 3.07E-06 9.20E-07 3.59E+02
Sle e p 3.73E-11 1.37E-06 4.03E-06 2.73E+02
Zigz ag 3.35E-11 1.57E-06 4.11E-06 2.41E+02
Sle e py Stack 4.23E-11 8.73E-06 2.92E-06 6.12E+02
Sle e py Ke e pe r 3.73E-11 5.95E-07 3.12E-06 3.89E+02
Sle e p dVth 4.92E-11 3.12E-08 3.95E-06 2.73E+02
Zigz ag dVth 3.91E-11 8.07E-08 4.05E-06 2.41E+02
SS dVth 5.54E-11 1.45E-06 2.56E-06 6.12E+02
Fig 13. Area of D-flip flop SK dVth 5.21E-11 1.88E-08 1.90E-06 3.89E+02

Table 5. Results for JK Master-Slave (180nm)

Static Dynamic
180nm De lay(s) Are a(m 2 )
Powe r (W) Powe r (W)
Base Case 1.19E-10 2.05E-04 1.00E-04 2.39E+03
Stack 3.89E-10 1.10E-09 3.51E-05 5.22E+03
Sle e p 2.06E-10 1.97E-09 3.64E-05 3.97E+03
Zigz ag 1.84E-10 3.51E-09 4.00E-05 3.51E+03
Sle e py Stack 2.97E-10 1.84E-09 3.30E-05 8.90E+03
Sle e py Ke e pe r 2.27E-10 9.02E-10 2.39E-05 5.65E+03
Sle e p dVth 2.73E-10 3.87E-12 4.49E-05 3.97E+03
Zigz ag dVth 2.27E-10 6.87E-12 3.66E-05 3.51E+03
SS dVth 3.38E-10 8.70E-12 3.16E-05 8.90E+03
SK dVth 2.83E-10 4.03E-12 2.44E-05 5.65E+03
Fig 14. Propagation delay of JK Master-Slave

Table 6. Results for JK Master-Slave (90nm)

Static Dynamic
90nm De lay(s) Are a(m 2 )
Powe r (W) Powe r (W)
Base Case 1.18E-10 8.83E-06 3.30E-06 6.57E+02
Stack 3.68E-10 7.58E-10 3.67E-06 1.44E+03
Sle e p 2.08E-10 1.70E-09 4.32E-06 1.09E+03
Zigz ag 1.76E-10 3.18E-09 4.28E-06 9.66E+02
Sle e py Stack 2.74E-10 1.32E-09 3.65E-06 2.45E+03
Sle e py Ke e pe r 2.18E-10 8.76E-10 2.41E-06 1.55E+03
Sle e p dVth 3.34E-10 1.91E-12 4.13E-06 1.09E+03
Zigz ag dVth 2.85E-10 2.00E-12 4.08E-06 9.66E+02
SS dVth 3.87E-10 5.16E-12 3.17E-06 2.45E+03
SK dVth 3.47E-10 1.09E-12 2.48E-06 1.55E+03
Fig 15. Static power of JK Master-Slave

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P Srikanth et al ,Int.J.Computer Technology & Applications,Vol 3 (3), 1254-1259
Fig 16. Dynamic power of JK Master-Slave
Fig 17. Static power of JK Master-Slave
6. Conclusions
Scaling down of the CMOS technology feature
size and threshold voltage for achieving high
performance has resulted in increase of leakage
power dissipation. This paper presents an efficient
methodology for reducing leakage power in VLSI
design. The sleepy keeper technique results in ultra
low static power consumption with state saving.
Furthermore, the sleepy keeper approach is
applicable to single and multiple threshold voltages.
With application of dual Vth, sleepy keeper is the
most efficient approach to reduce leakage current
with the smallest delay and area increases while
simultaneously preserving precise logic state in sleep
mode. In terms of area, the sleepy keeper approach is
expected to be more attractive for complex logic
circuits, because the portion of increased area for the
required additional transistors will be smaller for
complex logic circuits than for simple logic circuits
(e.g., for an inverter). For the future work, the plan to
investigate why the sleepy keeper approach increases
dynamic power consumption over the sleepy stack
approach, aiming to reduce this increase in dynamic
power consumption.
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7. References
[1] Se Hun Kim, Vincent J. Mooney III Sleepy Keeper: a
New Approach to Low-leakage Power VLSI Design, VLSI,
2006 IFIP international conference.
[2] J.C. Park, V. J. Mooney III and P. Pfeiffenberger,
Sleepy Stack Reduction of Leakage Power, Proceeding
of the International Workshop on Power and Timing
Modeling, Optimization and Simulation, pp.148-158,
September 2004. N. Azizi, A. Moshovos, F. N. Najm.
[3] S.Nadara, S. Borkar, V. De, D. Antoniadis and A.
Chandrakasan, Scaling of Stack Effect and its Application
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[4] K.S. Min, H. Kawaguchi and T. Sakurai, Zigzag Super
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Adaptive Voltage Level Controller: An Alternative to
Clock-gating Scheme in Leakage Dominant Era, IEEE
International Solid-State Circuits Conference, pp. 400-401,
February 2003.
[5] Berkeley Predictive Technology Model (BPTM),
http://www.eas.asu.edu/~ptm/.
[6] International Technology Roadmap for Semiconductors
by Semiconductor Industry Association,
http://public.itrs.net
[7] Z. Chen, M. Johnson, L. Wei and K. Roy, Estimation
of Standby Leakage Power in CMOS Circuits Considering
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[8] N. S. Kim et al., Leakage Current: Moores Law
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[9] A. P. Chandrakasan, S. Sheng, and R. W. Brodersen,
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