DESING REVIEW CHECKLIST TEMPLATE

File name: PCB Design Review - Template 2.Docx

Creation date: 02/23/2012 16:00:00 AM
Last saved: 2/23/2012 3:09:00 PM
Minutes Prepared By:
Review Team:

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1 General Action

1.1 Copyright notice on PCB in copper.

1.2 Date code on PCB in copper.

1.3 PCB ID number and layer number on each layer in copper.

1.4 Drill legend - what sizes are used?

1.5 Netlist check - automatic and manual. Look for nets with single nodes or too many nodes.

1.6 Design rule check. A manual version can find problems missed by automatic checks.

1.7 Check for dead-end traces.

1.8 Ensure schematic software did / did not separate Vcc from Vdd, Vss from GND as needed.

2 Sizing Action

2.1
When determining board size go for a larger board within reason. This decreases time to layout

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or auto route, populate, debug and maintain. Small size is cute but not always needed.

Consider PCB manufacturing panel sizes when deciding on PCB sizes. (Minimize wastage of
PCB's per panel).

2.2 Holes on layout are probably finished sizes, after plating.

Finished hole sizes are >=10 thou larger than the lead, or larger spec dictated by automatic
2.3 insertion gear.

2.4 Pads >=15 thou larger than finished hole sizes.

2.5 Place thru hole components on 50 thou grid.

2.6 All components >= 0.2" from edge of PCB.

2.7 Silk screen legend text weight >=10 thou.

2.8 Check layout rules with your pcb manufacturer.

3 Mounting Check

3.1 Are mounting holes electrically isolated or grounded?

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Allow proper mounting hole clearance for hardware. Allow space around them for stand off
3.2 mounts, washers, brackets.

3.3 All polarized components checked.

3.4 No acute inside angles in foil.

3.5 No traces within 20 thou of PCB edge.

3.6 Serial number blank on silk screen legend.

3.7 Thru hole drill tolerance noted.

3.8 Thru hole solder mask tolerance noted.

3.9 Thru hole route tolerance noted.

3.10 Thru hole silk screen legend tolerance noted.

3.11 Use ground planes where possible.

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4 Components Check

4.1 Mounting holes matched 1:1 with mating parts.

4.2 All polarized components point same way.

4.3 Use but ensure there is minimum component body spacing.

4.4 Clearance for IC extraction tools.

Clearance for IC sockets (especially for during proto phase). Sufficient clearance for socketed
4.5 ICs.

4.6 Sockets used on devices prone to damage (near I/O connectors).

4.7 CPU devices usually socketed to allow bus testing, emulator etc.

4.8 Visual references for automated assembly (future auto placement).

4.9 Tooling holes for automated assembly (future auto placement).

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Tooling and mounting holes have internal plane clearance to avoid multilayer shorts. (Expect
4.10
the software to look after this, but check it).

Ensure pin 1 interpretation and orientation consistent among all connectors of a given type on
4.11
the board.

4.12 All ICs have pin one marking visible when chip is installed.

4.13 Standoffs on power resistors or other hot components.

4.14 Check power and ground connections to all ICs.

4.15 Check hole diameters for odd components: rectangular pins, spring pins.

5 Tracks and EMI Check

5.1 Trace width sufficient for current carried, consider trace heating especially on internal layers

5.2 Thermal relief's for internal power layers.

5.3 Clearance for high voltage traces.

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Clearance and guards between noisy and quiet lines. Noisy ones to note are the capacitors on
5.4 negative rail 7661 chips, RS232 lines, digital lines and busses. Keep noisy lines short.

Bypass capacitors located close to IC power pins. Minimize loop areas of decoupling
capacitors.

High frequency crystal cases should be flush to the PCB and grounded so they don't become
5.5 an antenna.

5.6 Check for traces running under noisy or sensitive components.

5.7 Use guard tracks round high impedance and low noise lines. Keep them short.

5.8 Component and trace keepout areas observed.

5.9 Digital and analog signal commons joined at only one point.

5.10 Place I/O devices near where their signals leave the board.

EMI and RFI filtering as close as possible to exit and entry points of shielded areas, I/O
5.11
connectors.

5.12 Provide multiple vias for high current and/or low impedance traces.

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5.13 Consider ground loops and voltage drops on tracks - ground ain't ground.

6 Testability Check

6.1 Provide a ground test point, accessible and sized for scope ground clip.

6.2 Potentiometers should increase controlled quantity clockwise.

6.3 Check the orientation of all connectors using actual connector/cable.

6.4 Silkscreen text located to be readable when the board is populated.

6.5 No vias under metal-film resistors and similar poorly insulated parts.

6.6 Check for traces which may be susceptible to solder bridging.

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