library ieee;

use ieee.std_logic_1164.all;

entity dff is
port(clk,d:in std_logic;
q:out std_logic);
end dff;

architecture structure of dff is

begin
p1:process(clk)
begin
if (clk 'event and clk = '1') then
q <= d;
end if;
end process p1;
end structure;

library ieee;
use ieee.std_logic_1164.all;

entity dff is
port(clk,d:in std_logic;
reset:in std_logic;
q,q':out std_logic);
end dff;

architecture structure of dff is

begin
p1:process(clk,reset)
begin
if (reset = '0' ) then
q <= '0';
q' <= '1';
else if (clk 'event and clk = '1') then
q <= d;
q' <=not(d);
end if;
end process p1;
end structure;

library ieee;
use ieee.std_logic_1164.all;

entity myNAND is
port(a,b:in std_logic;
c:out std_logic);
end myNAND;

architecture myNAND1 of myNAND is

begin
c <= not(a and b);
end myNAND1;
library ieee;
use ieee.std_logic_1164.all;

entity my_trigate is
port(a,en:in std_logic;
c:out std_logic);
end my_trigate;

architecture structure of my_trigate is

begin
process(a,en)
begin
if(en = '1')then
c <= a;
else
c <= 'Z'; //
end if;
end process;
end structure;
library ieee;
use ieee.std_logic_1164.all;

entity mydecoder_8 is
port(d:in std_logic_vector(7 downto 0);
q:out std_logic_vector(2 downto 0));
end mydecoder_8;

architecture structure of mydecoder_8 is

begin
process(d)
begin
case d is
when "01111111" => q <= "111";
when "10111111" => q <= "110";
when "11011111" => q <= "101";
when "11101111" => q <= "100";
when "11110111" => q <= "011";
when "11111011" => q <= "010";
when "11111101" => q <= "001";
when "11111110" => q <= "000";
when others => q <= "ZZZ";
end case;
end process;
end structure;
library ieee;
use ieee.std_logic_1164.all;

entity t_trigger is
port(t,clk:in std_logic;
q,qb: out std_logic);
end t_trigger;

architecture structure of t_trigger is

signal q_temp,qb_temp:std_logic;
begin
process(clk)
begin
if( clk 'event and clk = '1')then
if(t = '1')then
q_temp <= Not q_temp;
qb_temp <= Not qb_temp;
else
q_temp <= q_temp;
qb_temp <= qb_temp;
end if;
end if;
q_temp <= q_temp;
qb_temp <= qb_temp;
end process;
end structure;

library ieee;
use ieee.std_logic_1164.all;

entity mychooser is
 port(s0,s1:in std_logic;
d0,d1,d2,d3:in std_logic;
y:out std_logic);
end mychooser;

architecture structure of mychooser is

begin
process(s0,s1,d0,d1,d2,d3)
begin
if( s0 = '0' and s1 = '0' )then
y <= d0;
end if;
if( s0 = '0' and s1 = '1' )then
y <= d1;
end if;
if( s0 = '1' and s1 = '0' )then
y <= d2;
end if;
if( s0 = '1' and s1 = '1' )then
y <= d3;
end if;
end process;
end structure;

library ieee;
use ieee.std_logic_1164.all;

entity mycompare is
port(a:in std_logic;
b:in std_logic;
y:out std_logic_vector(2 downto 0));
end mycompare;

architecture structure of mycompare is

begin
process(a,b)
begin
if( a = b )then
y <= "001";
end if;
 if( a > b )then
y <= "010";
end if;
if( a < b )then
y <= "100";
end if;
end process;
end structure;

//Program 1. Lighting a LED at first

library ieee;
use ieee.std_logic_1164.all;

entity led2 is
port
(
led:out std_logic_vector(2 downto 0)
);
end entity;

architecture behave of led2 is

begin
led<="001"; -- 0 means on and 1 means off.
end behave;

library ieee;
use ieee.std_logic_1164.all;

//Program 2. Button test

entity led2 is
port
(
key:in std_logic;
led:out std_logic_vector(2 downto 0)
);
end entity;
architecture behave of led2 is
begin
process(key)
begin
if (key = '1') then
led<="000";
else
led<="111";
end if;
end process;
end behave;

//Program 3. Press button then the led on

library ieee;
use ieee.std_logic_1164.all;

entity led2 is
port
(
key:in std_logic_vector(2 downto 0);
led:out std_logic_vector(2 downto 0)
);
end entity;

architecture behave of led2 is

begin
process(key)
begin
case key is
when "000" => led <= "000"; -- Push down the button is 0
when "001" => led <= "001";
when "010" => led <= "010";
when "100" => led <= "100";
when "101" => led <= "101";
when "110" => led <= "110";
when "111" => led <= "111";
when others => led <= "XXX";
end case;
end process;
end behave;

//Program 4. Real Time Simulation

library ieee;
use ieee.std_logic_1164.all;

entity led2 is
port
(
clk:in std_logic;
led:out std_logic_vector(2 downto 0);
sound:out std_logic
);
end entity;

architecture behave of led2 is

signal frequency_flag:std_logic;
signal sound_flag:std_logic;

begin

P1:process(clk)
variable div_1:integer range 0 to 99999999;
begin
if clk'event and clk = '1'then
frequency_flag <= '0';
div_1 := div_1 + 1;
end if;
if div_1 >= 99999999 then
frequency_flag <= '1';
div_1 := 1;
end if;
end process P1;

P2:process(frequency_flag)
variable count:integer range 0 to 8;
begin
if frequency_flag = '1' then
count := count + 1;
sound_flag <= '0';
end if;
if count >= 8 then
count := 0;
sound_flag <= '1';
end if;

case count is
when 0 => led <= "111";
when 1 => led <= "110";
when 2 => led <= "101";
when 3 => led <= "100";
when 4 => led <= "011";
when 5 => led <= "010";
when 6 => led <= "001";
when 7 => led <= "000";
when others => led <= "XXX";
end case;
end process P2;

P3:process(sound_flag)
begin
 if sound_flag = '1' then
sound <= '0';
else
sound <= '1';
end if;
end process P3;

end behave;

//Program 5. PWM Test

library ieee;
use ieee.std_logic_1164.all;

entity led2 is
port
(
clk:in std_logic;
led:out std_logic_vector(2 downto 0)
);
end entity;

architecture behave of led2 is

signal frequency_flag:std_logic;
signal pwm:std_logic;
begin
P1:process(clk)
variable div_1:integer range 0 to 9999;
begin
if clk'event and clk = '1'then
frequency_flag <= '0';
div_1 := div_1 + 1;
end if;

if div_1 <= 1000 then

led(0) <= '0';
pwm <= '0';
elsif div_1 > 1000 and div_1 < 9999 then
led(0) <= '1';
pwm <= '1';
 end if; -- 1000 to 3000 is better

if div_1 >= 9999 then

frequency_flag <= '1';
div_1 := 1;
end if;

led(1) <= pwm;

led(2) <= pwm;

end process P1;

end behave;
//Program 6. Mode Modulation!

library ieee;
use ieee.std_logic_1164.all;

entity led2 is
port
(
clk:in std_logic;
mode:in std_logic;
reset:in std_logic;
led:out std_logic_vector(2 downto 0)
);
end entity;

architecture behave of led2 is

signal frequency_flag:std_logic;

begin

P1:process(clk)
variable div_1:integer range 0 to 29999999;
begin
if clk'event and clk = '1' then
frequency_flag <= '0';
div_1 := div_1 + 1;
end if;
if div_1 >= 29999999 then
frequency_flag <= '1';
div_1 := 1;
end if;
end process P1;

P2:process(frequency_flag)
variable count:integer range 0 to 8;
begin
if frequency_flag = '1' then
count := count + 1;
if count >= 8 then
count := 0;
end if;
if mode = '1' then
case count is
when 0 => led <= "111";
when 1 => led <= "110";
when 2 => led <= "101";
 when 3 => led <= "100";
when 4 => led <= "011";
when 5 => led <= "010";
when 6 => led <= "001";
when 7 => led <= "000";
when others => led <= "XXX";
end case;
end if;
if mode = '0' then
case count is
when 0 => led <= "000";
when 1 => led <= "001";
when 2 => led <= "010";
when 3 => led <= "011";
when 4 => led <= "100";
when 5 => led <= "101";
when 6 => led <= "110";
when 7 => led <= "111";
when others => led <= "XXX";
end case;
end if;
end if;
if reset = '0' then
led <= "000";
end if;
end process P2;

end behave;

//Program 7. Cymometer for Frequency and PWM Duty!

library ieee;
use ieee.std_logic_1164.all;

entity led2 is
port
(
clk:in std_logic;
pulse:in std_logic;
led:out std_logic
);
end entity;

architecture behave of led2 is

signal frequency_flag:std_logic;
signal on_flag:std_logic;
signal off_flag:std_logic;
begin

P1:process(clk)
variable div_1:integer range 0 to 9999999;
begin
if clk'event and clk = '1'then
frequency_flag <= '0';
div_1 := div_1 + 1;
end if;
if div_1 >= 9999999 then
frequency_flag <= '1';
div_1 := 1;
end if;
end process P1; -- Setting Gate Period

P2:process(frequency_flag,pulse)
variable count:integer range 0 to 9999999;
begin
if pulse 'event and pulse = '1' then
count := count + 1;
end if;
if frequency_flag = '1' then
count := 0;
end if;

if count >= 10 then

led <= '0';
else
led <= '1';
end if;
end process P2;

capture:process(pulse)
begin
if pulse 'event and pulse = '1' then
on_flag <= '1';
off_flag <= '0';
elsif pulse 'event and pulse = '0' then
on_flag <= '0';
off_flag <= '1';
end if;
end process capture;

P3:process(on_flag,off_flag,clk)
variable pwm_on:integer range 0 to 9999999;
variable pwm_period:integer range 0 to 9999999;
variable chance:integer range 0 to 1;
begin
if on_flag = '1' then
chance := chance + 1;
if chance = 1 then
if clk 'event and clk = '1' then
pwm_on := pwm_on + 1;
pwm_period := pwm_period + 1;
end if;
end if;
if chance > 1 then
pwm_on := 0;
 pwm_period := 0;
chance := 0;
end if;
end if;

if off_flag = '1' and pwm_on > 0 then

pwm_period := pwm_period + 1;
end if;
end process P3;
end behave;

[1] System
library ieee;
use ieee.std_logic_1164.all;

entity system is
port
(
clk_in:in std_logic;
mode:in std_logic;
reset:in std_logic;
led:out std_logic_vector(2 downto 0)
);
end entity;

architecture structure of system is

component clock_div_for_timer
port
(
clk_in:in std_logic;
clk_div_timer:out std_logic
);
end component;

component clock_div_for_pwm
port
(
clk_in:in std_logic;
clk_div_pwm:out std_logic
);
end component;

component mode_led
port
(
clk_div_timer:in std_logic;
clk_div_pwm:in std_logic;
mode:in std_logic;
reset:in std_logic;
led:out std_logic_vector(2 downto 0)
);
end component;

signal clk_div_timer:std_logic;
signal clk_div_pwm:std_logic;

begin

system_clock_div_for_timer:clock_div_for_timer
port map
(
clk_in => clk_in,
clk_div_timer => clk_div_timer
);

system_clock_div_for_pwm:clock_div_for_pwm
port map
(
clk_in => clk_in,
clk_div_pwm => clk_div_pwm
);

system_mode_led:mode_led
port map
(
clk_div_timer => clk_div_timer,
clk_div_pwm => clk_div_pwm,
mode => mode,
reset => reset,
led => led
);
end structure;

[2] clock_div_for_timer
library ieee;
use ieee.std_logic_1164.all;

entity clock_div_for_timer is
port
(
clk_in:in std_logic;
clk_div_timer:out std_logic
);
end entity;

architecture structure of clock_div_for_timer is

signal frequency_timer:std_logic;

begin

P1:process(clk_in)
variable count : integer range 0 to 9999999;
begin
if clk_in 'event and clk_in = '1' then
count := count + 1;
frequency_timer <= '0';
end if;
if count >= 9999999 then
count := 0;
frequency_timer <= '1';
end if;
end process P1;

P2:process(frequency_timer)
begin
if frequency_timer = '1' then
clk_div_timer <= '1';
else
clk_div_timer <= '0';
end if;
end process P2;

end structure;

[3] clock_div_for_pwm
library ieee;
use ieee.std_logic_1164.all;

entity clock_div_for_pwm is
port
(
clk_in:in std_logic;
clk_div_pwm:out std_logic
);
end entity;

architecture structure of clock_div_for_pwm is

begin
 P1:process(clk_in)
variable count:integer range 0 to 9999;
begin
if clk_in 'event and clk_in = '1' then
count := count + 1;
if count < 4000 then
clk_div_pwm <= '1';
end if;
if count > 4000 and count < 9999 then
clk_div_pwm <= '0';
end if;
if count >= 9999 then
count := 0;
end if;
end if;
end process P1;

end structure;

[4] mode_led
library ieee;
use ieee.std_logic_1164.all;

entity mode_led is
port
(
clk_div_timer:in std_logic;
clk_div_pwm:in std_logic;
mode:in std_logic;
reset:in std_logic;
led:out std_logic_vector(2 downto 0)
);
end entity;

architecture structure of mode_led is

begin

P1:process(clk_div_timer)
variable count : integer range 0 to 8;
begin
if clk_div_timer 'event and clk_div_timer = '1' then
count := count + 1;
if count >= 8 then
count := 0;
end if;
if reset = '1' then
led <= "111";
end if;
if mode = '0' then
case count is
when 0 => led(0) <= '1';
led(1) <= '1';
led(2) <= '1';
when 1 => led(0) <= clk_div_pwm;
led(1) <= '1';
led(2) <= '1';
when 2 => led(0) <= '1';
led(1) <= clk_div_pwm;
led(2) <= '1';
 when 3 => led(0) <= clk_div_pwm;
led(1) <= clk_div_pwm;
led(2) <= '1';
when 4 => led(0) <= '1';
led(1) <= '1';
led(2) <= clk_div_pwm;
when 5 => led(0) <= clk_div_pwm;
led(1) <= '1';
led(2) <= clk_div_pwm;
when 6 => led(0) <= '1';
led(1) <= clk_div_pwm;
led(2) <= clk_div_pwm;
when 7 => led(0) <= clk_div_pwm;
led(1) <= clk_div_pwm;
led(2) <= clk_div_pwm;
when others => led <= "XXX";
end case;
end if;
end if;
end process P1;

end structure;