Feb.

14th, 2017 2612 Digital Design Exam 1

Name_____________________Answers____________________
1. [10 points] Perform the following conversions/operations (use Verilog notation):

a) 14'b10111010100111 to hexadecimal:__________14'h2ea7____________

b) 5'b10100 to unsigned decimal:________________5d20_____________

c) 12'habc to binary:_________12b101010111100___________________

d) 7'h25 to unsigned decimal:__________7d37______________________

e) 6'd66 to binary:_____________6b000010______________________

2. A description of the QR code is provided in the supplement.

a) [6 points] How many bits are required to store one alphanumeric character of QR's
alphanumeric character code?

There are 45 alphanumeric character codes for the QR code. This will require 6-
bits to store these codes (2^6 = 64 and 2^5 = 32)

b) [6 points] Explain the advantage of using the formula: V = 45 C1 + C2 when coding two
characters.

By multiplying the 1st character by 45, it leaves the remainder when dividing that
result by 45 equal to zero. Thus, since there are 45 codes, we can add the code
information for the second character to that product without aliasing the first
character. So this method preserves the information of C1 and C2 without
aliasing.
The advantage is that the maximum value of V will be 45 * 44 + 44 = 2024. To
represent this range we only need 11 bits (2^11 = 2048). So we save one bit by
packing two characters this way versus 2 * 6-bits for single characters.
Name_______________________________________________________

3. A cell phone/tablet app is to be designed to play HD videos but only when the long axis of the
screen is horizontal and the eye detection sensor is true. Assume that the orientation signal
(orn[1:0]) is 2-bits: 00=phone logo on top; 01=logo left; 10= logo bottom; 11=logo right. The eye
detection sensing signal (eds) is logic 1 if the viewer's eyes are detected, otherwise it is logic 0. The
output signal, play, is logic 1 if the specification above is met and the video should play.

a) [6 points] Complete a truth table that embodies this specification/behavior.

orn[1] orn[0] eds play

0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
b) [6 points] Using a Verilog continuous assign statement, design this logic using the Sum of
Products method. (Only need the assign statement, not module, etc.)

assign play = (~orn[1] & orn[0] & eds) |

(orn[1] & orn[0] & eds);

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Name_______________________________________________________

4. [12 points] Are these two circuits equivalent? Show proof of your answer.

Try by matching truth tables.

a b c d e f
0 0 0 0 0 0
0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 1 1 0
Yes, they are equivalent.

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Name_______________________________________________________

5. [15 points] You are part of a design team that is developing a new, specialized QR scanner. For this
scanner the QR codes have the price encoded using the alphanumeric character coding table as
shown in the Supplement. Since it is encoding only the price, only 12 characters from this set will be
used: 0-9, decimal point and dollar sign.
Your part of the design involves developing a module to decode these 12 characters in QT code into
their equivalent ASCII characters (the ASCII code table is also in the Supplement). If any codes other
than these 12 characters are input, then the output should be an ASCII E, for Error. Complete the
Verilog design below. (Also, complete the size indices for the i/o variable declaration of the module.)

module qr_to_ascii (output reg [6:0] ascii,

input [5:0] qr_code);

// there are many solutions to this problem here is one

always @* begin
case (qr_code)
// 0 through 9 can be in a single statement
0, 1, 2, 3, 4, 5, 6, 7, 8, 9: begin
ascii = {3'h3, qr_code[3:0]};
end
37: ascii = 7'h24; // dollar sign
42: ascii = 7'h2e; // decimal point
default: ascii = 7'h45; // anything else, E for error
endcase
end // end always

endmodule

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Name_______________________________________________________

6. [15 points] Using the module outline below, design an ASCII to binary decoder only for the digits 0 to
9. The input is a 7 bit ASCII code (ascii) and the output is the 4-bit binary number (num). If the input
is not a ASCII code from 0 to 9, then the output should be hexadecimal: F.

module ascii_2_num (output reg [3:0] num, input [6:0] ascii);

// there are many solutions to this problem here is one

always @* begin
num = 4'hf; // default if nothing matches
if (ascii[6:4] == 3'd3) begin // upper nibble = 3
if (ascii[3] == 1'b0) num = ascii[3:0]; // for 0-7
else begin
if (ascii[2:0] == 3'b0) num = 4'd8 // for 8
if (ascii[2:0] == 3'b1) num = 4'd9 // for 9
end // end else
end // end upper nibble if
end // end always

endmodule

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7. [12 points] In Lab 3 you designed a seven segment decoder. Its module declaration is in the
supplement. Design the module ascii_display below that is based on the block diagram for
ascii_display given in the supplement. The display for this design will be on continuously.

module ascii_display (output [6:0] seg_out, input [6:0] ascii);

wire [3:0] i_num;

ascii_2_num u1 (.num(i_num), .ascii(ascii));

svn_seg_decoder u2 (.seg_out(seg_out), .bcd_in(i_num),

.display_on(1'b1));

endmodule

8. [12 points] Design a module whose input is a 4-bit binary code (num) that represents 0-15 decimal,
and the output is a signal (multip_4) that is logic 1 if the input is divisible by 4 with no remainder.
Otherwise it is logic 0. (Draw a truth table if it helps.)

module is_multip_4 (output multip_4, input [3:0] num);

// there are many solutions to this problem a simple one:

// if the two input ls bits are zero, it is a multiple of 4
assign multip_4 = ~num[1] & ~num[0];

endmodule

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