DIAMuunpubis

MV B- BUILD FINAL
2008/08/21

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 1 of 67
EE2 Thursday, August 21, 2003 11:19:38 am A02 PC8803

 TABLE OF CONTENTS

PAGE PAGE PAGE

5- DC& BATTERY CHANGER 27- DDR-SDRAM-3 48- HDD CONN
6- SELECT & BATTERY CONN 28- DDR-SDRAM-4 49- MULTIBAY CONN
7- SYSTEM POWER(3V/5V/12V) 29- ATI-M10-P-1 50- USB&IR CONN
8- DAUGHTER SYSTEM POWER(1.5V/1.8V) 30- ATI-M10-P-2 51- CARDBUS CONTROLL
9- SYSTEM POWER(VCCP/1.2V) 31- ATI-M10-P-3 52- PC CARD SLOT
10- DAUGHTER SYSTEM POWER(2.5V/VGAVCC) 32- ATI-M10-P-4 53- SD CARD CONN
11- CPU POWER(VCC_CORE) 33- VIDEO RAM DEPEND 54- MINIPCI CONN
12- DDR_TERMINATION 34- VIDEO RAM-2 55- LAN INTERFACE-1
13- POWER(SLEEP) 35- CRT& SVEDIO CONN
14- POWER(SEQUENCE) 56- LAN INTERFACE-2
36- LCD CONN 57- DOCKING CONN
15- CLOCK_GENEATOR 37- ICH4-1
16- BANIAS-1 58- BLUETOOTH
17- BANIAS-2 38- ICH4-2 59- BOARD TO BOARD CONN & LID SWITCH
18- BANIAS-3 39- ICH4-3 60- DAUGHTER FHW
40- KBC 61- DAUGTHER MDC CONN
19- BANIAS-4
41- INT.KBC/POINT DEVICES 62- DAUGTHER TCPA CONN
20- THERMAL&FAN CONTROLLER 63- DAUGTHER CONN & SWITCH LED
42- SUPER I/O 64- DAUGTHER LED & VOL BUTTON
21- ODEM-1 43- SERIAL PORT
22- ODEM-2 44- PARALLER PORT
23- ODEM-3 45- AC97 CODEC
24- ODEM-4 46- EQ&MIC JACK
25- DDR-SDRAM-1 47- AUDIO AMP&HP JACK
26- DDR-SDRAM-2

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 2 of 67
EE2 Thursday, July 31, 2003 10:53:56 am A02 PC8803

 PORT REPLICATOR
BANIAS CK 408
ITP (Micro-FCPGA) Clock generator
S-video
ATI_M9-X 1.5V,AGP 4X/8X_BUS,66MHz
LCM
VGA Chip
PSB, VCCP,400MHz
CRT

DDR _SODIMM0

DDR _SODIMM1
32MB/64MB Odem MCH-M 2.5V,DDR SDRAM200/266 Interface

DDR RAM 593 BGA

Primary_IDE
HDD ATA 66/100

Secondary_IDE 1.8V, Hub Link, 66MHz

Multi-bay/ Battery

Bluetooth
CONN A

CONN B

ICH4-M 3.3V, PCI_Interface,33MHz

Dock
Dock

USB3

USB5
USB0

USB1

USB2

USB4
421 BGA
Giga-bit LAN Mini_PCI O2_711M3B
BCM 5705 Wireless LAN CARD BUS

RJ45 ANT ANT

SD Card Cardbus
3.3V, AC97 LINK 3.3MHz 3.3V, LPC_Interface,33MHz SLOT SLOT A/B

BATTERY

MDC/Modem AD_1981 System BIOS TCPA Super I/O Kahuna Lite

Module 56K AC97 Codec FWH Module 47N227
System Charger & 47N250
DC/DC System power

Engineer

RJ11
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 3 of 67
EE2 Thursday, July 31, 2003 10:54:58 am A02 PC8803

 +V5 +V12
+VBATR
+V5A
0.0295 5V
ADPT 3V
+V3A
+V5S
+V5L +V5L
SKIP# NS_LM2621MMX
+V3L +V3L
+VBDC +V3

+V1.25
+V3S
ICTL ACOK

+VBATA
ON1 +VGAVCC
+VGAVCC +V2.5
SKIP#
2.5V
+V2.5L
ON2

PDS CHGA
+V2.5S
DISA
THMA
COMA ON1 1.05V +VCCP
+VBATB +V1.2L
CHGB
SKIP#
1.2V +V1.2L
THMB
DISB ON2

+V1.2_MCH
COMB
ON1 1.5V +V1.5A
BATSELB_A# BATSEL
+V1.5A
SKIP#
1.8V +V1.8S
ACPRES# ON2
BATSTAT# BATSTAT
+V1.5S

+VCC_CORE

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 4 of 67
EE2 Thursday, July 31, 2003 10:56:04 am A02 PC8803

 +V5S

D1000 BAT54S
R1016 CHANGE TO 133K_1%
2 1
U1002 4 1 1 R1015 2
1
LM324A 3 R1000 R1016 3
+ 10K_1% U1002 133K_1% 100K_5%
1
$V

OUT 1 U1002 4 U1002 1

- 2 4 5 + 4
R1022 2
10 + LM324A LM324A 2 1 C1015
R6043 2 OUT 7 12 +
1 11 0_5% 8 6 - 14 3 D6009 1 C1003
$V

1
R1001 OUT 1 OUT 2 1UF_25V
R1021 1 2 9 - 0 13 - BAT54C 2 1UF_16V
2 1 11 R1020 LM324A
0_5% 100K_0.5% 1 R6036 2 11 R1037 4.7K 11
2
10K_5% 1
R1019 2
2 1
499_1% C1000 2200PF 2
R1011
U1000 2 Q1002 2 100K_5% 10
1 2 Q1003 2
1
1B E 1 1 C1016 1 R6044 2
$V

2
R1006 1B E C R1017 2 6800PF_25V
1 C312 10K_0.5% 80.6K_1% OPEN
CATHODE 3
MMBT3906 3
C 7- MAX_LX5
4 REF
2
NC 2 2 MMBT3906 3 2
0.1UF_25V
5 ANODE NC 1 Q1004 5
1 S1
G1
NS_LMV431ACM5X_SOT23_5P 6 R1588
D1
1 D2 4 1 2 37-,16- H_STPCLK#
3 G2 OPEN
R1038
47K_5% S2 2
1 NDC7002N R6029
2
R1040 1 2 37-
10K_5% STBY_SWIN#_3
0_5%
2
+ VADP1 +VBATR

DC JACK
+ VADP
1 R1039 2 L26 SINGA_2DC_S028I200
NFM60R30T222 JACK3
237K_1% 3.3A_150mil 1 2 +VADPTR 3.3A_150mil 1
+ VADP 3
+ VADP1 Iadp=3.3A +VADP2 +VBATR 4 3 2
1N4148 1 C301 1 C300 1 C302 1 C299
R1035

4
5
15mil 0.018_1%_1W 3.3A_150mil
3.3A_150mil R1036 2 10PF 2 0.1UF_25V 2 10PF 2 0.1UF_25V
1 2 1 2

1
D1004 1 C1034 0.015_1W_1%
1 R1591 2 2
2 1UF_25V

1
1772LDO OPEN
R1048 R1049 +V3A
4.7 1 R1590 2 4.7
OPEN

2
1 R1041 2 5.4V_15mil 1
1772REF
33 1

0.47UF_25V 2
C1033 1

0.47UF_25V 2
C1041 1
1 C1044 R1054
1 100K_5%
R1592 1 2 1UF_10V 1
2
+V3A OPEN R1050 1772REF 1 C1040 R1047 57-,55-
52.3K_1% 10K_5% AIRACIN
2 2 0.1UF_16V 1772LDO Q1005 3
2 2 R1055 D

D1006 AIRACIN# 40-,6-1 2 2G

5-
1 C1037 1 C1038
1772GND 10K_5% 2N7002

5
6
7
8
S

2
4.096V_10mil 15mil
1 1 2 10UF_25V 2 10UF_25V 1

D
R1071 1 C6038 R1052

G
100K_5%
2 1UF_6.3V
52.3K_1% 1 C1045 U1008 1N4148
Q1007

2 1
1 28

S
2 2 2 1UF_6.3V DCIN IINP IRF7807V
2 LD0 CSSP 27 10mil C1039 +VBDC

4
3
2
1
3 CLS CSSN 26 10mil
R1046 2 0.1UF_25V
40- 4 REF BST 25 15mil 1
ACIN# 24
5 CCS DHI 15mil 2.2_5% L27
6 23 15mil 1 2 1 R265 2 2.5A_100mil
CCI LX
7 CCV DL0V 22 15mil PLFC1055P_220A_22UH
C1053 0.1UF_16V R1051 21 0.05_1W_1%
8 GND DL0 15mil
567 8
1 2 1 2 10mil 9 PGND 20 15mil C297
1K_5% GND 19 1 C1049 D 1 1 1 1 C288
10 ICHG CSIP 10mil
1 C1043 1 C1042 11 ACIN CSIN 18 10mil G U1007 R1065 R1064
1 2 1UF_10V FDS6680S 2 2 22UF_23V_METAL 2 10UF_25V
2 2 12 AC0K BATT 17 10mil
1 R1053 13 16 S
10K_5% REFIN CELLS 2 C1050 2
+ VADP 0.01UF_16V 2 C1046 14 ICTL VCTL 15 1772LDO 43 2 1 C1051
R1060 2 0.01UF_16V 2
1 MAX_MAX1772EEI_QSOP_28P 1 2 1 2
0_5% 0.1UF_16V R1063 2 0.1UF_25V 0.1UF_25V
5- 1
1772GND
1 R1068 2 47K_5%
+V3A
10.2K_1% 1
1 +V3A ICHG R1062
R1070 1 R1059 2 47K_5%
1.37K_1%
100K_1% 1 2
2
R1061
R16 37.4K_1%
R1067 2 WAIT TO CHANGE 38.3K Q1008 Engineer

Note:
CHGCTRL_3 40- 1

40.2K_1%
1
2 3 SST3904
C
B 2 6- CELLSEL
David Du
Drawn by
David Du
INVENTEC
high power trace R1066 1 C1052
E
1 C6023
Icharger=2.5A R&D CHK
TITLE
Size
1 A3
5- CELLSEL=1,Vcharger=12.6V
49.9K_1%
2
2
0.1UF_16V
1772GND 2 OPEN
CELLSEL=0,Vcharger=16.8V
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
DC &BATTERY CHANGER
1772GND 5- Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 5 of 67
EE2 Thursday, August 21, 2003 11:22:36 am A02 PC8803

 +V3A +V3A

+V3A
1
1 +VBATA
R283 +V3A
1 1 13.0K_1%
R1218 +VBATB
R1581 R1215 1
100K_5% 2
3.3K_1% 2.7K_1% 6- R1233
2 BAT6CELL# 100K_5%
2 2 5A_200mil
2
1 1
R1231 R1230 5A_200mil
40- 1 R1216 2 1 C203 1.8K_5% 1.8K_5%
SCL_MAIN
0_5% CN14 2 0.1UF_25V 2 2
1 1
2 2 57-,40- 1 R1232 2
R1219 3 3 SCL_MBAY
SDA_MAIN 40- 1 2
100_5% CN1003
4 4 1 1 1 C1289
0_5% 5 5 2 2 2 0.1UF_25V
6 6 57-,40- 1 R1229 2 3 3
SDA_MBAY
40-,6- 1 R1217 2 4 4
THM_MAIN# 100_5% 5
100_5% AMP_1470444_1_6P 5
1 C1245 6 6
1 D1064 1 D1015 1 R1234 2
2 THM_MBAY#40-,6-
100_5% AMP_C1470694_1_6P
2 UDZS5.6B 2 UDZS5.6B 47PF_50V 1 C1282
1 D1016 1 D1017
2
47PF_50V
2 UDZS5.6B 2 UDZS5.6B

MAIN BATT
2nd BATT

2.5A_100mil 2.5A_100mil

+VBATB +VADP2
+VADP2 +VBATA +VBDC +VBDC
Q1032 Q1025
FDS4435 FDS4435 Q1028 Q1029
5A_200mil 5A_200mil 5A_200mil 5A_200mil
D

D
S

S
5 6 7 8

5 6 7 8

5 6 7 8

5 6 7 8
4 3 2 1

4 3 2 1

4 3 2 1

4 3 2 1
2.5A_100mil 2.5A_100mil
G

G
1 C204 1 C1288
1 FDS4435 FDS4435
2 2.2UF_25V 1
2 2.2UF_25V

5
D2 6
3
1
7
D1 8
R1246

2 G1 S1

S2
10K R1245 +VBDC
10K

4 G2
2
2

1 C1291 Q1031
10mil FDS4935 10mil
2 0.022UF 1 C1287
2 0.022UF
+VADP +VADP1 +V3A

D1002 Q1030 2
3.3A_150mil 3.3A_150mil U12 1 R1244 2 1 B E
1
2 1 10mil 1 BATA BATB 20 10mil
100K_5% C

40-,6- 2 19 40-,6- THM_MBAY# R1251

SFPB74 THM_MAIN#
3
THMA THMB
18 MMBT3906 3 470K_5%
Q1001 CHGA CHGB
10mil 4 DISA DISB 17 10mil
2
FDS6675 10mil 5 16 10mil
1
5-
R1026 2 COMA COMB 3.3V_10mil R1589 CELLSEL
6 15
D

1
S

6- 1773VDD
100K_1% GND VDD
5 6 7 8

1 R205 390K_5%
4 3 2 1

10K 1773VDD 6- 2 7 MINV TCOMP 14 10mil

15mil 8 13 40- 3
EXTLD BATSEL BATSELB_A# 2 C
15mil 9 12 40-,5- 2 Q1062
G

B
PDS ACPRES# AIRACIN#
D1003
15mil 10 ACDET BATSTAT 11 40- BATSTAT# 1 C1290 1
E SST3904
R1252 2 1
R1250
2

15mil 1 MAX_MAX1773EUP_TSSOP_20P +V3A 0.33UF_10V 47K_5%

3.3K_5% 2
1N4148 R203 R1249 2
10mil 1 2 1 2

100K_1% 10K_1%
BAT6CELL# 6-
1 R1248 2
1
+V3A
R204
100K_1% 100K_5%
D1014 1R1247 2
2
2

100K_5%
1 R202 2 1R1214 2
1N4148
0_5% 100K_5% Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
SELECT & BATTERY CONN
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 6 of 67
EE2 Thursday, July 31, 2003 10:58:32 am A02 PC8803

 +VBATR +VBATP

PAD4
5A_200mil 3 5A_200mil 20mil 1 R231 2 20mil
4
4.7_1206_1/4W
POWERPAD_4A MAX3V +V3A
For power test C197
1
1 C225 +V5L
100UF_25V 1 C226
2

4.7UF_K_25V
2
2 +VBATP

0.1UF_25V
D1011 PAD2
R232 3
220K_5% 2 4A_160mil
L21 4A_160mil 3
+V5L MAX5V 1
15mil 15mil
S2
1 2 1
1 2 3 PLFC1055P_6R8A_6.8UH 4
4 G2 2A_80mil
POWERPAD_4A

1
D2
BAT54A 6

OPEN
R218
1 C202
R1208 1 5 1 1 C185
0.1UF_25V
R1212 1 C201 D1 8
47K_5% 7 2 10UF_K_6.3V

2
10K_5% R1195 C1221 1 C1222 1 C1223

330UF_4V_OSCON
2 OPEN 15mil 1 2 G1
2 2 S1
1 2
Q1022 1

10UF_25V
2 0 2 2 1UF_25V

1
R217
0
2
1 C1244
FDS6982S
2 0.022UF U1012
1 NC BST3 28
2 PGOOD 27 15mil
LX3
3 ON3 DH3 26 15mil
4 ON5 LDO3 25
5 ILIM3 24 15mil 4A_160mil +VBATP
6 DL3
SHDN# GND 23 15mil 5 6 7 8 Q1021 7-
7- 7 22 15mil 1632GND M1999FB3
M1999FB3 FB3 OUT3 1 C1217 1 C1218 MAX5V +V5A
10mil 8 21 15mil D FDS6612A
REF OUT5
M1999FB5 7-
R1211 9 FB5 V+ 20 G
2 2 10UF_25V
2 1 10 PRO# DL5 19 15mil
11 ILIM5 18 S
1 0_5% LDO5
12 SKIP# VCC 17 10UF_25V
R1210 13 16 15mil 4 3 2 1 L19 2 PAD1
80.6K_1% TON DH5 6A_250mil 3 6A_250mil
14 BST5 15 15mil 1 2 1
1 1632GND LX5 4
R1242 2
Q1024 SIQ127A_10UH
MAX_MAX1999EEI_QSOP28_28P 56 7 8 POWERPAD_4A

1
143K_1%
D FDS6680S R214 C182
2 R1207 2 C1242 0.1UF_25V 1 1 C198
15mil 1 +V3L G 5-
+V5L MAX_LX5 16K_1%
0 1 2 2 10UF_K_6.3V

2
470PF_50V S
R1209 R213 +V5L
1 10mil 1 R1194 2 15mil 15mil
2 1 43 2 1 220UF_6.3V_OSCON
2 1 324K_1% 0_5% 22 1 C1220
1 C1219 1 C200

2
1
R1243 1 2 2 C199 2 D1018

2 1
C1243 2 2
C1286 4.7UF_K_6.3V
4.7UF_K_6.3V BAT54C

3
274K_1% 2 1UF_6.3V
0.1UF_10V

1
10mil

1
1 R1241 2
+V3A
0 R216
0.22UF_K_10V
10.2K_1%

2
7-
1632GND M1999FB5
1632GND
1 1N4148
2
1632GND
D1012
+V5 D1005 +V12
R1213 EC10QS03L
1
OPEN 2
SLP_S3#_3R 30mil L1000 120mA_30mil 120mA_30mil
59-,47-,45-,40-,38-,13-,12-,9- 1 2 2 1
SIL520_6.8UH

1 C1047 +V5

2 22UF_10V U1006
20mil 1 PGND 8 20mil
SW
2 EN 7 10mil
BOOT
1R1045 2 3 6 10mil 1 R1044 2 1 C1032
FREQ VDD 1 C1036
150K_1% 5 0
4 FB SGND 47UF_20V 2 10UF_K_16V

1 2
NS_LM2621MMX_MSO8_8P

1
1
C1048 R1043
2
0.1UF_16V C1035 147K_1%
2.2PF_50V

2
1
R1042 Engineer
16.9K_1% David Du
Drawn by
David Du
INVENTEC

2
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
SYSTEM POWER(3V/5V/12V)
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 7 of 67
EE2 Thursday, July 31, 2003 10:59:19 am A02 PC8803

 +V5A_BN

15mil +V1.5A_BN

3 D4004 BAT54A L4000 3A_100mil

1 2
15mil 15mil PLFC0735P_6R8A
2 1

C4004
1 1 C4003
1
1 C4005 2 0.1UF_16V
+VBATP_BN R4001
10K_1% 2 220P_25V
Q4004 2
+VBATP_BN
S2 3 1 220UF_2.5V_S18_METAL
12mil 40mil
4 G2 R4002
10 D2 6 20K_1%
15mil R4022
2 1 5 1 1 2
12mil D1 8
1 C4002 7 2 C4000 2
G1 C4001
2 S1
2 0.1UF_25V 1
12mil 10UF_25V 0.1UF_25V
1 C4020
15A18SGND
2 1UF_10V
1
R4005 U4000 FDS6984S

15
20

22 4
VDD

V+
NC2
2
10mil 21 VCC 25
BST1 26
1 DH1 27
23 NC0 LX1 15mil
24
2 C4006 DL1
28 NC1 FB1 2
1UF_10V
5 TON PGOOD 7
6 SKIP# OUT1 1 12mil +V1.8S_BN
15A18SGND
OUT2 14 12mil 10
10 ON1
18 15mil 2 R4025 1
R4003 2 BST2 L4001 3A_100mil
63-,10- 1 11 ON2 DH2 17 1 2
SLP_S3#_3R_BN
LX2 16 15mil PLFC0735P_6R8A
0_5% 3 ILIM1 19
DL2 1 C4021 Q4000
FB2 13 +VBATP_BN
8 AGND

22 PGND

12 ILIM2
2 0.1UF_25V 12mil
9 REF

S2 3
40mil C4010
4 G2
D2 6 1 1 C4009
MAX_MAX1715_QSOP_28P
5 1 C4011 1 2 0.1UF_16V
12mil D1 8
7 2 2 C4012 1
G1
2 S1 R4004
1 10UF_25V 20K_1% 1 C4008
0.1UF_25V 220UF_2.5V_S18_METAL
2 2 180PF_50V
15mil

FDS6984S
10mil
R4000

1 C4007
1
274K_1%

1 2
R4007
274K_1%
2

2 1UF_6.3V 1
R4006
10mil 1 R4008 2 23.7K_1%
0 2

15A18SGND

15A18SGND

SYSTEM POWER (1.5&1.8) ON BUTTON DAUGHTER BOARD Engineer

David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
SYSTEM POWER(1.5V/1.8V)
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 8 of 67
EE2 Thursday, July 31, 2003 10:59:26 am A02 PC8803

 +VGAVCC
+V5A

+VBATR

15mil 40mil L20 4A_160mil PAD5 5A_200mil

1 2
SIL104R_5R2 POWERPAD_2_0610
3 D4 BAT54A 1 1
5 6 7 8 2 C205 2
2 1 C186 1
Q7 D
FDS6612A G 10UF_25V 0.1UF_25V R219 1 C207 1 C242
+VBATR 1K_1% 2 220P_25V C230 2 0.1UF_16V
S 1
2

4 3 2 1 220UF_2.5V +V3A

1
10 R1582
15mil R235 15mil 1 OPEN 1
2 1 56 7 8
R220 R6019
D 2 OPEN
20K_1%
1 C206 G
1 C231 12mil
Q15 2
D D Q1057 2
2 0.1UF_25V FDS6680S R1583 2
S G G 1
2 1UF_10V
43 2 1 S OPEN
S SSM3K17FU Q1058 D
1 OPEN 1 C1469 29-G G
D

R1175 U13 PWRPLAY

2 OPEN

15
20
S
22

4
SSM3K17FU S

VDD

V+

NC2
2 OPEN
VGA25LGND
10mil 21 VCC 25
BST1
26 15mil
1 DH1 27
23 NC0
C189

LX1 15mil
1UF_10V

2 24 15mil
DL1
28 NC1 FB1 2 10mil

5 TON PGOOD 7 +V2.5L

VGA25LGND

SLP_S3#_3R 59-,47-,45-,40-,38-,13-,12-,7- 6 SKIP# OUT1 1 12mil

OUT2 14 12mil 10
10 ON1
1 R223 2 18 15mil 2 R236 1 15mil
BST2 L22 4A_160mil PAD3 4A_160mil
11 ON2 DH2 17 15mil 1 2
200K_5% 16
LX2 15mil SIL104R_7R0
3 ILIM1 19 15mil POWERPAD_2_0610
DL2 1 C232
+V3A FB2 13 10mil Q12 +VBATR
8 AGND

12 ILIM2 22 PGND
2 0.1UF_25V
9 REF

S2
3
4 G2 60mil
5 U4005 D2 6
MAX_MAX1715_QSOP_28P
2 4 5 1 C211 1
D1 8 C213
3 TI_SN74LVC1G17DBVR_SOT_5P 7 2 2 C212 2
1 C6016 G1 1 1 C209
2

15K_1%
S1

R226
2 0.012UF_16V 1 10UF_25V 1 C210 2 1UF_10V
0.1UF_25V
FDS6982S 2 OPEN
15mil
1
220UF_4V_METAL
10mil

LAN_ON_3 59-,55-

1 C208
1

1 2
R221
R224 1UF_6.3V
300K_1%
300K_1%
2

2 1

+V1.2_MCH +V1.2L R225

10mil 1 R207 2 9.76K_1%
0 2

VGA25LGND
Q1020
1 S D 8 VGA25LGND
2 7
3 6
1 4 5
G VGAVCC NOTES : USED M10 (1.0V/ 1.2V) USED M9(1.25V/ 1.5V)
R1166 R219_ 1K_1% R219_ 10.2K_1%
470_5% NDS8425
C1189 R220_20K_1% R220_40.2K_1%
2
1 1 R1582_5.49K_1% R1582_40.2K_1%
Q1019 3 R238
D
14- 2G 220K_5%
PWR_GOOD#_5 68UF_6.3V_METAL
S 2
NDS7002A 1

Engineer
David Du
Drawn by
David Du
INVENTEC
PWR_GOOD_5 14- R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
SYSTEM POWER (2.5V/1.25V)
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 9 of 67
EE2 Thursday, August 21, 2003 11:26:35 am A02 PC8803

 +V5A_BN

+VCCP_BN
15mil

3 D4005 BAT54A
L4004
15mil 15mil
PLFC0735P_6R8A 3A_100mil
2 1
1 2
C4044
1 1 C4043
+VBATP_BN 1 2 0.1UF_16V
+VBATP_BN R4032 1 C4026 220UF_2.5V_S18_METAL
S2 1.1K_1% 2 220P_25V
3 2
4 G2 40mil
D2 6
5 1 1
D1 8
R4041 7 2 C4041 2
15mil G1 C4040
2 S1
1 C4033
2 10 1 1
Q4007 10UF_25V 0.1UF_25V
1 C4035 FDS6984S
2 1UF_10V
12mil 2 0.1UF_25V
1
R4034
1
20K_1%
R4042 U4003 2
15
20

22
4
VDD

V+
NC2

2
63- MCH_GOOD_BN
10mil 21 VCC 25
BST1 26
DH1 15mil
1 23 NC0 27 15mil
LX1 24
2 C4027 DL1 15mil
28 NC1 FB1 2 10mil VCCP12LGND
1UF_10V
5 TON PGOOD 7 1 R4050 2 63-,10-PWR_GOOD_3_BN
VCCP12LGND
100K_5%
SLP_S3#_3R_BN 63-,8- 6 SKIP# OUT1 1 15mil +V1.2L_BN
R4029 2 0_5% OUT2 14 15mil
63-,10- 1 10 ON1
PWR_GOOD_3_BN 18 15mil 2 R4040 1
BST2 L4003 3A_100mil
63- 11 ON2 DH2 17 15mil 10 1 2
LAN_ON_3_BN 16
LX2 15mil PLFC0735P_6R8A
3 ILIM1 DL2 19 15mil
13 10mil 1 C4032
FB2 +VBATP_BN
8 AGND

22 PGND

12 ILIM2
2 0.1UF_25V
9 REF

S2
3
4 G2 40mil C4039
D2
6 1 1 C4038
MAX_MAX1715_QSOP_28P
5 1 1 2 0.1UF_16V
D1 8
7 2 2 2
G1
2 S1
1 C4036 C4037
10UF_25V 0.1UF_25V 3.92K_1% 1 C4024
Q4006 220UF_2.5V_S18_METAL
R4027 2 100PF_50V
15mil FDS6984S 1

10mil

1 1
1 2 C4025
R4031 1UF_6.3V
274K_1% R4028
2
274K_1%
2 1
R4026
10mil 1 R4030 2 18.7K_1%
0 2

VCCP12LGND

VCCP12LGND

Engineer
David Du
INVENTEC
SYSTEM POWER (VCCP&1.2) ON BUTTON DAUGHTER BOARD Drawn by
David Du
R&D CHK
TITLE
Size
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
SYSTEM POWER(VCCP/1.2V)
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 10 of 67
EE2 Thursday, July 31, 2003 6:06:02 pm A02 PC8803

 +V3S
+VBATR LAYOUT NOTES: C1779 C502 C503 PIN2 CONNECT TO Q14 , Q18 GND
C54

2
1
C1780 C532 C531 PIN2 CONNECT TO Q16 , Q20 GND
5A_200mil 10UF_25V x3
D1025 1N4148
1 2 0.1UF_16V

FDS6694
6
5 5

7
D 8
Q1010FDS6694
U1035 U1035

6
R1404 2 1 C1066 1 C1160 1 C1065

7
8
1 6 1 3 4 38-

G
D
200K_5% SB_VGATE 2 2 2

Q1011
G
2 2 +V5S

1 S
1 C1402

S
KENVEN SENSE +VCC_CORE

4
3
2
+V3S
2

4
3
2
1
0.1UF_16V DHM
R272
3K_5%1 LXM L24 R257 25A
2 1 1 2

HMU1050_0.6UH_17A 0.0015_5%_1W
FAIR_NC7WZ17_SC70_6P C281 C1107
2
1 1
FAIR_NC7WZ17_SC70_6P
15-

Q1012 FDS7764A
1

FDS7764A
PM_VGATE

6
5

7
8

7
D 8
R1117
20mil 20_5%

D
1 D1008

G
2

Q1013
R273
1 1 C291 2 SSM34_3A40V 220UF_2.5V

1 S
OPEN1 R267 1 C1069 10mil 220UF_2.5V
2 1UF_6.3V

4
3
2
1

4
3
2
10 1 C1064 1 1
2 2.2UF_K_10V R1095 R1097
2 2 1K_1%
750_1%
DLM
2 2 2

C1056 470PF_50V
20mil 1 2
1 C303
2 1UF_6.3V 1 KENVEN SENSE
1000PF_50V_X7R
3 D1007
BAT54A
15mil
2 1 1
VCC_IN 20mil
10UF_25V x3 R1094 R1098
TH 49 750_1% 1K_1%
U1009 MAX1987GND
2 2
15mil 12 VDD 36

FDS6694

FDS6694
VCC

6
R264

7
8

7
D 8
59- 1 2 22 SYSPOK
MCH_GOOD 24 C1070 1 C1068 1 C1162 1 C1161

D
0_5% CLKEN# 42 0.1UF_25V

G
23 V+ 15mil
2 2 2

Q1017
1 C292 IMVPOK
20mil 1 R1092 2

Q1016
BSTM 32
11- 30 34 1 2

1 S
2 OPEN VR_VID0 D0 DHM 25mil 4.7_5%
11- 29 D1 LXM 33 25mil
VR_VID1

4
3
2
1

4
3
2
11- 28 D2 DLM 35 25mil
VR_VID2 27 37
VR_VID3 11- D3 PGND 25mil
11- 26 D4 GND 13 15mil
VR_VID4 25
VR_VID5 11- D5
UGATE2
6 S0 CMP 45 10mil
S0 L23
7 S1 CMN 46 MAX1987GND 10mil 2 1 1 R250 2
S1 20
S2 8 S2 OAIN+ 10mil HMU1050_0.6UH_17A
0.0015_5%_1W
OAIN- 19 10mil
3 B0 C262
B0 1 1 1
B1 4 B1 R1079 R1096
5 B2 FB 18 10mil 1.1K_1% 4.7K_5% R1159 C263
B2

FDS7764A
20_5% 1 1
NEG 16

FDS7764A
1 D1009

6
5

7
8

7
8
38- 0_5%1 2 R1076 43 SUS
+VCCP PM_DPRSLPVR 2 2 2
0_5%1 R1075 44 CCI 17

D
38-,15- 2 10mil
CPUSTOP#_3 DPSLP# 1 C1058
0_5%1 R274 21 POS 15

G
17- 2 10mil 2 SSM34_3A40V
PSI#

Q1015
PSI# 59-,40-,30-,14- 0_5%1 2 R268 9
1
4700PF_50V2

Q1014
PWR_GOOD_3 SHDN# C1055 2 R1081
OPEN1 2 R1074 2 CSP 48

S
TON 1M_5%
CSN 47 470PF_50V 1

4
3
2
1

4
3
2
1
C1057 270PF_50V 14 CCV C1067
1 1 C1123 220UF_2.5V
2
1 2 0.1UF_25V R271 2 1000PF_50V_X7R 220UF_2.5V
R1073 2
REF
10mil 10 REF BSTS 41 20mil 1 1.1K_1%
4.7_5% 1 2 2
11 ILIM DHS 39 25mil

1 1 R1077 2
1 1 TIME LXS 40 25mil
MAX1987GND R1078
2 100K_5% 28K_5%
0.22UF_K_10V 31 DDO# DLS 38 25mil
C1054 2
MAX_MAX1987ETM_QFN48_48P
MAX1987GND
10mil
MAX1987GND
KENVEN SENSE
10mil
1 1
C1059
R1080
100PF_50V 2 30.1K_1%
MAX1987GND R269 POWER_GROUND
2
10mil 1 2

MAX1987GND
0_5%

MAX1987GND MAX1987GND
B0 B1 B2
S0 VCC_IN S2 1
H_VID0 18- 0_5% 1 2 R1104 11- VR_VID0 Engineer
1 1 1
H_VID1
H_VID2
H_VID3
18-
18-
18-
0_5%
0_5%
0_5%
0_5%
1
1
1
2
2
2
R1103
R1102
R1101
11-
11-
11-
VR_VID1
VR_VID2
VR_VID3
1
R1084
0_5%
1
R1082
1
R1083
OPEN
R270

2
100K_5% R1085
0_5%
R1086
0_5%
R1087
OPEN
David Du
Drawn by
David Du
INVENTEC
H_VID4 18- 1 2 R1100 11- VR_VID4 2 2 2 R&D CHK Size
18- 0_5% 1 2 R1099 11- 0_5% TITLE
H_VID5 VR_VID5 2 2 REF A3
S1
2 REF DOC CTRL CHK

MFG ENGR CHK

DIAMOND
MAX1987GND CPU POWER(VCC_CORE)
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 11 of 67
EE2 Thursday, July 31, 2003 10:53:10 am A02 PC8803

 +V3 D6 BAT54
3 1
+V1.25S
R1144 10

1
MAX1809_LXA
U1010
59-,47-,45-,40-,38-,13-,9-,7- 1 R1138 2 1 LX 16
SLP_S3#_3R SHDN#
2 IN PGND 15
1K_1% MA1809_V3 40mil L25 3A_120mil
3 LX LX 14 1 2
4 IN PGND 13 1UH
5 SS VCC 12 10mil
6 11 1 R263 2
EXTREF GND
7 REF 10 C290
C11191 TOFF 9 100 1
8 FB GND
1 C1099 1 C1100
0.01UF_16V 2 MAX_MAX1809EEE_QSOP_16P
330UF_2.5V_METAL
2 2 10UF_K_6.3V 1
10UF_K_6.3V R266 MA1809LX_FB
68K_5%1 C298 10mil
2 2 0.01UF_16V 1 C1121
C11221
1UF_6.3V2 2 1UF_10V
10mil 1 R1146 2 40mil
0_5%

26-,25-,21-
SM_VREF
+V2.5

+V5

U1011
1 5
1 OUT VCC
R255 1 C1120
10K_1% 2 VEE
2 0.1UF_10V 1 C261
2
3 IN+ 4 2 0.1UF_10V
IN-
1
MAX_MAX4322EUK_SOT23_5P
R256 1 C280
10K_1%
2 0.1UF_10V
2

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
VGA POWER(VDD_CORE)
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 12 of 67
EE2 Thursday, July 31, 2003 10:53:16 am A02 PC8803

 +V5A

+V2.5L +V2.5S +V1.5A +V1.5S

+V3A +V3S +V5A +V5S

14 U1038 Q1046 Q10

Q1041
1 2 8 1 8 1 8 1
5 S D 2 5 S D 2 5 S D 2 Q6
74ACT14MTC 3 3 3 8 D S 1
7 6 6 6 7 2
4 G 7 4 G 7 4 G 7 6 3
5 G
4
FDR840P FDR840P FDR840P 1 C188
NDS8425
C1368 1 C1377 68UF_4V_METAL
1 C1369 1 C175
1
2 OPEN 68UF_4V_METAL
1 47UF_6.3V_METAL R1204 1
220K 1 1 R1407
1 R1359 470_5%
1 2
R1373 R1382 470_5%
2 2
330K R1371 1 470_5%
470_5% 2 Q1054 3 1
2 47UF_6.3V_METAL D
R1383 2G R206 1 C187
2 220K Q1039 3 100K
+V5A Q1047 3 D S 2 0.039UF_10V
2G
Q1043 3 2
2G
D +V5A NDS7002A 1 2
D S
2G S
NDS7002A 1
S
NDS7002A 1
NDS7002A 1

14 U1038 14 U1038
SLP_S3#_3R 59-,47-,45-,40-,38-,12-,9-,7- 3 4 9 8 57- SLP_S3#_5R

7 7 74ACT14MTC
74ACT14MTC

49-,32- SLP_S3_5R

+V3
+V2.5L +V2.5 +V5A +V5
+V3A

Q11 Q1035
8 1 Q1042 4 S D 1
5 S D 2 4 S D 1 2
3 2 5
6 5 3 G
6
4 G 7 3 G
6
1 FDC638P
1 FDR840P
C274 1 FDC638P R1343
R78 1 1 1 1 C6024 220K C1351 1
220K 2 1 R1372 R1345 1 R1344
10UF_K_6.3V C1350 2 2
R1236 220K 470_5% 470_5%
2 470_5%
+V5A 2 2 Q1034 2 +V5A
2
47UF_6.3V_METAL Q1033 3
3 1000PF_0402
Q1023 3 D D
D 47UF_6.3V_METAL 2G 2G
2G S S

S 1 1
NDS7002A NDS7002A
1 C52 NDS7002A 1 1 C53
2 0.1UF_16V 2 0.1UF_16V

14 U1038 14 U1038
SLP_S5#_3R 38- 5 6 11 10 SLP_S5#_5R

7 74ACT14MTC 7 74ACT14MTC

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
POWER(SLEEP)
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 13 of 67
EE2 Thursday, August 21, 2003 11:28:38 am A02 PC8803

 +V3S

1 1 D1029
R1424
180_0.5% 2 1N4148
2

1 C1408 +V5S +V3S

2 1UF_10V +V5A

+V5A
1
R1412
1 4.7K_5%
R1425
2
10K_5%
2
+V1.5S +V2.5S +V1.8S
U103610
1 9
IN1 VCC OUT1 8
59-,40-,30-,11- PWR_GOOD_3
14 Q1052 3
2 IN2 U1038
OUT2 7 D
3 IN3 OUT3 6 13 12 2G
4
IN4 GND OUT4 S

7 74ACT14MTC NDS7002A 1
5
MAX_MAX6338KUB_UMAX_10P

9- PWR_GOOD#_5

9- PWR_GOOD_5

+V3A +V3A

1
R277 1 C306
511K_1%
2 0.1UF_16V
2

5 U1032 VCC1_POR#_3
2 4 40-,38-

3
TI_SN74LVC1G17DBVR_SOT_5P

1 C307 1
R278
2 0.1UF_16V 100K_5%
2

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
POWER(SEQUENCE)
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 14 of 67
EE2 Thursday, July 31, 2003 10:53:25 am A02 PC8803

 +V3S

+V3S
L1018
NFM40P12C223
(10/5) 2 1 (15/5)
(10/5) (10/5)
3 4 1 L1019 2
BLM11A221S
1 1 1 1 1 1
C1365
2 C118 C1363 2 C134 2 C133 2 C135 2 C132 1
0.01UF_16V22UF_6.3V 0.1UF_16V 0.1UF_16V 0.1UF_16V 0.1UF_16V C1366 1 1 C1367
0.01UF_16V 2 10UF_K_6.3V
2 22UF_6.3V

U1020
1 VDD VDDA 26
8 VDD
14 VDD VSSA 27 1 2
19 VDD R147 49.9_1%
R1332 2 33_5%
+V3S Place crystal within 500 32 VDD CPU2 45 CLK_CPU_BCLK_3 1 16- CLK_CPU_BCLK
mils of CLK_TITAN 37 VDD CLK_CPU_BCLK#_3 R1331 2 33_5%
C1339 10PF
46 VDD CPU2# 44 1 16- CLK_CPU_BCLK#
1 50 VDD
1 2
1 2
R149 49.9_1% R150 49.9_1%
X1001 2 XTAL_IN CLK_MCH_BCLK_3 R1330 2 33_5%
1 1 CPU1 49 1 1 2 22- CLK_MCH_BCLK
R1314 R1312 14.318MHZ R1333 2 33_5%
CPU1# 48 CLK_MCH_BCLK#_3
C1340 10PF
3 XTAL_OUT 1 22- CLK_MCH_BCLK#
OPEN 1K_5% 1 2
2 1 2
1 R1327 2 R1308 49.9_1% R148 49.9_1%
2 2
CLK_ITP_3 1
R1310 2 33_5% 1 2 1 2
1K_5% 40 SEL2 CPU0 52 19- CLK_ITP
R1309 0_5%
CPU0# 51 CLK_ITP#_3 1 R1326 2 33_5% 1 2
55 SEL1 R1325 49.9_1%
66INPUT 24 1 2 19- CLK_ITP#
R1369 R1324 0_5%
54 SEL0 66BUF2 23 CLK_AGPCONN_3 33_5% 29- CLK_AGPCONN
1 2
R1370 2 25 PWRDWN# CLK_MCH66_3 R1368 33_5%
SLP_S1#_3R 38- 1 66BUF1 22 21- CLK_MCH66
1 2
1 1 33_5% CLK_ICHHUB_3 R1367 2 33_5%
PCISTOP#_3 38- 34 PCI_STOP# 66BUF0 21 1 37- CLK_ICHHUB
R1311 R1313 R1340 2 33_5%
53 CPU_STOP# CLK_ICHPCI_3
1K_5% OPEN PCIF2 7 1 37- CLK_ICHPCI_3R
2 2
28 VTT_PWRGD# PCIF1 6
R1328 1 2
+V3S 10K_5% 1 R1329 2 43 MULT0 PCIF0 5
OPEN
29 SDATA CLK_CBPCI_3 33_5% R1337 2
ICH_SMDAT_3 37-,26-,25-,20- PCI6 18 1 51- CLK_CBPCI_3R
30 SCLOCK CLK_NICPCI_3 33_5% 1 R1338 2
CPUSTOP#_3 38-,11- ICH_SMCLK_3 37-,26-,25-,20- PCI5 17 55- CLK_NICPCI_3R
33 DRCG0 PCI4 16 CLK_MINIPCI_3 33_5% 1 R1339 2 54- CLK_MINIPCI_3R
35 DRCG1_VCH PCI3 13
42 IREF CLK_FWHPCI_3 33_5% 1 R1336 2
PCI2 12 59- CLK_FWHPCI_3R
CLK_SIOPCI_3 33_5% 1 R1342 2
1 PCI1 11 42- CLK_SIOPCI_3R
41 VSSIREF
R1335 R1341 2
475_1% 4 CLK_KBCPCI_3 33_5% 1
VSS PCI0 10 40- CLK_KBCPCI_3R
2 9 VSS R1334 2
15 USB 39 CLK_ICH48_3 33_5% 1 38-
VSS CLK_ICH48_3R
20 VSS ADI48M_3 R1361 2
31 OPEN
VSS DOT 38 1 45- ADI48M
36 VSS
47 R1584 2
VSS REF 56 1
+V3S 33_5%
ICS_950810_TSSOP_56P CLK_SIO14_3 33_5% 1 R1316 2 42- CLK_SIO14_3R
33_5% 1 R1315 2 38- CLK_ICH14_3R
33_5% 1 R1317 2 40- CLK_KBC14_3R
1
R1366
10K_5%
2

Q1040 3
D

PM_VGATE 11- 2G
S

NDS7002A 1

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
CLOCK_GENEATOR
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 15 of 67
EE2 Thursday, July 31, 2003 10:53:30 am A02 PC8803

 H_A#(3:16) 22-
GTL4/8

GTL4/8
CN19 GTL4/8

H_A#(3) P4 N2 23-
GTL4/8
A3# ADS# L1
GTL4/8
H_ADS# +VCCP
H_A#(4)
GTL4/8
U4 A4# BNR# 23- GTL4/8
H_BNR#
H_A#(5) V3 J3 23-
GTL4/8
A5# BPRI# H_BPRI#
H_A#(6)
GTL4/8
R3 A6# GTL4/8
1
L4

ADDR GROUP 0
H_A#(7)
GTL4/8
V2 A7# DEFER# 23- GTL4/8
H_DEFER#
H_A#(8) W1 H2 23- R261
GTL4/8
A8# DRDY# M2
GTL4/8
H_DRDY# 56_5%
H_A#(9)
GTL4/8
T4 A9# DBSY# 23- GTL4/8
H_DBSY#
H_A#(10)
GTL4/8
W2 A10# 2
Y4 N4

CONTROL
H_A#(11)
GTL4/8
A11# BR0# 23- H_BR0#
H_A#(12) Y1 A12# A4
GTL4/8 GTL4/8

H_A#(13)
GTL4/8
U1 A13# IERR#
H_A#(14) AA3 B5 59-,37-
GTL4/8
A14# INIT# GTL4/8
H_INIT#
H_A#(15) Y3 A15#
H_A#(16) AA2 J2 23-
GTLDQS5/15-4/12 GTL4/8
A16# LOCK# GTL4/8
H_LOCK#
H_REQ#(4:0) 22- H_ADSTB#0 22- U3
GTL4/8
ADSTB#0 GTL4/8

H_REQ#(0) R2 B11 22-,19- 23-

GTL4/8
REQ0# RESET# GTL4/8
H_CPURST# H_RS#(0:2)
H_REQ#(1) P3 H1 H_RS#(0)
GTL4/8
REQ1# RS0# GTL4/8

K1
H_REQ#(2) T2
AGP4/8
REQ2# RS1# H_RS#(1) GTL4/8

H_REQ#(3) P1 L2 H_RS#(2)
REQ3# RS2#
H_REQ#(4) T1 M3 23-
GTL4/8
REQ4# TRDY# H_TRDY#
H_A#(17:31) 22- GTL4/8 GTL4/8

H_A#(17) AF4 K3 23-

GTL4/8
A17# HIT# GTL4/8
H_HIT#
H_A#(18) AC4 K4 23-
GTL4/8
A18# HITM# H_HITM#
H_A#(19) AC7
GTL4/8
A19# +VCCP
H_A#(20) AC3 C8 19-
GTL4/8
A20# BPM#0 B8 19- H_BPM0_ITP#
H_A#(21) AD3 A21# BPM#1
GTL4/8

H_BPM1_ITP#

ADDR GROUP 1
H_A#(22) AE4 A9 19-
GTL4/8
A22# BPM#2 C9 H_BPM2_ITP# 1
POWER15/5

ITP SIGNALS
H_A#(23) AD2 19-
GTL4/8
A23# BPM#3 A10 19- H_BPM3_ITP# R1140
H_A#(24) AB4 A24# PRDY# 19- H_TCK
H_A#(25)
GTL4/8

AC6 B10 19- H_BPM4_PRDY# 150_5%

GTL4/8
A25# PREQ# H_BPM5_PREQ#
H_A#(26) AD5 A13 19-
GTL4/8
A26# TCK C12 H_TCK 2
H_A#(27) AE2
GTL4/8
A27# TDI 19- TDI_FLEX
H_A#(28) AD6 A12 19-
GTL4/8
A28# TDO H_TDO
H_A#(29) AF3 C11 19-
GTL4/8
A29# TMS B13 H_TMS
H_A#(30) AE1 A30# TRST# 19- H_TRST#
H_A#(31) AF1 A7 38-,19-
GTLDQS5/15-4/12
A31# DBR# ITP_DBRESET# LAYOUT NOTES
GTL4/8
H_ADSTB#1 22- AE5 ADSTB#1 B17 TP1 H_TCK FORKS
PROCHOT# B18

THERM
1
H_A20M# 37-
GTL4/8
C2 A20M# THERMDA 20- THERM10/10
H_THERMDA AT CPU PIN
37- D3 FERR# A18 20- R1120
H_FERR_S# GTL4/8
THERMDC C17 THERM10/10
H_THERMDC 680_5%
H_IGNNE# 37- A3 IGNNE# THERMTRIP# 38- PM_THRMTRIP#
GTL4/8
2 POWER15/5

37-,5- C6 A15
H_STPCLK# GTL4/8
STPCLK# H_CLK ITP_CLK1 A16
H_INTR 37-
GTL4/8
D1 LINT0 ITP_CLK0 B14
H_NMI 37-
GTL4/8
D4 LINT1 BCLK1 B15 15- CLK4/4_25A
CLK_CPU_BCLK#
H_SMI# 37- B4 SMI# BCLK0 15- CLK4/4_25A
CLK_CPU_BCLK

AMP_MPGA479M_C_1376756_479P_BANIAS

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
BANIAS-1
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 16 of 67
EE2 Thursday, July 31, 2003 10:53:36 am A02 PC8803

 H_D#(0:15) 22- CN19 22- H_D#(32:47)
H_D#(0) A19 Y26 H_D#(32)
A25 D0# D32# AA24
H_D#(1) D1# D33# H_D#(33)
H_D#(2) A22 T25 H_D#(34)
B21 D2# D34#
H_D#(3) U23 H_D#(35)
A24 D3# D35# V23
H_D#(4) D4# D36# H_D#(36)
H_D#(5) B26 R24 H_D#(37)
A21 D5# D37#
H_D#(6) R26 H_D#(38)
B20 D6# D38# R23
H_D#(7) H_D#(39)

DATA GRP 0

DATA GRP 2
C20 D7# D39# AA23
H_D#(8) D8# D40# H_D#(40)
H_D#(9) B24 U26 H_D#(41)
D24 D9# D41# V24
H_D#(10) D10# D42# H_D#(42)
H_D#(11) E24 U25 H_D#(43)
C26 D11# D43# V26
H_D#(12) D12# D44# H_D#(44)
H_D#(13) B23 Y23 H_D#(45)
E23 D13# D45#
H_D#(14) AA26 H_D#(46)
C25 D14# D46# Y25
H_D#(15) D15# D47# H_D#(47)
22- C23 W25 22-
H_DSTBN#0 C22 DSTBN0# DSTBN2# H_DSTBN#2
22- W24 22-
H_DSTBP#0 D25 DSTBP0# DSTBP2# T24 H_DSTBP#2
H_DINV#0 22- DINV0# DINV2# 22- H_DINV#2

H_D#(16:31) 22- 22- H_D#(48:63)

H_D#(16) H23 AB25 H_D#(48)
D16# D48#
H_D#(17) G25 AC23 H_D#(49)
D17# D49# AB24
H_D#(18) L23 D18# D50# H_D#(50)
H_D#(19) M26 AC20 H_D#(51)
D19# D51# AC22
H_D#(20) H24 D20# D52# H_D#(52)
H_D#(21) F25 AC25 H_D#(53)
D21# D53# AD23
H_D#(22) G24 D22# D54# H_D#(54)

DATA GRP 1

DATA GRP 3
H_D#(23) J23 AE22 H_D#(55)
D23# D55# AF23
H_D#(24) M23 D24# D56# H_D#(56)
H_D#(25) J25 AD24 H_D#(57)
D25# D57# AF20
H_D#(26) L26 D26# D58# H_D#(58)
H_D#(27) N24 AE21 H_D#(59)
D27# D59#
H_D#(28) M25 AD21 H_D#(60)
D28# D60# AF25
H_D#(29) H26 D29# D61# H_D#(61)
H_D#(30) N25 AF22 H_D#(62)
D30# D62#
H_D#(31) K25 AF26 H_D#(63)
+VCCP D31# D63# AE24
H_DSTBN#1 22- K24 DSTBN1# DSTBN3# 22- H_DSTBN#3
22- L24 AE25 22-
H_DSTBP#1 DSTBP1# DSTBP3# H_DSTBP#3
22- J26 AD20 22-
1 H_DINV#1 DINV1# DINV3# H_DINV#3
R242 AC1
1K_1%
TP570 GTLREF3 COMP0 P25 R244 1 2 27.4_1%
TP571 G1 GTLREF2 COMP1 P26 R243 1 2 54.9_1%
2
TP572 E26 GTLREF1 COMP2 AB2 R1093 1 2 27.4_1%
AD26 GTLREF0 COMP3 AB1 R1091 1 2 54.9_1%
+VCCP
1
A1 NC0 MISC R11181330_5% 2
R241 B2 NC1 B7 37-,21-
2K_1% LAYOUT NOTES : PLACE R1275 , R1276 CLOSE TO CN1008 DPSLP# C19 H_DPSLP#
DPWR# 21- H_DPWR#
2
C14 RSVD1 PWRGOOD E4 37- H_PWRGD
C3 A6 37-
RSVD2 SLP# H_CPUSLP#
AF7 RSVD3
C16 TEST3 TEST1 C5
11- 1 R1088 2 E1 F23
PSI# PSI# TEST2
0_5%
AMP_MPGA479M_C_1376756_479P_BANIAS
1 1 1
R1141 R1147 R260
OPEN OPEN OPEN
2 2 2

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
BANIAS-2
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 17 of 67
EE2 Thursday, July 31, 2003 10:53:41 am A02 PC8803

 +VCC_CORE +VCC_CORE

CN19
AA11 G5
VCC0 VCC59 H22
AA13 VCC60
AA15 VCC1 H6
1 C252 1 C1130 1 C267 1 C284 1 C1114 VCC2 VCC61 J21
AA17 VCC62
AA19 VCC3 J5
2 2 2 2 2 VCC4 VCC63 +V1.8S
AA21 K22 +V1.5S
10UF_K_6.3V 10UF_K_6.3V 10UF_K_6.3V 10UF_K_6.3V VCC5 VCC64 U5
AA5 VCC65
AA7 VCC6 V22
10UF_K_6.3V VCC7 VCC66
AA9 V6
VCC8 VCC67 W21 1
AB10 VCC68 +VCCA
AB12 VCC9 W5 R247 1
VCC10 VCC69 0 R246
AB14 Y22
VCC11 VCC70 Y6 OPEN
AB16 VCC71 2
1 C272 1 C1109 1 C265 1 C1131 1 C271 AB18 VCC12
VCC13 2
AB20 F26 10UF_K_6.3V 10UF_K_6.3V 0.01UF_16V 0.01UF_16V
2 2 2 2 2 VCC14 VCCA0 B1
10UF_K_6.3V 10UF_K_6.3V 10UF_K_6.3V AB22 VCCA1 N1
10UF_K_6.3V AB6 VCC15
VCC16 VCCA2 1 C295 1 C245 1 C1073 1 C294 1 C243 1 C293 1 C1071 1 C1072
AB8 AC26
10UF_K_6.3V VCC17 VCCA3
AC11 2 2 2 2 2 2 2 2
AC13 VCC18 D10
VCC19 VCCP0 D12
AC15 VCCP1 D14
AC17 VCC20
VCC21 VCCP2 10UF_K_6.3V 10UF_K_6.3V 0.01UF_16V 0.01UF_16V
AC19 D16
1 C264 1 C1093 1 C283 1 C1105 1 C1138 VCC22 VCCP3 E11
AC9 VCCP4 E13
AD10 VCC23
2 2 2 2 2 VCC24 VCCP5 +VCCP
AD12 E15
10UF_K_6.3V 10UF_K_6.3V 10UF_K_6.3V 10UF_K_6.3V VCC25 VCCP6 F10
AD14 VCCP7 F12
AD16 VCC26 C1134
10UF_K_6.3V VCC27 VCCP8
AD18 F14
VCC28 VCCP9 F16 0.1UF_16V
AD8 VCCP10 K6
AE11 VCC29
VCC30 VCCP11
AE13 L21
VCC31 VCCP12 L5 1 C1090 1 C1088 1 C1085 1 C1136 1 C1132 1 C1135 1
AE15 VCCP13 M22
1 C1129 1 C1113 1 C1128 1 C1110 1 C1083 AE17 VCC32
VCC33 VCCP14 2 2 2 2 2 2 2
AE19 M6
2 2 2 2 2 VCC34 VCCP15 N21 0.1UF_16V 0.1UF_16V 0.1UF_16V 0.1UF_16V 0.1UF_16V 0.1UF_16V
10UF_K_6.3V 10UF_K_6.3V 10UF_K_6.3V AE9 VCCP16 N5
10UF_K_6.3V AF10 VCC35
VCC36 VCCP17 P22
10UF_K_6.3V AF12 VCCP18 P6
AF14 VCC37
VCCP19 R21 100UF_2.5V_METAL
AF16 VCC38
VCC39 VCCP20 R5
AF18 VCCP21 T22
AF8 VCC40 C1108 C1086
VCC41 VCCP22 1 C1089 1 C1087 1 C1133 1 1
D18 T6
VCC42 VCCP23 U21
D20 VCCP24 2 2 2
1 C1084 1 C1106 1 C268 1 C273 1 C1091 D22 VCC43
VCC44 P23 0.1UF_16V 0.1UF_16V 0.1UF_16V 100UF_2.5V_METAL
2 2 2 2 2 D6 VCCQ0 W4
D8 VCC45
10UF_K_6.3V 10UF_K_6.3V 10UF_K_6.3V 10UF_K_6.3V VCC46 VCCQ1
E17
E19 VCC47 E2 11-
10UF_K_6.3V VCC48 VID0 F2 H_VID0
E21 VID1 11- H_VID1
E5 VCC49 F3 11-
VCC50 VID2 H_VID2
E7 G3 11-
VCC51 VID3 G4 H_VID3
E9 VID4 11- H_VID4
F18 VCC52 H4 11-
1 C1092 1 C269 1 C266 1 C1137 1 C282 VCC53 VID5 H_VID5
F20
F22 VCC54 AE7
2 2 2 2 2 VCC55 VCCSENSE
10UF_K_6.3V 10UF_K_6.3V 10UF_K_6.3V F6
10UF_K_6.3V F8 VCC56 AF6
VCC57 VSSSENSE
10UF_K_6.3V G21
VCC58
1 1

AMP_MPGA479M_C_1376756_479P_BANIAS R258 R259

OPEN OPEN
1 C1111 1 C1112 1 C270 1 C1082 1 C1139 2 2

2 2 2 2 2
10UF_K_6.3V 10UF_K_6.3V 10UF_K_6.3V 10UF_K_6.3V
10UF_K_6.3V
NOTES : INSTALL 54.9_1% FOR TESTING

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
BANIAS-3
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 18 of 67
EE2 Thursday, July 31, 2003 10:53:46 am A02 PC8803

 CN19
A2 D13
VSS0 VSS97 D15
A5 VSS1 VSS98
A8 D17
VSS2 VSS99 D19
A11
VSS3 VSS100 D21
A14 VSS4 VSS101
A17 D23
VSS5 VSS102 D26
A20
VSS6 VSS103 E3
A23 VSS7 VSS104
A26 E6
VSS8 VSS105 E8
AA1
VSS9 VSS106 E10
AA4 VSS10 VSS107
AA6 E12
VSS11 VSS108 E14
AA8 VSS12 VSS109
AA10 E16
VSS13 VSS110 E18
AA12
VSS14 VSS111 E20
AA14 VSS15 VSS112
AA16 E22
VSS16 VSS113 E25
AA18
VSS17 VSS114 F1
AA20 VSS18 VSS115
AA22 F4
VSS19 VSS116 F5
AA25
VSS20
AB3
AB5
VSS21
VSS22
VSS117
VSS118
VSS119
F7
F9 In-Target Probe
AB7 F11
VSS23 VSS120 F13
AB9 VSS24 VSS121
AB11 F15
VSS25 VSS122 F17
AB13
VSS26 VSS123 F19
AB15 VSS27 VSS124 +VCCP +VCCP +VCCP
AB17 F21
VSS28 VSS125 F24
AB19
VSS29 VSS126 G2
AB21 VSS30 VSS127
AB23 G6
VSS31 VSS128 G22
AB26 VSS32 VSS129
AC2 G23
VSS33 VSS130 G26 1 C1074
AC5
VSS34 VSS131 H3 1 1 1
AC8 VSS35 VSS132 2 0.1UF_16V +V3A
AC10 H5 R1105 R1124 R1123
VSS36 VSS133 H21 54.9_1% 54.9_1% 39.2_1%
AC12
VSS37 VSS134 H25
POWER15/5

AC14 VSS38 VSS135 2 2 2 POWER15/5

AC16 J1 CN1002
VSS39 VSS136 1 1
AC18
VSS40 VSS137
J4
TDI_FLEX 16- 1 27 27
AC21 J6 16- 2 2 28 28 R1106
VSS41 VSS138 H_TMS 5
POWER15/5

240_5%
AC24 VSS42 VSS139
J22
H_TCK 16- 5 26 26
AD1 J24 16- R11251 2 22.6_1% 7 7
VSS43 VSS140 H_TDO 2
AD4 K2 16- 3 3
VSS44 VSS141 H_TRST# GTL4/8

AD7 VSS45 VSS142

K5 25 25 38-,16- ITP_DBRESET#
AD9 K21 22-,16- R11221 2 22.6_1% 12 12 24 24
VSS46 VSS143 H_CPURST#
AD11 K23
VSS47 VSS144 K26 11 11
AD13 VSS48 VSS145 H_TCK 16-
AD15 L3 23 23 16-
VSS49 VSS146 L6 8 8 21 H_BPM0_ITP#
AD17 VSS50 VSS147 CLK_ITP# 15-
CLK4/4_25A 21 16- H_BPM1_ITP#
AD19 L22 15- 9 9 19 19 16-
VSS51 VSS148 L25 CLK_ITP CLK4/4_25A

17 H_BPM2_ITP#
AD22 VSS52 VSS149 17 16- H_BPM3_ITP#
AD25 M1 10 10 15 15 16-
VSS53 VSS150 M4 14 13 H_BPM4_PRDY#
AE3 14 13 16- H_BPM5_PREQ#
VSS54 VSS151 M5 1
16
AE6 VSS55 VSS152 16
AE8 M21 R1121 18 18
VSS56 VSS153 M24 27.4_1% 20
AE10
VSS57 VSS154 20 4 4
AE12 N3 22 22 6 6
VSS58 VSS155 N6 2
AE14 VSS59 VSS156
AE16 N22 MLX_52435_2891
VSS60 VSS157 N23
AE18 VSS61 VSS158
AE20 N26
VSS62 VSS159 P2
AE23
VSS63 VSS160 P5
AE26 VSS64 VSS161
AF2 P21
VSS65 VSS162 P24
AF5
VSS66 VSS163 R1
AF9 VSS67 VSS164
AF11 R4
VSS68 VSS165 R6
AF13 VSS69 VSS166
AF15 R22
VSS70 VSS167 R25
AF17 VSS71 VSS168
AF19 VSS72 VSS169
T3 LAYOUT NOTES : H_CPURST# PIN OF MCH_M FORK OUT INTO TWO BRANCHES ON CPU AND ITP CONNECTOR
AF21 T5
VSS73 VSS170 T21
AF24
VSS74 VSS171 T23
B3 VSS75 VSS172
B6 T26
VSS76 VSS173 U2
B9
VSS77 VSS174 U6
B12 VSS78 VSS175
B16 U22
VSS79 VSS176 U24
B19
VSS80 VSS177 V1
B22 VSS81 VSS178
B25 V4
VSS82 VSS179 V5
C1
VSS83 VSS180 V21
C4 VSS84 VSS181
C7 V25
VSS85 VSS182 W3
C10
VSS86 VSS183 W6
C13 VSS87 VSS184
C15 W22
VSS88 VSS185 W23
C18 VSS89 VSS186
C21 W26
VSS90 VSS187 Y2
C24 VSS91 VSS188
D2 Y5
VSS92 VSS189 Y21
D5 VSS93 VSS190
D7 Y24
VSS94 VSS191
D9 VSS95
D11 VSS96
Engineer
AMP_MPGA479M_C_1376756_479P_BANIAS David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
BANIAS-4
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 19 of 67
EE2 Thursday, July 31, 2003 10:53:51 am A02 PC8803

 +V5

CN20

1 C296 1 C1060 1 VCC

3
2 1UF_10V 2 0.01UF_16V 2 GND
D5 3
REFENCE

1
+V3S BAT54
MLX_53398_0390_3P

U17 Q13 3
FAN_PWM_3 40- 1 5 D
4 1 R262 2 1G
TEMP_WARN#_3
38-,20- 2 1K_5% S

3 FDV303N 2
NC7SZ00M5

+V3S

1 C111 1 C285
2 0.1UF_16V 2 0.1UF_16V

+V3S
U15
6 VCC PWM_OUT1 1
37-,26-,25-,15- 16 SCL TACH1_AIN1 2
ICH_SMCLK_3
37-,26-,25-,15- 15 SDA PWM_OUT2 3
ICH_SMDAT_3 R1435 2
16- 9 D1-_NT1 TACH2_AIN2 4 1
H_THERMDC 16-
H_THERMDA 10 D+ 2.2K_5%
C287 7 38-,20-
THERM# TEMP_WARN#_3
1 2 FAN_FAULT# 8
2200PF_50V 11 D2- INT#_NTO 14 37-
13 THERM_SCI#
DMINUS 30- 12 D2+ ADD
GND 5
30-
DPLUS C286
ANLG_ADM1031ARQ_QSOP_16P
1 2
OPEN

LAYOUT NOTES: PUT THE THERMAL SENSOR CLOSE TO CPU Engineer

David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
THERMAL&FAN CONTROLLER
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 20 of 67
EE2 Wednesday, August 13, 2003 10:20:09 pm A02 PC8803

 M_A(12:0)

AGP_AD(31:0)
27-,28-,26-

M_A(0)
M_A(1)
M_A(2)
M_A(3)
M_A(4)
M_A(5)
M_A(6)
M_A(7)
M_A(8)
M_A(9)
M_A(10)
M_A(11)
M_A(12)

29-
U16
SMA0 E12
R27 GAD0 SMA1 F17
R28 GAD1 SMA2 E16
T25 GAD2 SMA3 G17
R25 GAD3 SMA4 G18
T26 GAD4 SMA5 E18
T27 GAD5 SMA6 F19
U27 GAD6 SMA7 G20
U28 GAD7 SMA8 G19
V26 GAD8 SMA9 F21
V27 GAD9 SMA10 F13
T23 GAD10 SMA11 E20
U23 GAD11 SMA12 G21
T24 GAD12 RSVD2 G22
U24 GAD13
U25 GAD14 SDQ0 G28

AGPREF
V24 GAD15 SDQ1 F27
Y27 GAD16 SDQ2 C28
Y26 GAD17 SDQ3 E28
AA28 GAD18 SDQ4 H25
AB25 GAD19 SDQ5 G27
AB27 GAD20 SDQ6 F25
AA27 GAD21 SDQ7 B28
AB26 GAD22 SDQ8 E27
Y23 C27
27-

GAD23 SDQ9
AB23 GAD24 SDQ10 B25

AGP_CBE#(3:0)
AA24 C25

1 C1165
GAD25 SDQ11
AA25 GAD26 SDQ12 B27

AGP_PAR
AB24 D27

2 0.1UF_16V
GAD27 SDQ13

AGP_GNT#
AGP_REQ#
29-

AGP_IRDY#
AC25 D26

AGP_STOP#
AGP_TRDY#
GAD28 SDQ14

AGP
AC24 E25

AGP_FRAME#
GAD29 SDQ15

AGP_DEVSEL#
AC22 GAD30 SDQ16 D24
AD24 GAD31 SDQ17 E23
C22
M_DATA(63:0)

SDQ18

29-
29-
29-
29-
29-
29-
29-
29-
V25 GCBE0# SDQ19 E21
V23 GCBE1# SDQ20 C24
Y25 GCBE2# SDQ21 B23
AA23 GCBE3# SDQ22 D22
SDQ23 B21
Y24 GFRAME# SDQ24 C21
W28 GDEVSEL# SDQ25 D20

2
1
W27 GIRDY# SDQ26 C19
W24 GTRDY# SDQ27 D18

AGP_SBA(7:0)
AGP_ADSTB1#
AGP_ADSTB1
AGP_ADSTB0#
AGP_ADSTB0
CLK_MCH66

+V1.5S
W23 GSTOP# SDQ28 C20

R237
W25 GPAR SDQ29 E19
AG24 GREQ# SDQ30 C18

8.2K_1%
29-
29-
29-
29-
29-
15-
AH25 GGNT# SDQ31 E17

R227 40.2_1%
1
GRCOMP AD25 E13
GRCOMP SDQ32
AA21 AGPREF SDQ33 C12
P22 66IN SDQ34 B11
SDQ35 C10
R24 AD_STB0 SDQ36 B13
R23 AD_STB#0 SDQ37 C13
AC27 AD_STB1 SDQ38 C11
AC28 AD_STB#1 SDQ39 D10
SDQ40 E10
AH28 C9

AGP_ST2
AGP_ST1
AGP_ST0
AGP_WBF#
AGP_RBF#
AGP_SBSTB#
AGP_SBSTB
MEMORY

SBA0 SDQ41
AH27 SBA1 SDQ42 D8
AG28 SBA2 SDQ43 E8

29-
29-
29-
29-
29-
29-
29-
AG27 SBA3 SDQ44 E11
AE28 SBA4 SDQ45 B9
AE27 SBA5 SDQ46 B7
AE24 SBA6 SDQ47 C7
AE25 SBA7 SDQ48 C6
AF27 SB_STB SDQ49 D6
AF26 SB_STB# SDQ50 D4
SDQ51 B3
SDQ52 E6
AE22 RBF# SDQ53 B5
AE23 WBF# SDQ54 C4
AF22 PIPE# SDQ55 E4
M_DQS_R(7:0)

AG25 ST0 SDQ56 C3

AF24 ST1 SDQ57 D3
AG26 ST2 SDQ58 F4
SDQ59 F3
SDQ60 B2
SDQ61 C2
P25 HI_0 SDQ62 E2
28-,26-,25-

P24 G4

EE2
HI_1 SDQ63
N27 HI_2 SDQ64 C16
P23 HI_3 SDQ65 D16
M26 HI_4 SDQ66 B15

Changed by
M25 HI_5 SDQ67 C14
L28 HI_6 SDQ68 B17
L27 C17
1
1
1
1
1
1
1
1

HI_7 SDQ69
M27 C15
HUB

HI_8 SDQ70
N28 HI_9 SDQ71 D14
M24
10_5%

HI_10
R1205
R1191
R1170
R1161

N25 F26 M_DQS0

R1228 2
2
2
2
2
2
2
2

HI_STB SDQS0
N24 C26 M_DQS1
HI_STB# SDQS1
2
1

HUB_RCOMP P27 C23 M_DQS2

HLRCOMP SDQS2
P26 B19 M_DQS3
10_5%
10_5%
10_5%
10_5%
R1156 10_5%
R1155 10_5%
R1143 10_5%

HI_REF SDQS3 M_DQS4

SDQS4 D12

Date Changed
C8 M_DQS5
SDQS5 M_DQS6
C5
+V1.8S

SDQS6 M_DQS7
R1167
36.5_1%

J27 RSTIN# SDQS7 E3

H27 RSVD1 SDQS8 E15
Thursday, July 31, 2003
H26 TESTIN#
SWE# G11
SCAS# G8
SRAS# F11
G23 SCKE0
E22 SCKE1
M_WE#

H23 SCKE2 SCK0 J25

M_CAS#

F23 SCKE3 SCK#0 K25

M_RAS#

SCK1 G5
M_BS0# G12 F5
M_BS1#
SBS0 SCK#1
G13 SBS1 SCK2 G24
M_CS0 21- E9 SCS#0 SCK#2 E24
M_CS1 21- F7 SCS#1 SCK3 G25
10:54:07 am

21- F9 J24

M_CS2 SCS#2 SCK#3

MEMORY

Time Changed

M_CS3 21- E7 SCS#3 SCK4 G6

G7
M_CS0
M_CS1
M_CS2
M_CS3

M_RCOMP
SCK#4
J28 SMRCOMP SCK5 K23
J23
37-
37-
37-
55-,48-,37-,29-
28-,25-
28-,25-
28-,26-
28-,26-
28-,27-,26-
28-,27-,26-
21-
21-
21-
21-

G15RCVENIN# SCK#5
25-
25-
25-
25-

G14RCVENOUT#
David Du
David Du
TP540

QA CHK
28-,27-,26-
28-,27-,26-
28-,27-,26-

Engineer

Drawn by

R&D CHK
2
2
2
2

AD26 NC0
TP539
TP545
TP544

AD27 NC1
DOC CTRL CHK

MFG ENGR CHK

M_RCVIN

M_BS0#
M_BS1#

V8 DPSLP#
M_WE#

100MILS(+-5MILS)

M_CKE0_R#
M_CKE1_R#
M_CKE2_R#
M_CKE3_R#
M_RAS#
M_CAS#

Y8 DPWR# SDREF0 J21

HUB_PSTRB
HUB_PSTRB#

HUB_PD(10:0)

SDREF1 J9
M_CLK_DDR2
M_CLK_DDR1

PCI_RESET1#_3
1 28-,25-
1 28-,25-
1 28-,26-
1 28-,26-
37-,17-
17-
26-
26-
26-
26-
M_CLK_DDR2#
M_CLK_DDR1#

VER
A02
TITLE
TP547
TP546

C1148

ITL_ODEM_BGA_593P
2
1

R253 R254 R252 R251

1 C218 30_1%
1 R2282

PC8803
C1190
MCH_TEST#
0_5% 0_5% 0_5% 0_5%
H_DPWR#

M_CS0_R#
M_CS1_R#
M_CS2_R#
M_CS3_R#

ODEM-1
0.01UF_16V
2
1
2

HUB_VREF_MCH

Model Number
M_CLK_DDR5
M_CLK_DDR4

M_CLK_DDR5#
M_CLK_DDR4#

1
SM_VREF

0.1UF_16V 0.1UF_16V
1 C1180

H_DPSLP# +V1.25S
26-,25-,12-

OPEN
R229

DIAMOND
2

Sheet
1 C1191
2 0.1UF_16V

+V1.5S

21
2 0.1UF_16V
2
2

1
1

of
SM_VREF

INVENTEC
+V1.8S

67
Size
R1168
R1169

A3
150_1%
150_1%
 17- H_D#(63:0)
H_A#(31:3) 16-
U16
U6 HA3# HD0# AA2
T5 HA4# HD1# AB5
R2 HA5# HD2# AA5
U3 HA6# HD3# AB3
R3 HA7# HD4# AB4
P7 HA8# HD5# AC5
T3 HA9# HD6# AA3
P4 HA10# HD7# AA6
P3 HA11# HD8# AE3
P5 HA12# HD9# AB7
R6 HA13# HD10# AE5
N2 HA14# HD11# AF3
N5 HA15# HD12# AC6
N3 HA16# HD13# AC3
J3 HA17# HD14# AF4
M3 HA18# HD15# AE2
M4 HA19# HD16# AG4
M5 HA20# HD17# AG2
L5 HA21# HD18# AE7
K3 HA22# HD19# AE8
J2 HA23# HD20# AH2
N6 HA24# HD21# AC7
L6 HA25# HD22# AG3

HOST
L2 HA26# HD23# AD7
K5 HA27# HD24# AH7
L3 HA28# HD25# AE6
L7 HA29# HD26# AC8
K4 HA30# HD27# AG8
H_REQ#(4:0) 16- J5 HA31# HD28# AG7
HD29# AH3
+VCCP U2 HREQ0# HD30# AF8
T7 HREQ1# HD31# AH5
R7 HREQ2# HD32# AC11
U5 HREQ3# HD33# AC12
T4 HREQ4# HD34# AE9
H_ADSTB#0 16- R5 HADSTB0# HD35# AC10
1 C1140 16- N7 AE10
1 H_ADSTB#1 HADSTB1# HD36#
AD9
R1149 2 0.1UF_16V 15- K8
HD37#
AG9
301_1% CLK_MCH_BCLK# BCLK# HD38#
CLK_MCH_BCLK 15- J8 BCLK HD39# AC9
2 HYRCOMP AC13 HRCOMP1 HD40# AE12
HYSWING AD13 HSWNG1 HD41# AF10
HXRCOMP AC2 HRCOMP0 HD42# AG11
1
AA7 HSWNG0 HD43# AG10
HD44# AH11
R1148 17- AD4 AG12
150_1% H_DSTBN#0 HDSTBN0# HD45#
1 1 H_DSTBN#1 17- AF6 HDSTBN1# HD46# AE13
2 H_DSTBN#2 17- AD11 HDSTBN2# HD47# AF12
R1160 R1142 17- AC15 AG13
27.4_1% 27.4_1% H_DSTBN#3 HDSTBN3# HD48#
H_DSTBP#0 17- AD3 HDSTBP0# HD49# AH13
2 2 H_DSTBP#1 17- AG6 HDSTBP1# HD50# AC14
H_DSTBP#2 17- AE11 HDSTBP2# HD51# AF14
HYSWING, HXSWING 12 mil trace, 10 mil space 17- AC16 AG14
H_DSTBP#3 HDSTBP3# HD52#
+VCCP H_DINV#0 17- AD5 DBI0# HD53# AE14
H_DINV#1 17- AG5 DBI1# HD54# AG15
H_DINV#2 17- AH9 DBI2# HD55# AG16
H_DINV#3 17- AD15 DBI3# HD56# AG17
LAYOUT NOTES HD57# AH15
H_CPURST# 19-,16- AE17 CPURST# HD58# AC17
1 1 C1142 H_CPURST# FORKS 19-,16- AF16
R1150 H_CPURST# HD59#
2 0.1UF_16V AT ODEM PIN M7 HVREF0 HD60# AE15
301_1% P8 AH17
HVREF1 HD61#
2
AA9 HVREF2 HD62# AD17
AB12 HVREF3 HD63# AE16
HXSWING MCH_GTLREF AB16 HVREF4
1
R1151
150_1% ITL_ODEM_BGA_593P
2 +VCCP

1
R1152
49.9_1%
2

1 1 C1144 1 C1166 1 C1143 1 C308 1 C309 1 C310

R1153 2
100_1% 1UF_10V2 2 220P_25V 2 220P_25V 2 220P_25V 2 220P_25V

220P_25V CLOSE TO MCH

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
ODEM-2
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 22 of 67
EE2 Thursday, July 31, 2003 10:54:13 am A02 PC8803

 +V1.5S
POWER15/5

U16
ADS# U7 16-
GTL4/8
H_ADS#
10UF_K_6.3V HTRDY# V4 16-
GTL4/8
H_TRDY#
AA22 VCCAGP0 DRDY# W2 16-
GTL4/8
H_DRDY#
AA26 VCCAGP1 DEFER# Y4 16-
GTL4/8
H_DEFER#
R22 Y3 16-

HOST
1 C1211 1 C1168 1 C1172 1 C214 1 C1163 1 C1210 1 C233 1 C1167 1 C1171 VCCAGP2 HITM# GTL4/8
H_HITM#
R29 VCCAGP3 HIT# Y5 16-
GTL4/8
H_HIT#
2 2 2 2 2 2 2 2 2 U22 VCCAGP4 HLOCK# W3 16-
GTL4/8
H_LOCK#
U26 VCCAGP5 BR0 V7 16- H_BR0#
0.1UF_16V 0.1UF_16V 0.1UF_16V 0.1UF_16V 0.1UF_16V 0.1UF_16V W22 V3 16-
VCCAGP6 BNR# GTL4/8
H_BNR#
10UF_K_6.3V W29 VCCAGP7 BPRI# Y7 16-
GTL4/8
H_BPRI#
10UF_K_6.3V AB21 V5 16-
VCCAGP8 DBSY# GTL4/8
H_DBSY#
AC29 VCCAGP9 RS0# W7
AD21 VCCAGP10 RS1# W5 GTL4/8

AD23 VCCAGP11 RS2# W6 GTL4/8

AE26 VCCAGP12 GTL4/8

+V1.2_MCH AF23 VCCAGP13 VTT0 AB10 16- H_RS#(2:0)

AG29 VCCAGP14 VTT1 AB14
AJ25 VCCAGP15 VTT2 AB18
VTT3 AB20 +VCCP
VTT4 AB8
0.22UF_K_10V 100UF_2.5V_METAL VTT5 AC19
N14 VCC0 VTT6 AD18 C234
N16 AD20 100UF_2.5V_METAL
C1178 C1170 VCC1 VTT7 0.1UF_16V
P13 VCC2 VTT8 AE19
1 C1169 1 C1173 1 C1174 1 C1175 1 C1176 1 C1146
POWER15/5

1 1 P15 AE21 C246 C247

VCC3 VTT9 1 1 1 C248 1 C249 1 C1141 1 C1145 1
2 2 0.047UF_10V
2 0.022UF_16V 2 0.01UF_16V
2 2 P17 VCC4 VTT10 AF18
0.015UF R14 VCC5 VTT11 AF20 2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V 2 0.1UF_16V 2
R16 VCC6 VTT12 AG19
2.2UF_0805_16V T15 VCC7 VTT13 AG21 100UF_2.5V_METAL
100UF_2.5V_METAL U14 AG23
+V1.8S VCC8 VTT14
U16 VCC9 VTT15 AJ19
1 C1147 1 C1164 1 C235
POWER15/5

VTT16 AJ21
VTT17 AJ23 2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V
VTT18 M8
VTT19 T8
L25 VCCHL0
L29 VCCHL1 VCCSM0 A13
1 C1192 1 C1214 1 C1177 1C1179 M22 A17
VCCHL2 VCCSM1
2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V 2 N23 VCCHL3 VCCSM2 A21
N26 VCCHL4 VCCSM3 A25
10UF_K_6.3V VCCSM4 A5 +V2.5
VCCSM5 A9
VCCSM6 C1
VCCSM7 C29
VCCSM8 D11
VCCSM9 D15
VCCSM10 D19
VCCSM11 D23
D25 1 C215 1 C1193 1 C216 1 C1149 1 C1150 1 C1184
VCCSM12
G16 RSVD3 VCCSM13 D7 2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V
G10 RSVD4 VCCSM14 E5
G9 RSVD5 VCCSM15 F10
H7 RSVD6 VCCSM16 F14
ETS# 25- H4 ETS# VCCSM17 F16 C278
H3 F18 1 1 C253 1 C1182 1 C1181 1 C1183 1 C1194 1 C236
RSVD7 VCCSM18
G3 RSVD8 VCCSM19 F22 2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V
+V1.8S G2 RSVD9 VCCSM20 G1
VCCSM21 G29 150UF_4V_METAL
VCCSM22 H10
H12 C1215
VCCSM23
H14 1 C250 1 C1115
POWER15/5

1 C276 1 1 C277 1 C275

VCCSM24
VCCSM25 H16 2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V
POWER15/5
2 10UF_K_6.3V2 10UF_K_6.3V
VCCSM26 H18
T17 VCCGA VCCSM27 H20 150UF_4V_METAL
T13 VCCHA
POWER15/5
VCCSM28 H22
VCCSM29 H24
C1212 H5
1 VCCSM30
C1213 1 VCCSM31 H8
0.01UF_16V 2 2 10UF_K_6.3V VCCSM32 J6
VCCSM33 K22
VCCSM34 K24
VCCSM35 K26
VCCSM36 K7
VCCSM37 L23

ITL_ODEM_BGA_593P

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
ODEM-3
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 23 of 67
EE2 Thursday, July 31, 2003 10:54:19 am A02 PC8803

 U16
A11 VSS0 VSS71 E14
A15 VSS1 VSS72 E26
A19 VSS2 VSS73 E29
A23 VSS3 VSS74 F12
A27 VSS4 VSS75 F15
A3 VSS5 VSS76 F20
A7 VSS6 VSS77 F24
AA1 VSS7 VSS78 F6
AA29 VSS8 VSS79 F8
AA4 VSS9 VSS80 G26
AA8 VSS10 VSS81 H11
AB11 VSS11 VSS82 H13
AB13 VSS12 VSS83 H15
AB15 VSS13 VSS84 H17
AB17 VSS14 VSS85 H19
AB19 VSS15 VSS86 H21
AB22 VSS16 VSS87 H6
AB6 VSS17 VSS88 H9
AB9 VSS18 VSS89 J1
AC1 VSS19 VSS90 J22
AC18 VSS20 VSS91 J26
AC20 VSS21 VSS92 J29
AC21 VSS22 VSS93 J4
AC23 VSS23 VSS94 J7
AC26 VSS24 VSS95 K27
AC4 VSS25 VSS96 K6
AD10 VSS26 VSS97 L1
AD12 VSS27 VSS98 L22
AD14 VSS28 VSS99 L24
AD16 VSS29 VSS100 L26
AD19 VSS30 VSS101 L4
AD22 VSS31 VSS102 L8
AD6 VSS32 VSS103 M23
AD8 VSS33 VSS104 M6
AE1 VSS34 VSS105 N1
AE18 VSS35 VSS106 N13
AE20 VSS36 VSS107 N15
AE29 VSS37 VSS108 N17
AE4 VSS38 VSS109 N22
AF11 VSS39 VSS110 N29
AF13 VSS40 VSS111 N4
AF15 VSS41 VSS112 N8
AF17 VSS42 VSS113 P14
AF19 VSS43 VSS114 P16
AF21 VSS44 VSS115 P6
AF25 VSS45 VSS116 R1
AF5 VSS46 VSS117 R13
AF7 VSS47 VSS118 R15
AF9 VSS48 VSS119 R17
AG1 VSS49 VSS120 R26
AG18 VSS50 VSS121 R4
AG20 VSS51 VSS122 R8
AG22 VSS52 VSS123 T14
AH19 VSS53 VSS124 T16
AH21 VSS54 VSS125 T22
AH23 VSS55 VSS126 T6
AJ11 VSS56 VSS127 U1
AJ13 VSS57 VSS128 U13
AJ15 VSS58 VSS129 U15
AJ17 VSS59 VSS130 U17
AJ27 VSS60 VSS131 U29
AJ3 VSS61 VSS132 U4
AJ5 VSS62 VSS133 U8
AJ7 VSS63 VSS134 V22
AJ9 VSS64 VSS135 V6
D13 VSS65 VSS136 W1
D17 VSS66 VSS137 W26
D21 VSS67 VSS138 W4
D5 VSS68 VSS139 W8
D9 VSS69 VSS140 Y22
E1 VSS70 VSS141 Y6

ITL_ODEM_BGA_593P
POWER15/5

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
ODEM-4
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 24 of 67
EE2 Thursday, July 31, 2003 10:54:24 am A02 PC8803

M_A_FR_(12:0) 27- 28-,27-,26- M_DATA_R_(63:0)

CN15
112 5
A0 DQ0
111 A1 DQ1 7
110 A2 DQ2 13
109 17
A3 DQ3
108 A4 DQ4 6
107 A5 DQ5 8
106 A6 DQ6 14
105 A7 DQ7 18
102 19
A8 DQ8
101 A9 DQ9 23
115 A10_AP DQ10 29
100 31 +V2.5
A11 DQ11
99 A12 DQ12 20
97 A13_DU DQ13 24

201
202
30
M_BS0_FR# 27- 117
DQ14
32 CN15
M_BS1_FR# BA0 DQ15 GG
+V2.5 27- 116 BA1 DQ16 41 9 VDD1 VSS1 3
98 43 21 15
BA2_DU DQ17 VDD2 VSS2
71 CB0 DQ18 49 33 VDD3 VSS3 27
73 53 1 C1187 1 C1198 1 C1116 1 C1117 1 C1151 45 39
CB1 DQ19 VDD4 VSS4
79 42 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 57 51
CB2 DQ20 VDD5 VSS5
1
83 CB3 DQ21 44 69 VDD6 VSS6 63
72 CB4 DQ22 50 81 VDD7 VSS7 75
R1171 74 54 93 87
OPEN CB5 DQ23 VDD8 VSS8
80 CB6 DQ24 55 113 VDD9 VSS9 103
2
84 CB7 DQ25 59 131 VDD10 VSS10 125
M_CLK_DDR2 21- 35 CK0 DQ26 65 143 VDD11 VSS11 137
21- 37 67 C1241 155 149
M_CLK_DDR2# CK0# DQ27 1 C1185 1 C1186 1 C1197 1 VDD12 VSS12
M_CLK_DDR1# 21- 158 56 157 159
CK1# DQ28 VDD13 VSS13
M_CLK_DDR1 21- 160 CK1 DQ29 60 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 167 VDD14 VSS14 161
89 CK2 DQ30 66 179 VDD15 VSS15 173
91 68 191 185
CK2# DQ31 VDD16 VSS16
M_CKE0_R# 28-,21- 96 CKE0 DQ32 127 150UF_4V_METAL 10 VDD17 VSS17 4
1 M_CKE1_R# 28-,21- 95 CKE1 DQ33 129 22 VDD18 VSS18 16
M_CAS_FR# 27- 120 135 34 28
R1172 CAS# DQ34 VDD19 VSS19
M_RAS_FR# 27- 118 RAS# DQ35 139 36 VDD20 VSS20 38
OPEN 27- 119 128 C181 C311 46 40
M_WE_FR# WE# DQ36 1 1 VDD21 VSS21
M_CS0_R# 28-,21- 121 130 58 52
2 S0# DQ37 VDD22 VSS22
M_CS1_R# 28-,21- 122 S1# DQ38 136 150UF_4V_METAL 150UF_4V_METAL 70 VDD23 VSS23 64
194 SA0 DQ39 140 82 VDD24 VSS24 76
196 141 92 88
SA1 DQ40 VDD25 VSS25
198 SA2 DQ41 145 94 VDD26 VSS26 90
ICH_SMCLK_3 37-,26-,20-,15- 195 SCL DQ42 151 114 VDD27 VSS27 104
ICH_SMDAT_3 37-,26-,20-,15- 193 SDA DQ43 153 132 VDD28 VSS28 126
86 RESET_DU DQ44 142 144 VDD29 VSS29 138
DQ45 146 156 VDD30 VSS30 150
12 DM0 DQ46 152 +V3S 168 VDD31 VSS31 162
26 DM1 DQ47 154 180 VDD32 VSS32 174
48 163 192 186
DM2 DQ48 VDD33 VSS33
62 DM3 DQ49 165
134 DM4 DQ50 171 199 VDDID DU1 85
148 175 197 123
DM5 DQ51 SM_VREF VDDSPD DU2
170 DM6 DQ52 164 SM_VREF 26-,21-,12- 1 VREF1 DU3 124
M_DQS_R(7:0) 28-,26-,21- 184 DM7 DQ53 166 2 VREF2 DU4 200
78 172
DM8 DQ54
DQ55 176
11 177 1 C176
25
DQS0 DQ56
181 AMP_1473005_1_200P
DQS1 DQ57 2 0.1UF_16V
47 DQS2 DQ58 187
61 DQS3 DQ59 189
133 178
DQS4 DQ60
147 DQS5 DQ61 182
169 DQS6 DQ62 188
183 DQS7 DQ63 190
77 DQS8 +V2.5

AMP_1473005_1_200P +V3

SO DIMM 0 U14
R1154
10K_5%

VCC 5
2

1 3 23-
SCK/SCK#(0)=SCK/SCK#(1)=SCK/SCK#(2) SET OUT# ETS#
SCK/SCK#(3)=SCK/SCK#(4)=SCK/SCK#(5)

4 HYST
1

2 GND
DQ=CB=DQS R248
10K_5%
SCK(2:0) be longer than DQS 1"~2"
2 MAX_MAX6509HAUK_T_SOT23_5P
SCK(5:3) be longer than DQS 1"~2"

SDQ(63:0) from MCH to DIMM0 2"~3.5"

SCS#,SCKE from MCH to DIMM0 2"~4.5"
SMA(12:0),SBS(1:0),SRAS#,SCAS#,SWE# 2"~3.5"
SCK 3"~6.5"

Engineer
LAYOUT NOTES : LOCATION MUST BE CENTER OF BOTTON SODIMM 0 David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
DDR-SDRAM-1
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 25 of 67
EE2 Thursday, July 31, 2003 10:54:29 am A02 PC8803

 M_A(12:0) 27-,28-,21- 28-,27-,25- M_DATA_R_(63:0)
CN16
112 A0 DQ0 5
111 A1 DQ1 7
110 13
A2 DQ2
109 A3 DQ3 17
108 A4 DQ4 6
107 A5 DQ5 8
106 A6 DQ6 14
105 18
A7 DQ7
102 A8 DQ8 19 +V2.5
101 A9 DQ9 23
115 29
A10_AP DQ10

201
202
100 31
99
A11
A12
DQ11
DQ12 20 CN16
97 24 9 GG 3
A13_DU DQ13 VDD1 VSS1
DQ14 30 21 VDD2 VSS2 15
M_BS0# 28-,27-,21- 117 32 33 27
M_BS1# BA0 DQ15 1 C1196 1 C217 1 C1195 1 C254 1 C1216 VDD3 VSS3
28-,27-,21- 116 41 45 39
BA1 DQ16 VDD4 VSS4
98 BA2_DU DQ17 43 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 57 VDD5 VSS5 51
71 CB0 DQ18 49 69 VDD6 VSS6 63
+V2.5 73 53 81 75
CB1 DQ19 VDD7 VSS7
79 CB2 DQ20 42 93 VDD8 VSS8 87
83 CB3 DQ21 44 113 VDD9 VSS9 103
72 50 131 125
CB4 DQ22 VDD10 VSS10
1
74 CB5 DQ23 54 143 VDD11 VSS11 137
80 CB6 DQ24 55 155 VDD12 VSS12 149
R240 84 59 1 C1152 1 C1153 1 C1118 157 159
OPEN CB7 DQ25 VDD13 VSS13
M_CLK_DDR5 21- 35 CK0 DQ26 65 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 167 VDD14 VSS14 161
M_CLK_DDR5# 21- 37 67 179 173
2 CK0# DQ27 VDD15 VSS15
M_CLK_DDR4# 21- 158 CK1# DQ28 56 191 VDD16 VSS16 185
M_CLK_DDR4 21- 160 CK1 DQ29 60 10 VDD17 VSS17 4
89 66 22 16
CK2 DQ30 VDD18 VSS18
91 CK2# DQ31 68 34 VDD19 VSS19 28
1 M_CKE2_R# 28-,21- 96 CKE0 DQ32 127 36 VDD20 VSS20 38
28-,21- 95 129 C1312 46 40
R239 M_CKE3_R# CKE1 DQ33 1 C313 VDD21 VSS21
M_CAS# 28-,27-,21- 120 CAS# DQ34 135 58 VDD22 VSS22 52
OPEN 28-,27-,21- 118 139 1 70 64
M_RAS# RAS# DQ35 150UF_4V_METAL VDD23 VSS23
+V3S M_WE# 28-,27-,21- 119 128 82 76
2 WE# DQ36 150UF_4V_METAL VDD24 VSS24
M_CS2_R# 28-,21- 121 S0# DQ37 130 92 VDD25 VSS25 88
M_CS3_R# 28-,21- 122 S1# DQ38 136 94 VDD26 VSS26 90
194 140 114 104
SA0 DQ39 VDD27 VSS27
196 SA1 DQ40 141 132 VDD28 VSS28 126
198 SA2 DQ41 145 144 VDD29 VSS29 138
ICH_SMCLK_3 37-,25-,20-,15- 195 SCL DQ42 151 156 VDD30 VSS30 150
ICH_SMDAT_3 37-,25-,20-,15- 193 SDA DQ43 153 +V3S 168 VDD31 VSS31 162
86 RESET_DU DQ44 142 180 VDD32 VSS32 174
DQ45 146 192 VDD33 VSS33 186
12 DM0 DQ46 152
26 154 199 85
DM1 DQ47 VDDID DU1
48 DM2 DQ48 163 197 VDDSPD DU2 123
62 165 SM_VREF 1 VREF1
DM3 DQ49 SM_VREF 25-,21-,12-
DU3 124
134 171 2 200
DM4 DQ50 VREF2 DU4
148 DM5 DQ51 175
170 DM6 DQ52 164
28-,25-,21- 184 166 1 C177
M_DQS_R(7:0) DM7 DQ53 AMP_C_1279284_1_DDR_SODIMM_200P
78 DM8 DQ54 172 2 0.1UF_16V
DQ55 176
11 177
DQS0 DQ56
25 DQS1 DQ57 181
47 DQS2 DQ58 187
61 189
DQS3 DQ59
133 DQS4 DQ60 178
147 DQS5 DQ61 182
169 DQS6 DQ62 188
183 DQS7 DQ63 190
77 DQS8

AMP_C_1279284_1_DDR_SODIMM_200P

SO DIMM 1
SCK(2:0) be longer than SCS(1:0),CKE(1:0) 1"~3"
SMA(12:0),SBS(1:0)
RAS#,CAS#,WE#

SCK(5:3) be longer than SCS(3:2),CKE(3:2) 1"~3"

SMA(12:0),SBS(1:0)
RAS#,CAS#,WE#

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
DDR-SDRAM-2
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 26 of 67
EE2 Thursday, July 31, 2003 10:54:35 am A02 PC8803

 28-,26-,25- M_DATA_R_(63:0)

DDR4/8 10_5%
RS1030 DDR4/8 DDR4/8 10_5%
RS1010DDR4/8

1
DDR4/8
8 DDR4/8 DDR4/8
1 8
DDR4/8

2
DDR4/8
7 DDR4/8 DDR4/8
2 7
DDR4/8

3
DDR4/8
6 DDR4/8 DDR4/8
3 6
DDR4/8

4 5 4 5

DDR4/8 10_5%
RS1029 DDR4/8 DDR4/8 10_5%
RS1008 DDR4/8

DDR4/8
1 8
DDR4/8
1
DDR4/8
8 DDR4/8

DDR4/8
2 7
DDR4/8
2
DDR4/8
7 DDR4/8

DDR4/8
3 6
DDR4/8
3
DDR4/8
6 DDR4/8

4 5 4 5

DDR4/8 10_5%
RS1025 DDR4/8 DDR4/8 10_5%
RS1005DDR4/8

1
DDR4/8

2
DDR4/8
8
7
DDR4/8

DDR4/8
DDR4/8

DDR4/8
1
2
8
DDR4/8

7
DDR4/8
close to DIMM1<750 mil
3
DDR4/8
6 DDR4/8 DDR4/8
3 6
DDR4/8

4 5 4 5
M_A(12:0) 28-,26-,21-,27- RS1015 10
DDR4/8 DDR4/8
25-,27- M_A_FR_(12:0)
10_5% 10_5% M_A(12) 4 5 M_A_FR_(12)
DDR4/8
RS1024 DDR4/8
RS1009
DDR4/8 DDR4/8 DDR4/8 DDR4/8

DDR4/8
1 8
DDR4/8
1
DDR4/8
8 DDR4/8
M_A(11) 2
DDR4/8
7
DDR4/8
M_A_FR_(11)
DDR4/8
2 7
DDR4/8
2
DDR4/8
7 DDR4/8
M_A(5) 1
DDR4/8
8
DDR4/8
M_A_FR_(5)
DDR4/8
3 6
DDR4/8
3
DDR4/8
6 DDR4/8
M_A(9) 3 6 M_A_FR_(9)
4 5 4 5
RS10
DDR4/8 10 DDR4/8

10_5% 10_5% M_A(8) 3 6 M_A_FR_(8)

RS1021
DDR4/8 DDR4/8 DDR4/8
RS1004DDR4/8 DDR4/8 DDR4/8

1
DDR4/8
8 DDR4/8 DDR4/8
1 8
DDR4/8
M_A(4) 1
DDR4/8
8
DDR4/8
M_A_FR_(4)
2
DDR4/8
7 DDR4/8 DDR4/8
2 7
DDR4/8
M_A(6) 2
DDR4/8
7
DDR4/8
M_A_FR_(6)
3
DDR4/8
6 DDR4/8 DDR4/8
3 6
DDR4/8
M_A(7) 4 5 M_A_FR_(7)
4 5 4 5 DDR4/8 DDR4/8

M_WE# 28-,26-,21- RS1011 10 25- M_WE_FR#

DDR4/8 10_5%
RS1020 DDR4/8 DDR4/8 10_5%
RS1003 DDR4/8
4
DDR4/8
5
DDR4/8

DDR4/8
1 8
DDR4/8
1
DDR4/8
8 DDR4/8
M_A(10) 3
DDR4/8
6
DDR4/8
M_A_FR_(10)
DDR4/8
2 7
DDR4/8
2
DDR4/8
7 DDR4/8
M_A(3) 1
DDR4/8
8
DDR4/8
M_A_FR_(3)
DDR4/8
3 6
DDR4/8
3
DDR4/8
6 DDR4/8
M_A(1) 2 7 M_A_FR_(1)
4 5 4 5
DDR4/8 DDR4/8

M_A(0) 1 R1162 2 M_A_FR_(0)

DDR4/8 10_5%
RS1014 DDR4/8 DDR4/8 10_5%
RS1001DDR4/8

1 8 1 8
DDR4/8 DDR4/8 DDR4/8 DDR4/8
10_5%
2
DDR4/8
7 DDR4/8 DDR4/8
2 7
DDR4/8

3
DDR4/8
6 DDR4/8 DDR4/8
3 6
DDR4/8

4 5 4 5

DDR4/8 10_5%
RS1019 DDR4/8 DDR4/8 10_5%
RS1000 DDR4/8

DDR4/8
1 8
DDR4/8
1
DDR4/8
8 DDR4/8

DDR4/8
2 7
DDR4/8
2
DDR4/8
7 DDR4/8

DDR4/8
3 6
DDR4/8
3
DDR4/8
6 DDR4/8

4 5 4 5

DDR4/8 DDR4/8

28-,26-,21- 1 R1163 2 25-

M_BS0# M_BS0_FR#
10_5%
RS13 10
DDR4/8 DDR4/8

M_BS1# 28-,26-,21- 3
DDR4/8
6
DDR4/8
25- M_BS1_FR#
M_CAS# 28-,26-,21- 1
DDR4/8
8
DDR4/8
25- M_CAS_FR#
M_DATA(63:0) 21- M_A(2) 28-,26-,21-,27- 4
DDR4/8
5 25-,27- DDR4/8
M_A_FR_(2)
M_RAS# 28-,26-,21- 2 7 25- M_RAS_FR#

close to DIMM0<750 mil

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
DDR-SDRAM-3
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 27 of 67
EE2 Thursday, July 31, 2003 10:54:40 am A02 PC8803

 M_CKE0_R# 25-,21-
M_CKE1_R# 25-,21- +V1.25S

M_CKE2_R# 26-,21-
M_A(12:0) 27-,26-,21-,28- M_DQS_R(7:0) M_CKE3_R# 26-,21-
M_DATA_R_(63:0) 27-,26-,25-,28-

R1164 56_5%

56_5%
56_5%
56_5%
56_5%
4 3 2 1 1 2 3 4 4 3 2 1 1 2 3 4 4 3 2 1 1 2 3 4 4 3 2 1 1 2 3 4 1 4 2 3 1 4 2 3 3 4 2 1
1 1 1 1 1

R1193
R1192
R1206
R1235
RS1022 RS9 RS1027 RS8 RS1026 RS7 RS1031 RS5 RS11 RS14 RS1016
56 56 56 56 56 56 56 56 56 56 56

5 6 7 8 8 7 6 5 5 6 7 8 8 7 6 5 5 6 7 8 8 7 6 5 5 6 7 8 8 7 6 5 8 5 7 6 8 5 7 6 2 2 2 2 2 6 5 7 8

R1145 56_5%

R1157 56_5%
R1158 56_5%
1 2 3 4 4 3 2 1 1 2 3 4 4 3 2 1 1 2 3 4 4 3 2 1 1 2 3 4 4 3 2 1 1 1 3 2 4 1 1 1 1 2 4 3 1 4 3 2 1

R1173
56_5%

56_5%
R249
RS1002 RS18 RS1006 RS15 RS1007 RS16 RS1012 RS17 RS12 RS1013 RS1017
56 56 56 56 56 56 56 56 56 56 56
2 2 2 2 2
8 7 6 5 5 6 7 8 8 7 6 5 5 6 7 8 8 7 6 5 5 6 7 8 8 7 6 5 5 6 7 8 8 6 7 5 8 7 5 6 5 6 7 8

M_DATA_R_(63:0) 27-,26-,25-,28-

M_A(12:0) 27-,26-,21-,28-

M_DQS_R(7:0) 26-,25-,21-,28-

close to DIMM1< 800mil M_CS2_R#

M_CS3_R#
26-,21-
26-,21-

M_CS0_R# 25-,21-
M_CS1_R# 25-,21-

M_BS0# 27-,26-,21-
M_BS1# 27-,26-,21-

M_WE# 27-,26-,21-
+V1.25S
M_RAS# 27-,26-,21-

M_CAS# 27-,26-,21-

1 C279 1 C1200 1 C1188 1 C221 1 C220 1 C193 1 C180 1 C259 1 C1158

Close to DDR as passible
2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V

1 C1155 1 C241 1 C240 1 C219 1 C195 1 C192 1 C178 1 C1156 1 C1154 1 C255 1 C260
2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V

1 C1157 1 C1201 1 C239 1 C223 1 C194 1 C191 1 C258 1 C257

2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V

1 C1159 1 C1199 1 C237 1 C222 1 C196 1 C179 1 C6031 1 C6033 1 C6036

2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V 2 100PF_50V 2 100PF_50V 2 100PF_50V

1 C256 1 C251 1 C238 1 C224 1 C6032 1 C6034 1 C6035 1 C6037

2 100PF_50V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V 2 100PF_50V 2 100PF_50V 2 100PF_50V 2 100PF_50V Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
DDR-SDRAM-4
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 28 of 67
EE2 Thursday, July 31, 2003 10:54:46 am A02 PC8803

 USED M9+X R184 , R181 OPEN
USED M10 R184 , R181, R177, R188 PULL UP 10K +V3S

U11
AGP_AD(0) H29 AJ5 1 R181 2
AD0 GPIO0 VGA_GPIO(0) VGA_GPIO(0)
AGP_AD(1) H28 AH5 29-
AD1 GPIO1 VGA_GPIO(1) 10K_1%
21- AGP_AD(2) J29 AJ4 29-
AGP_AD(31:0) AD2 GPIO2 VGA_GPIO(2)
AGP_AD(3) J28 AK4
AD3 GPIO3 VGA_GPIO(3) R184
AGP_AD(4) K29 AH4 TP559 29- 1 2
AD4 GPIO4 VGA_GPIO(1)
AGP_AD(5) K28 AF4
AGP_AD(6) AD5 GPIO5 10K_1%
L29 AD6 GPIO6 AJ3 TP561
AGP_AD(7) L28 AK3 TP562
AGP_AD(8) AD7 GPIO7 R177
N28 AH3 R1287 1 2 1K_1% VGA_GPIO(2) 29- 1 2
AGP_AD(9) AD8 GPIO8
P29 AD9 GPIO9 AJ2 TP563
10K_1%
AGP_AD(10) P28 AH2
AGP_AD(11) AD10 GPIO10
R29 AH1 TP566
AGP_AD(12) AD11 GPIO11 R188
R28 AD12 GPIO12 AG3 VGA_GPIO(3) 1 2
AGP_AD(13) T29 AG1 TP568
AGP_AD(14) AD13 GPIO13 10K_1%
T28 AG2
AGP_AD(15) AD14 GPIO14
U29 AD15 GPIO15 AF3 9-
PWRPLAY
AGP_AD(16) N25 AF2 30-
AD16 GPIO16 GPIO16
AGP_AD(17) R26

PCI / AGP
AD17

DVO / EXT TMDS / GPIO

AGP_AD(18) P25
AGP_AD(19) AD18
R27 AD19 DVOMODE AE10
AGP_AD(20) R25
AGP_AD(21) AD20
T25 AD21 ZV_LCDDATA0 AH6 36- LCM_ID0
AGP_AD(22) T26 AJ6 36- LCM_ID1
AGP_AD(23) AD22 ZV_LCDDATA1
U25 AD23 ZV_LCDDATA2 AK6 36- LCM_ID2
AGP_AD(24) V27 AH7 36- LCM_ID3
AGP_AD(25) AD24 ZV_LCDDATA3
W26 AK7 36- LCM_ID4
AGP_AD(26) AD25 ZV_LCDDATA4
W25 AD26 ZV_LCDDATA5 AJ7 R186 1 2 1K_1%
AGP_AD(27) Y26 AH8 R183 1 2 1K_1%
AGP_AD(28) AD27 ZV_LCDDATA6
Y25 AJ8 R182 1 2 1K_1%
AGP_AD(29) AD28 ZV_LCDDATA7
AA26 AD29 ZV_LCDDATA8 AH9 R189 1 2 1K_1%
AGP_AD(30) AA25 AJ9 R187 1 2 1K_1%
AGP_AD(31) AD30 ZV_LCDDATA9
AA27 AK9 R185 1 2 1K_1%
AD31 ZV_LCDDATA10
ZV_LCDDATA11 AH10 R194 1 2 1K_1% +V3S
AGP_CBE#(3:0) 21-
ZV_LCDDATA12 AE6 R1262 1 2 1K_1%
AGP_CBE#(0) N29 AG6 R1286 1 2 1K_1%
AGP_CBE#(1) C_BE#0 ZV_LCDDATA13
U28 C_BE#1 ZV_LCDDATA14 AF6 R1285 1 2 1K_1% 1
AGP_CBE#(2) P26 C_BE#2 AE7 R1263 1 2 1K_1%
AGP_CBE#(3) ZV_LCDDATA15 R1275
U26 AF7 R1270 1 2 10K_5%
C_BE#3 ZV_LCDDATA16 10K_5%
ZV_LCDDATA17 AE8 R1269 1 2 10K_5%
CLK_AGPCONN 15- AG30 PCICLK ZV_LCDDATA18 AG8 R1271 1 2 1K_1% 2
PCI_RESET1#_3 55-,48-,37-,21- AG28 RST# ZV_LCDDATA19 AF8 R1265 1 2 1K_1%
AGP_REQ# 21- AF28 REQ# ZV_LCDDATA20 AE9 LCDDATA20
21- AD26 GNT# AF9 1 OPEN 2 R1274
AGP_GNT# ZV_LCDDATA21
21- M25 PAR AG10 1 OPEN 2 R190
AGP_PAR ZV_LCDDATA22
AGP_STOP# 21- R1179 1 2 10_5% AGP_STOP#_R N26 STOP# AF10 1 OPEN 2 R1273
10_5% AGP_DEVSEL#_R ZV_LCDDATA23
AGP_DEVSEL# 21- R1184 1 2 V29 +V3S
10_5% AGP_TRDY#_R DEVSEL# 1 1 1
AGP_TRDY# 21- R1182 1 2 V28 TRDY#
AGP_IRDY# 21- R1183 1 2 10_5% AGP_IRDY#_R W29 IRDY# AJ10 R193 1 2 1K_5%
10_5% AGP_FRAME#_R ZV_LCDCNTL0 R1268 R1267 R1272
AGP_FRAME# 21- R1185 1 2 W28 AK10 R195 1 2 1K_5%
FRAME# ZV_LCDCNTL1 OPEN OPEN OPEN 1
PIRQA#_3 37- AE26 INTA# ZV_LCDCNTL2 AJ11 R196 1 2 1K_5% 2 2 2
AH11 R1266 1 2 1K_5% R1277
10_5% AGP_WBF#_R ZV_LCDCNTL3 3K_5%
AGP_WBF# 21- R1188 1 2 AC26
WBF#
10_5% AGP_REF#_R VREFG AG4 2
AGP_RBF# 21- R1189 1 2 AE29 RBF#
AGP_ADSTB0 21- R1178 1 2 10_5% AGP_ADSTB0_R M28
10_5%AGP_ADSTB1_R AD_STBF_0
AGP_ADSTB1 21- R1180 1 2 V25 AD_STBF_1 TXOUT_L0N AK16 36- TXOUTL0-
AGP_SBSTB 21- R1187 1 2 10_5%AGP_SBSTB_R AB29 SB_STBF AH16 36- TXOUTL0+
TXOUT_L0P 1
AH17 36- TXOUTL1-
AGP_SBA(0)
AGP2X TXOUT_L1N R191
AD28 SBA0 TXOUT_L1P AJ16 36- TXOUTL1+
21- AGP_SBA(1) AD29 AH18 36- 3K_5%
AGP_SBA(7:0) SBA1 TXOUT_L2N TXOUTL2-
AGP_SBA(2) AC28 AJ17 36-
SBA2 TXOUT_L2P TXOUTL2+ 2
AGP_SBA(3) AC29 AK19 TP14
AGP_SBA(4) SBA3 TXOUT_L3N
AA28 SBA4 TXOUT_L3P AH19

LVDS
AGP_SBA(5) AA29 AK18 36-
SBA5 TXCLK_LN TXCLKOUTL-
AGP_SBA(6) Y28 AJ18 36- TXCLKOUTL+
AGP_SBA(7) SBA6 TXCLK_LP M9+X R1277, R191OPEN
Y29 AG16 36- TXOUTU0-
SBA7 TXOUT_U0N M10 R1277, R191 USED 3K OHM
TXOUT_U0P AF16 36- TXOUTU0+
AGP_ST0 21- AF29 ST0 TXOUT_U1N AG17 36- TXOUTU1-
AGP_ST1 21- AD27 AF17 36- TXOUTU1+
ST1 TXOUT_U1P
AGP_ST2 21- AE28 ST2 TXOUT_U2N AF18 36- TXOUTU2-
TXOUT_U2P AE18 36- TXOUTU2+
AH20
10_5%AGP_SBSTB#_R TXOUT_U3N
AGPREF AGP_SBSTB# 21- R1186 1 2 AB28 SB_STBS TXOUT_U3P AG20
21- R1177 1 2 10_5%AGP_ADSTB0#_R M29 ADSTBS_0 AF19 36- TXCLKOUTU-
AGP_ADSTB0#
10_5%AGP_ADSTB1#_R TXCLK_UN
21- R1181 1 2 V26 AG19 36- TXCLKOUTU+
ADSTBS_1 TXCLK_UP
4X

AGP_ADSTB1#
M26 AGPREF
AGP

C1232 1 +V1.5ATIAGP R1198 47_5% M27

1 C1208 AGPTEST
DIGON AE12
1 2 36- DIGON
2 2 10UF_K_6.3V R1200 20K_5% AB26 DBI_LO BLON AG12 36- BLON#
R1222 1 2 20K_5% AB25 DBI_HI
8X

0.1UF_16V
R1199 1 2 20K_5% AC25 AGP8X_DET#
+V3S 1 2

ATI_M9_M10_BGA_748P
LAYOUT NOTE : C1255 , C3 CLOSE TO M9+X USED M9+X R1198 49.9 OHM
USED M10 R1198 47 OHM Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
ATI-M10-P-1
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 29 of 67
EE2 Thursday, July 31, 2003 10:54:52 am A02 PC8803

 LAYOUT NOTES : R1359, R1361, R1360, R1362 CLOSE TO M9+X

R192
U11 1 R1227 2 1 R1226 2
1 2 AK21 R2SET TX0M AJ13 330_5% 330_5% 57- TX0M
715_1% TX0P AH14 57- TX0P
57-,35- AJ23 C_R TX1M AJ14 57- TX1M
CHROMA_C57-,35- AJ22 Y_G AH15 57-
LUMA_Y TX1P TX1P
AK22 AJ15

TMDS
57- 57-

DAC2
COMP_B COMP_B TX2M TX2M
TX2P AK15 57- TX2P
AJ24 H2SYNC TXCM AH13 57- TXCM
TP19 AK24 AK13 57- TXCP
V2SYNC TXCP 1 R1276 2 1 R1225 2
LCM_DDCCLK 36- AG23 DDC3CLK DDC2CLK AE13 330_5% 330_5% 57- DVIDDCCLK
LCM_DDCDATA 36- AG24 AE14 57- DVIDDCDATA
DDC3DATA DDC2DATA
HPD1 AF12 57- HPD
R6026 75_1%
M9+X USED R1203 120 OHM , R1202 100 OHM 1 2

27MHZ 30-
M10 USED R1203 200 OHM , R1202 120 OHM R AK27 57- R R6027 75_1%
+V3S TP20 AK25 AJ27 57- 1 2

SS
SSIN G G
AJ25 SSOUT B AJ26 57- B
X1000 1 2
4 3 1 R1203 2 R211 1 2 0_5% AH28 AG25 35-
VDD OUT XTALIN HSYNC HSYNC R6028 75_1%
200_5% R210 1 2 OPEN AJ29 XTALOUT CLK VSYNC AH25 35- VSYNC

DAC1
1 C1240 1 OE
1
GND 2 C1239
1 R209 2
2 0.1UF_16V AH27 TESTEN RSET AH26
1
27MHZ 2 R1202 E8 499_1%
120_5% TEST_YCLK
15PF B6 AF25 35- DDCDATA
2 R1201 TEST_MCLK DDC1DATA
AE25 PLLTEST DDC1CLK AF24 35- DDCCLK
PWR_GOOD_3 59-,40-,14-,11- 1 1K_5% 2 +V3S
AF261 R208 2 1 R1318 2
AUXWIN
SUS_STAT#_3 59-,42-,40-,38- AG26 SUS_STAT# 10K_5% 10K_5%
38- AH30 1 R1319 2

MAN
PWR
C3_STAT# STP_AGP#
AGPBUSY#_3 38- AH29 AF11 20- DPLUS 10K_5%
R1190 AGP_BUSY# DPLUS
AG29 DMINUS AE11 20-
1 1K_5% 2
RSTB_MSK THERM DMINUS

+V3S
20K_5%
2 1
ATI_M9_M10_BGA_748P +V3S

R1436

+V3S
OPEN
2 1

R64

+V3S

1 L1015 2 C1326 0.1UF_16V

BLM21A121S 1 2
+V1.5ATIAGP
FOR EMI

+V3S C1325 2 R1290 1 (20/5)

10K_5%
1
1
1 10UF_10V_METAL R1197
R164 1K_1%
U10 AGPREF
OPEN 2
2 3
0_5% 1 R163 2 2 VDD GND (20/5)
7 S0 SSCC 5
6 S1 XIN_CLK 1 1 R1288 2 30- 27MHZ
8 4 33_5%
XOVT SSCLK 1
29- GPIO16 R1176
CYS_IMISM560BZT_SOIC_8P 1K_1%
+V3S
2
OPEN
1

R162
10K_5%
10K_5% 1 R161 2 2

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
ATI-M10-P-2
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 30 of 67
EE2 Thursday, August 21, 2003 11:32:01 am A02 PC8803

 GMAB(13:0) L25
U11
E22
GMDB(63:0)
33- U11 31-
L26
K25
DQA0
DQA1
MAA0
MAA1 B22
GMDB(0) D7 GMAB(0)
GMDB(1) DQB0 MAB0 N5 GMAB(1) K26 DQA2 MAA2 B23
F7 M1 B24
GMDB(2) DQB1 MAB1 GMAB(2) J26 DQA3 MAA3
E7 DQB2 MAB2 M3 DQA4 MAA4 C23
GMDB(3) G6 GMAB(3) H25
GMDB(4) DQB3 MAB3 L3 GMAB(4) H26 DQA5 MAA5 C22
G5 L2 F22
GMDB(5) DQB4 MAB4 GMAB(5) G26 DQA6 MAA6
F5 DQB5 MAB5 M2 DQA7 MAA7 F21
GMDB(6) E5 GMAB(6) G30
GMDB(7) DQB6 MAB6 M5 GMAB(7) D29 DQA8 MAA8 C21
C4 P6 A24
GMDB(8) DQB7 MAB7 GMAB(8) D28 DQA9 MAA9
B5 DQB8 MAB8 N3 DQA10 MAA10 C24
GMDB(9) C5 GMAB(9) E28
GMDB(10) DQB9 MAB9 K2 GMAB(10) E29 DQA11 MAA11 A25
A4 DQB10 MAB10 K3 DQA12 MAA12 E21
GMDB(11) B4 GMAB(11) G29
GMDB(12) DQB11 MAB11 J2 GMAB(12) G28 DQA13 MAA13 B20
C2 P5 C19
GMDB(13) DQB12 MAB12 GMAB(13) F28 DQA14 MAA14
D3 DQB13 MAB13 P3 DQA15
GMDB(14) D1 G25
GMDB(15) DQB14 MAB14 P2 TP25
DQA16
D2 F26 J25
GMDB(16) DQB15 DQA17 DQMA#0
G4 DQB16 E26 DQA18 DQMA#1 F29
GMDB(17) H6
GMDB(18) DQB17 DQMB#0 E6 34- GDQMB(0) F25 DQA19 DQMA#2 E25

MEMORY INTERFACE A
H5 B2 34- GDQMB(1) E24 A27
GMDB(19) DQB18 DQMB#1 DQA20 DQMA#3
J6 DQB19 DQMB#2 J5 34- GDQMB(2) F23 DQA21 DQMA#4 F15
GMDB(20) K5 DQB20 DQMB#3 G3 34- GDQMB(3) E23 DQA22 DQMA#5 C15

MEMORY INTERFACE B
GMDB(21) K4 W6 34- GDQMB(4) D22 C11
GMDB(22) DQB21 DQMB#4 DQA23 DQMA#6
L6 DQB22 DQMB#5 W2 34- GDQMB(5) B29 DQA24 DQMA#7 E11
GMDB(23) L5
GMDB(24) DQB23 DQMB#6 AC6 34- GDQMB(6) C29 DQA25
G2 AD2 34- GDQMB(7) C25
GMDB(25) DQB24 DQMB#7 DQA26
F3 DQB25 C27 DQA27 QSA0 J27
GMDB(26) H2 B28 F30
GMDB(27) DQB26 DQA28 QSA1
E2 F6 34- QSB0 B25 F24
GMDB(28) DQB27 QSB0 DQA29 QSA2
F2 DQB28 QSB1 B3 34- QSB1 C26 DQA30 QSA3 B27
GMDB(29) J3 K6 34- B26 E16
DQB29 QSB2 QSB2 DQA31 QSA4
GMDB(30) F1 G1 34- F17 B16
DQB30 QSB3 QSB3 DQA32 QSA5
GMDB(31) H3 V5 34- E17 B11
DQB31 QSB4 QSB4 DQA33 QSA6
GMDB(32) U6 W1 34- D16 F10
DQB32 QSB5 QSB5 DQA34 QSA7
GMDB(33) U5 AC5 F16
GMDB(34) U3
DQB33
DQB34
QSB6
QSB7 AD1
34-
34-
QSB6
QSB7 E15
DQA35
DQA36 RASA# A19
Layout Note:
GMDB(35) V6 F14
GMDB(36)
GMDB(37)
W5
DQB35
DQB36 RASB# R2 31- DDR_RASB# E14
DQA37
DQA38 CASA# E18
CLOSE TO ATI
W4 DQB37 F13 DQA39
GMDB(38) Y6 T5 31- DDR_CASB# C17 E19
GMDB(39) DQB38 CASB# DQA40 WEA# USED ELPIDA MEMORY R1253 & R1256 CHANGE TO 732 OHM
Y5 DQB39 B18 DQA41
GMDB(40) U2
GMDB(41) DQB40 WEB# T6 31- DDR_WEB# B17 DQA42 CSA0# E20
V2 B15
GMDB(42) DQB41 DQA43
V1 DQB42 CSB0# R5 31- DDR_CSB0# C13 DQA44 CSA1# F20
GMDB(43) V3 B14
GMDB(44) DQB43 DQA45
W3 R6 31- DDR_CSB1# C14 B19
GMDB(45) DQB44 CSB1# DQA46 CKEA
Y2 DQB45 C16 DQA47 +VRAM_VCC
GMDB(46) Y3 R3 31- DDR_CKEB A13
GMDB(47) DQB46 CKEB DQA48
AA2 DQB47 A12 DQA49 CLKA0 B21 TP66
GMDB(48) AA6 N1 C12
GMDB(49) DQB48 CLKB0 31- DDR_CLKB0 DQA50 CLKA0# C20 TP67
1
AA5 DQB49 CLKB0# N2 31- DDR_CLKB0# LAYOUT NOTES: B12 DQA51
GMDB(50) AB6 C10 R1255
GMDB(51) DQB50 R237, R238 CLOSE TO U2163 DQA52 CLKA1 C18 TP68
1K_1%
AB5 DQB51 CLKB1 T2 31- DDR_CLKB1 ONLY ELPIDA MEMORY TO INSTALL C9 DQA53 CLKA1# A18 TP69
GMDB(52) AD6 T3 31- DDR_CLKB1# B9
GMDB(53) DQB52 CLKB1# B10 DQA54 2
AD5 DQB53 DQA55
GMDB(54) AE5 R1281 0_5%
DIMB_0 E3 E13 MVREFD B7
1 2 34-
DQB54 R1284 0_5% DIMB_0 DQA56
GMDB(55) AE4 AA3 1 2 34- DIMB_1 E12
GMDB(56) DQB55 DIMB_1 R1258 OPEN DQA57
AB2 DQB56
1 2 +V1.8S E10 DQA58 MVREFS B8 1
GMDB(57) AB3
GMDB(58) DQB57 ROMCS# AF5 TP28 F12 DQA59 R1253 1 C1298 1 C1301
AC2 F11
GMDB(59) DQB58 R1257 2 4.7K_5% DQA60 1K_1%
AC3 DQB59 MEMVMODE_0 C6 1 E9 DQA61 DIMA_0 D30 TP70 2 0.1UF_16V2 10UF_K_6.3V
GMDB(60) AD3 C7 F9
GMDB(61) DQB60 MEMVMODE_1 DQA62 DIMA_1 B13 TP71
2
AE1 +V1.8S F8
GMDB(62) DQB61 DQA63
AE2 DQB62 MEMTEST C8
GMDB(63) AE3 DQB63 1

R1259
R1261 1 2 OPEN
1 ATI_M9_M10_BGA_748P
R1260
ATI_M9_M10_BGA_748P 2
47_5% 4.7K_5%
2 LAYOUT NOTES : R176 R175 CLOSE TO ATI +VRAM_VCC

31- 1 2 34-
DDR_CLKB1# DDR_CLKB1#_R 1
RS3 10 R175 10_5%
31- 8 9 34- R1254
GMAB(11) GMAB_R(11) 1K_1%
31- 7 10 34- IF USED ELPIDA MEMORY R134 R135 ADD 4.7K 31- 1 2 34-
GMAB(10) GMAB_R(10) DDR_CLKB1 DDR_CLKB1_R
GMAB(9) 31- 6 11 34- GMAB_R(9) R176 10_5% R145 R144 2
GMAB(3) 31- 5 12 34- GMAB_R(3) THEN R145 R1370 OPEN 1 2 1 2

GMAB(4) 31- 4 13 34- GMAB_R(4) 56_5% 56_5% Layout Note:

GMAB(2) 31- 1 16 34- GMAB_R(2)
31- 3 14 34- 1 C125 CLOSE TO MEMORY
GMAB(5) GMAB_R(5) 1
GMAB(1) 31- 2 15 34- GMAB_R(1) 2 470PF_50V R1256 1 C1300 1 C1299
1K_1% 2 0.1UF_16V2 10UF_K_6.3V
2
31- R173 1 2 10_5% 34-
GMAB(0) GMAB_R(0)
31- 1 210_5% 34-
GMAB(6) R1585 GMAB_R(6)
Layout note: LAYOUT NOTES : R171 R172 CLOSE TO ATI C120 , C125 USED M9+X 0.01UF , M10 470PF
RS1033 10
place these componts 31- 4 13 34- 31- 1 2 34-
GMAB(8) GMAB_R(8) DDR_CLKB0# DDR_CLKB0#_R PLEASE OPEN ON M9+X
GMAB(13) 31- 5 12 34- GMAB_R(13) R172 10_5%
near the ATI 31- 2 15 34-
GMAB(12) GMAB_R(12)
31- 1 16 34- 31- 1 34-
DDR_CSB1# DDR_CSB1#_R DDR_CLKB0 DDR_CLKB0_R
GMAB(7) 31- 3 14 34- GMAB_R(7) R171 210_5%
31- 6 11 34- 1 R143 2 1 R142 2
DDR_CSB0# DDR_CSB0#_R Engineer
DDR_RASB#
DDR_CASB#
31-
31-
7
8
10
9
34-
34-
DDR_RASB#_R
DDR_CASB#_R
56_5%
1 C120
56_5%
Layout Note:
David Du
Drawn by
David Du
INVENTEC
2 470PF_50V CLOSE TO MEMORY R&D CHK Size
31- 1 210_5% 34- TITLE
DDR_WEB#
31-
R1283
1 210_5% 34-
DDR_WEB#_R A3
DDR_CKEB R174 DDR_CKEB_R DOC CTRL CHK

MFG ENGR CHK

DIAMOND
ATI-M10-P-3
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 31 of 67
EE2 Thursday, July 31, 2003 10:55:09 am A02 PC8803

 +VRAM_VCC VDD_MEM2.5
L11 R1282,R1221 USED M9+X IS OPEN , USED M10 CHANGE TO 0 OHM USED M9+X PLEASE OPEN THIS SYMBOL
1 2
NFM41P11C204 U11 U11
4 3 P17 VDDC VSS M16
T7 VDDR1 VDDC AC13 +VGAVCC P18 VDDC VSS N16
1 R1282 2 R4 AD13 P19 N15
1 C1252 1 C1302 VDDR1 VDDC VDDC VSS
C168 0_5% R1 VDDR1 VDDC AD15 U12 VDDC VSS P15
2 0.01UF_16V 2 1000PF_0402 N8 VDDR1 VDDC AC15 U13 VDDC VSS P16
1 1 C1309 N7 AC17 U14 R18
VDDR1 VDDC +V1.5S VDDC VSS
22UF_6.3V 2 0.1UF_16V M4 VDDR1 U17 VDDC VSS R17
L27 VDDR1 VDD15 P8 1 L1013 2 U18 VDDC VSS R16

M10 CENTER ARRAY

L8 VDDR1 VDD15 Y8 BLM21A121S +V1.8S U19 VDDC VSS R15
J24 VDDR1 VDD15 AC11 V19 VDDC VSS R14
J23 VDDR1 VDD15 AC20 1 C1259 1 C1258 1 L1009 2 NOTES: USED+V1.8S FOR M9+X INSTALL L1009 OPEN L1013 V18 VDDC VSS R13
J8 VDDR1 VDD15 Y23 2 0.01UF_16V 2 10UF_K_6.3V OPEN NOTES: USED+V1.5S FOR M10 INSTALL L1013 OPEN L1009 V17 VDDC VSS R12
1 C1303 1 C1254 J7 L23 V14 T13
VDDR1 VDD15 VDDC VSS
2 0.01UF_16V 2 1000PF_0402 J4 VDDR1 VDD15 H20 V13 VDDC VSS T14
1 C1230 1 C1308 J1 H11 +AGP_V3S Q6006 +V3S V12 T15
VDDR1 VDD15 VDDC VSS
2 0.1UF_16V 2 0.1UF_16V H10 VDDR1 N18 VDDC VSS W15
H13 AD7 4 S D 1 N17 V16
VDDR1 VDDR3 2 VDDC VSS
H15 VDDR1 VDDR3 AD19 N14 VDDC VSS V15
H17 AD21 C1324 5 W17 U15
VDDR1 VDDR3 1 C1275 1 C1322 1 3 6 VDDC VSS
T8 VDDR1 VDDR3 AD22 G W18 VDDC VSS U16
V4 VDDR1 VDDR3 AC22 2 0.01UF_16V 2 0.01UF_16V 22UF_6.3V W12 VDDC VSS T19
C167 1 C1229 1 C1228 V7 AC21 FDC638P W13 T18
1 1 C1256 VDDR1 VDDR3 VDDC VSS
2 0.01UF_16V 2 1000PF_0402 V8 VDDR1 VDDR3 AC19 49-,13- SLP_S3_5R W14 VDDC VSS T17
22UF_6.3V 2 0.1UF_16V AA1 VDDR1 VDDR3 AC8 N13 VDDC VSS T16
AA4 VDDR1 N19 VDDC
AA7 VDDR1 VDDR4 AG7 M19 VDDC
+V1.8S AA8 AD9 1 C1310 1 C1311 1 C1276 1 C1271 1 C1321 1 C1323 M18
VDDR1 VDDR4 VDDC
USED M9+X OPEN L18 , USED M10 OPEN L1005 A3 VDDR1 VDDR4 AC9 2 0.01UF_16V 2 0.01UF_16V 2 0.01UF_16V 2 0.01UF_16V 2 0.01UF_16V 2 0.01UF_16V M12 VDDC
INSTALL L1005 VDD_PNLIO2.5 INSTALL L18 A9 VDDR1 VDDR4 AC10 N12 VDDC
A15 VDDR1 VDDR4 AD10 M13 VDDC
1 L1005 2 A21 VDDR1 M14 VDDC
+V2.5S OPEN A28 VDDR1 VDDP J30 P12 VDDC VDDC1 W16
1 C1238 1 C1236 B1 AF27 P13
VDDR1 VDDP VDDC VDDC1 M15
L18 2 10UF_K_6.3V 2 0.01UF_16V B30 VDDR1 VDDP AE30 +V1.5ATIAGP +V1.5S P14 VDDC VDDC1 R19
1 2 D26 AC27 L1003 M17
VDDR1 VDDP VDDC VDDC1 T12
D23 AC23 1 2 W19
BLM21A121S VDDR1 VDDP VDDC

I / O POWER
VDD_PNLIO1.8 D20 VDDR1 VDDP AB30 NFM41P11C204
D17 AA24 C1207 C1209 4 3
+V1.8S
1 L1012 2
D14
D11
VDDR1
VDDR1
VDDP
VDDP AA23
Y27
1 C1267 1 C1233 1 C1231 1 C1270 1 1 ATI_M9_M10_BGA_748P
VDDR1 VDDP 2 1000PF_04022 0.01UF_16V 2 0.01UF_16V 2 0.1UF_16V 22UF_6.3V 22UF_6.3V
D8 W30
BLM11A121S 1 C1278 1 C1277 D5
VDDR1
VDDR1
VDDP
VDDP V23 U11
2 0.1UF_16V 2 0.01UF_16V E27 VDDR1 VDDP V24 A2 VSS VSS K8
F4 VDDR1 VDDP M23 A10 VSS VSS K7
+V1.8S VDD_PNLPLL1.8 G7 M24 A16 K1
VDDR1 VDDP VSS VSS
G10 VDDR1 VDDP N30 A22 VSS VSS L4
1 L1011 2 BLM11A121S G13 VDDR1 VDDP P23 A29 VSS VSS M30
G15 P27 1000PF_0402 C1 M8
1 C1281 1 C1280 VDDR1 VDDP C1304 VSS VSS
G19 VDDR1 VDDP T23 C3 VSS VSS M7
1 C1266 1 C1272 1 C1263
2

2 0.01UF_16V G22 T24 1 C28 N23

D6008 2 VDDR1 VDDP VSS VSS
10UF_K_6.3V G27 VDDR1 VDDP T30 22UF_6.3V 2 0.1UF_16V 2 1000PF_04022 C30 VSS VSS N24
H22 VDDR1 VDDP U27 D27 VSS VSS N27
3

H19 VDDR1 D24 VSS VSS P4

BAT54C_OPEN AD4 VDDR1 AD24 D21 VSS VSS R7
AVSSQ
T4 VDDR1 D18 VSS VSS R8
1

USED M9+X OPEN L1011 , USED M10 OPEN D6008 N4 D15 R23
INSTALL D6008 , INSTALL L1011 R1221 D19 VDDR1 VSS VSS
1 2
VDDR1 LVSSR AF20 D12 VSS VSS R24
+VRAM_VCC 0_5% D13 VDDR1 LVSSR AE19 D9 VSS VSS R30
AE16 1000PF_0402 D6 T27
LVSSR VSS VSS
1 L1008 2 LVSSR AF15 D4 VSS VSS T1

CORE GND
C1268 F27 U4
BLM11A121S 1 1 C1273 1 C1262 1 C1274 VSS VSS
G9 VSS VSS U8
1 C1255 1 C1305 1 C1257 AJ19 G12 U23
LPVSS 2 0.1UF_16V 2 0.01UF_16V 2 VSS VSS
2 2 0.01UF_16V 2 0.01UF_16V AE17 LVDDR_25 TPVSS AJ12 G16 VSS VSS V30
10UF_K_6.3V AE20 LVDDR_25 68UF_4V_METAL G18 VSS VSS W7
AE15 LVDDR_18 G21 VSS VSS W8
AF21 LVDDR_18 TXVSSR AH12 G24 VSS VSS W23
TXVSSR AG13 H27 VSS VSS W24
VDD_DAC2.5 AJ20 LPVDD TXVSSR AG14 H23 VSS VSS W27
+V2.5S 1 L16 2 AK12 TPVDD H21 VSS VSS Y4
L1010
USED M10 PLEASE OPEN THIS SYMBOL H18 AA30
BLM11A121S 1 C174 1 C1279 1 2 NFM41P11C204 1000PF_0402 VSS VSS
AF13 TXVDDR VSSRH0 F19 H16 VSS VSS AB27
AF14 TXVDDR VSSRH1 M6 H14 AB24
2
10UF_K_6.3V
2 0.01UF_16V
U11 4 3 1 C1306 1 C1265 1 C1264 H12
VSS
VSS
VSS
VSS AB23
F18 VDDRH0 J10 VDDC 2 0.1UF_16V 2 0.01UF_16V 2 H9 VSS VSS AB8
N6 VDDRH1 A2VSSN AH22 J12 VDDC H8 VSS VSS AB7
+V1.8S L17 VDD_DAC1.8 A2VSSN AJ21 J14 VDDC H4 VSS VSS AB1
1 2 AG21 A2VDD J15 VDDC K30 VSS VSS AC4
BLM11A121S AH21 A2VDD J16 VDDC K27 VSS VSS AC12
AF23 J17 VDDC K24 VSS VSS AC14
1 C190 1 C1234 A2VSSQ
AF22 A2VDDQ J19 K23 AD16

M9 INNER ROWS
VDDC VSS VSS
2 2 0.01UF_16V AVSSN AH23 J21 VDDC AG15 VSS VSS AC16
10UF_K_6.3V AH24 K9 VDDC C1260 1 C1307 AD12 VSS VSS AC18
AVDD 1 1 C1269 1 C1261
VSS1DI AE23 K22 VDDC AE27 VSS VSS AD30
AE24 VDD1DI M9 VDDC 22UF_6.3V2 0.1UF_16V 2 0.01UF_16V 2 AG5 VSS VSS AD25
L1004 AE22 AE21 M22 VDDC AG9 VSS VSS AD18
VDD_PLL1.8 VDD2DI VSS2DI
+V1.8S BLM11A121S P9 VDDC VSS J9 AG11 VSS VSS AK2
1 2 AK28 PVDD PVSS AJ28 P22 VDDC VSS J11 AG18 VSS VSS AK29
+V1.8S L1007 VDD_MEMPLL1.8 R9 VDDC VSS J13 AG22 VSS VSS AJ30
1 2 A7 MPVDD MPVSS A6 R22 VDDC VSS J18 1000PF_0402 AG27 VSS VSS AJ1
BLM11A121S T9 VDDC VSS J20 E4 VSS VSS D10
T22 VDDC VSS J22 AB4 VSS VSS D25
ATI_M9_M10_BGA_748P U9
U22
VDDC VSS L9
L22
V9
V22
VDDC
VDDC
VSS
VSS N9
N22
ATI_M9_M10_BGA_748P
VDDC VSS
Y9 VDDC VSS W9 Engineer
1 C1251 1 C1253 1 C1237 1 C1235
2 10UF_K_6.3V 2 0.01UF_16V 2 10UF_K_6.3V 2 0.01UF_16V
Y22
AB9
AB22
VDDC
VDDC
VDDC
VSS
VSS
VSS
W22
AA9
AA22
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
ATI_M9_M10_BGA_748P A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
ATI-M10-P-4
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 32 of 67
EE2 Thursday, August 14, 2003 8:32:25 pm A02 PC8803

 LAYOUT NOTES : THIS IS DEPEND RESISTOR NEED CLOSE TO VIDEO RAM

RS1037 RS1044
GMDB_R(1) 34- 2 7 31- GMDB(1) GMDB_R(32) 34- 4 5 31- GMDB(32)
GMDB_R(0) 34- 4 5 31- GMDB(0) GMDB_R(33) 34- 2 7 31- GMDB(33)
GMDB_R(2) 34- 3 6 31- GMDB(2) GMDB_R(34) 34- 3 6 31- GMDB(34)
GMDB_R(3) 34- 1 8 31- GMDB(3) GMDB_R(35) 34- 1 8 31- GMDB(35)
22 22
RS1038 RS1045
GMDB_R(5) 34- 3 6 31- GMDB(5) GMDB_R(36) 34- 4 5 31- GMDB(36)
GMDB_R(7) 34- 1 8 31- GMDB(7) GMDB_R(37) 34- 3 6 31- GMDB(37)
GMDB_R(4) 34- 4 5 31- GMDB(4) GMDB_R(38) 34- 2 7 31- GMDB(38)
GMDB_R(6) 34- 2 7 31- GMDB(6) GMDB_R(39) 34- 1 8 31- GMDB(39)
22 22

RS1047 RS1041
GMDB_R(10) 34- 1 8 31- GMDB(10) GMDB_R(42) 34- 1 8 31- GMDB(42)
GMDB_R(8) 34- 3 6 31- GMDB(8) GMDB_R(41) 34- 4 5 31- GMDB(41)
GMDB_R(11) 34- 2 7 31- GMDB(11) GMDB_R(40) 34- 3 6 31- GMDB(40)
GMDB_R(9) 34- 4 5 31- GMDB(9) GMDB_R(43) 34- 2 7 31- GMDB(43)
22 22
RS1034 RS1040
GMDB_R(12) 34- 4 5 31- GMDB(12) GMDB_R(46) 34- 2 7 31- GMDB(46)
GMDB_R(13) 34- 3 6 31- GMDB(13) GMDB_R(45) 34- 3 6 31- GMDB(45)
GMDB_R(14) 34- 2 7 31- GMDB(14) GMDB_R(44) 34- 4 5 31- GMDB(44)
GMDB_R(15) 34- 1 8 31- GMDB(15) GMDB_R(47) 34- 1 8 31- GMDB(47)
22 22

RS1039 RS1046
GMDB_R(16) 34- 4 5 31- GMDB(16) GMDB_R(49) 34- 3 6 31- GMDB(49)
GMDB_R(17) 34- 3 6 31- GMDB(17) GMDB_R(51) 34- 1 8 31- GMDB(51)
GMDB_R(18) 34- 2 7 31- GMDB(18) GMDB_R(50) 34- 2 7 31- GMDB(50)
GMDB_R(19) 34- 1 8 31- GMDB(19) GMDB_R(48) 34- 4 5 31- GMDB(48)
22 22
RS1048 RS1049
GMDB_R(21) 34- 4 5 31- GMDB(21) GMDB_R(53) 34- 4 5 31- GMDB(53)
GMDB_R(20) 34- 3 6 31- GMDB(20) GMDB_R(54) 34- 2 7 31- GMDB(54)
GMDB_R(23) 34- 1 8 31- GMDB(23) GMDB_R(52) 34- 3 6 31- GMDB(52)
GMDB_R(22) 34- 2 7 31- GMDB(22) GMDB_R(55) 34- 1 8 31- GMDB(55)
22 22

RS1043
RS1035 GMDB_R(63) 34- 1 8 31- GMDB(63)
GMDB_R(24) 34- 4 5 31- GMDB(24) GMDB_R(62) 34- 2 7 31- GMDB(62)
GMDB_R(25) 34- 3 6 31- GMDB(25) GMDB_R(61) 34- 3 6 31- GMDB(61)
GMDB_R(26) 34- 2 7 31- GMDB(26) GMDB_R(60) 34- 4 5 31- GMDB(60)
GMDB_R(27) 34- 1 8 31- GMDB(27)
22
22 RS1042
RS1036 GMDB_R(59) 34- 1 8 31- GMDB(59)
GMDB_R(28) 34- 4 5 31- GMDB(28) GMDB_R(57) 34- 3 6 31- GMDB(57)
GMDB_R(29) 34- 2 7 31- GMDB(29) GMDB_R(58) 34- 2 7 31- GMDB(58)
GMDB_R(30) 34- 3 6 31- GMDB(30) GMDB_R(56) 34- 4 5 31- GMDB(56)
GMDB_R(31) 34- 1 8 31- GMDB(31)
22
22

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
VGA DEPEND RESISTOR
Changed by Date Changed Time Changed QA CHK VER Model Number
EE2 Thursday, July 31, 2003 10:55:23 am A02 PC8803
Sheet 33 of 67

 GMAB_R(13:0)
31-,34- U1018 33- 31-,34- U1019 33-
GMAB_R(13:0) GMDB_R(63:32)
GMAB_R(12) N4 BA0 DQ31 B8 GMDB_R(31) GMAB_R(12) N4 BA0 DQ31 B8 GMDB_R(63)
M5 BA1 C9 GMDB_R(31:0) GMAB_R(13) M5 BA1 C9
GMAB_R(13) DQ30 GMDB_R(30) DQ30 GMDB_R(62)
DQ29 B9 GMDB_R(29) DQ29 B9 GMDB_R(61)
GMAB_R(11) M7 A11 DQ28 B10 GMDB_R(28) GMAB_R(11) M7 A11 DQ28 B10 GMDB_R(60)
GMAB_R(10) L6 A10 DQ27 C13 GMDB_R(27) GMAB_R(10) L6 A10 DQ27 C13 GMDB_R(59)
GMAB_R(9) M8 A9 DQ26 D12 GMDB_R(26) GMAB_R(9) M8 A9 DQ26 D12 GMDB_R(58)
GMAB_R(8) N11 A8_AP DQ25 D13 GMDB_R(25) GMAB_R(8) N11 A8_AP DQ25 D13 GMDB_R(57)
GMAB_R(7) N10 A7 DQ24 E13 GMDB_R(24) GMAB_R(7) N10 A7 DQ24 E13 GMDB_R(56)
GMAB_R(6) N9 A6 DQ23 K3 GMDB_R(23) GMAB_R(6) N9 A6 DQ23 K3 GMDB_R(55)
GMAB_R(5) M9 A5 DQ22 K2 GMDB_R(22) GMAB_R(5) M9 A5 DQ22 K2 GMDB_R(54)
GMAB_R(4) N8 A4 DQ21 J2 GMDB_R(21) GMAB_R(4) N8 A4 DQ21 J2 GMDB_R(53)
GMAB_R(3) N7 A3 DQ20 J3 GMDB_R(20) GMAB_R(3) N7 A3 DQ20 J3 GMDB_R(52)
GMAB_R(2) M6 A2 DQ19 G2 GMDB_R(19) GMAB_R(2) M6 A2 DQ19 G2 GMDB_R(51)
GMAB_R(1) N6 A1 DQ18 G3 GMDB_R(18) GMAB_R(1) N6 A1 DQ18 G3 GMDB_R(50)
GMAB_R(0) N5 A0 DQ17 F2 GMDB_R(17) GMAB_R(0) N5 A0 DQ17 F2 GMDB_R(49)
DQ16 F3 GMDB_R(16) DQ16 F3 GMDB_R(48)
C4 NC DQ15 F12 GMDB_R(15) C4 NC DQ15 F12 GMDB_R(47)
+VRAM_VCC C11 NC DQ14 F13 GMDB_R(14) +VRAM_VCC C11 NC DQ14 F13 GMDB_R(46)
H4 NC DQ13 G12 GMDB_R(13) H4 NC DQ13 G12 GMDB_R(45)
DIMB_0 DDR4/8
H11 NC DQ12 G13 GMDB_R(12) DIMB_1 DDR4/8
H11 NC DQ12 G13 GMDB_R(44)
1
31- L12 NC DQ11 J12 GMDB_R(11)
1
31- L12 NC DQ11 J12 GMDB_R(43)
PLACE CLOSE L13 NC DQ10 J13 GMDB_R(10) PLACE CLOSE L13 NC DQ10 J13 GMDB_R(42)
R1320 DDR_CSB1#_R M3 K12 GMDB_R(9) R1322 DDR_CSB1#_R M3 K12 GMDB_R(41)
TO THE MOMORY 1K_1% NC DQ9 TO THE MOMORY 1K_1% NC DQ9
31-,34- M4 NC DQ8 K13 GMDB_R(8) 31-,34- M4 NC DQ8 K13 GMDB_R(40)
2
N3 NC DQ7 E2 GMDB_R(7)
2
N3 NC DQ7 E2 GMDB_R(39)
DQ6 D2 GMDB_R(6) DQ6 D2 GMDB_R(38)
1
M13 MCL DQ5 D3 GMDB_R(5)
1
M13 MCL DQ5 D3 GMDB_R(37)
DQ4 C2 GMDB_R(4) DQ4 C2 GMDB_R(36)
1 C1343 R1321 1 C1342 N13 VREF B5 GMDB_R(3)
1 C1346 R1323 1 C1347 N13 VREF B5 GMDB_R(35)
1K_1% DQ3 1K_1% DQ3
2 2 0.1UF_16V DQ2 B6 GMDB_R(2)
2 2 0.1UF_16V DQ2 B6 GMDB_R(34)
10UF_K_6.3V 2 M10 RFU DQ1 C6 GMDB_R(1) 2 M10 RFU DQ1 C6 GMDB_R(33)
DQ0 B7 GMDB_R(0) DQ0 B7 GMDB_R(32)
L9 RFU L9 RFU
VDDQ C3 10UF_K_6.3V VDDQ C3
DDR_CLKB0#_R 31- M12 CLK# VDDQ C5 DDR_CLKB1#_R 31- M12 CLK# VDDQ C5 +V2.5S +V1.8S
VDDQ C7 VDDQ C7
DDR_CSB0#_R 31-,34- N2 CS# VDDQ C8 DDR_CSB0#_R 31-,34- N2 CS# VDDQ C8
VDDQ C10 VDDQ C10 +V1.8S FOR ELPIDA MEMORY
DDR_RASB#_R 31-,34- M2 RAS# VDDQ C12 +VRAM_VCC DDR_RASB#_R 31-,34- M2 RAS# VDDQ C12

POWERPAD_2

POWERPAD_2
VDDQ E3 VDDQ E3

PAD1001

PAD1002
DDR_CASB#_R 31-,34- L2 CAS# VDDQ E12 DDR_CASB#_R 31-,34- L2 CAS# VDDQ E12 +VRAM_VCC
VDDQ F4 VDDQ F4
DDR_WEB#_R 31-,34- L3 WE# VDDQ F11 DDR_WEB#_R 31-,34- L3 WE# VDDQ F11
VDDQ G4 VDDQ G4
GDQMB_R(3) 34- B12 DM3 VDDQ G11 GDQMB_R(7) 34- B12 DM3 VDDQ G11
VDDQ J4 VDDQ J4
GDQMB_R(2) 34- H3 DM2 VDDQ J11 GDQMB_R(6) 34- H3 DM2 VDDQ J11
K4 C146 0.1UF_16V C1349 K4 C151 0.1UF_16V
VDDQ 1 VDDQ
GDQMB_R(1) 34- H12 DM1 VDDQ K11 1 2 GDQMB_R(5) 34- H12 DM1 VDDQ K11 1 2
VDD D7 VDD D7 +V2.5S
34- B3 DM0 D8 C142 0.1UF_16V 34- B3 DM0 D8 C131 0.1UF_16V
GDQMB_R(0) VDD GDQMB_R(4) VDD
VDD E4 +V2.5S 1 2 VDD E4 1 2
31- M11 CLK E11 31- M11 CLK E11 1 C1348
DDR_CLKB0_R VDD C144 0.1UF_16V DDR_CLKB1_R VDD C152 0.1UF_16V
VDD L4 VDD L4 2 22UF_6.3V
31-,34- N12 CKE L7 1 2 47UF_6.3V_METAL 31-,34- N12 CKE L7 1 2
DDR_CKEB_R VDD DDR_CKEB_R VDD
VDD L8 VDD L8
L11 C140 0.1UF_16V L11 C147 0.1UF_16V
VDD VDD
QSB3_R 34- B13 DQS3 VSSQ B4 1 2 QSB7_R 34- B13 DQS3 VSSQ B4 1 2
VSSQ B11 VSSQ B11
H2 DQS2 D4 C139 0.1UF_16V H2 DQS2 D4 C148 0.1UF_16V
QSB2_R 34-
VSSQ PLACE IN QSB6_R 34-
VSSQ PLACE IN
R1295 22_5% VSSQ D5 1 2 VSSQ D5 1 2
MOMORY SECTION MOMORY SECTION
QSB1_R 34- H13 DQS1 VSSQ D6 QSB5_R 34- H13 DQS1 VSSQ D6
R1299 22_5% D9 C121 0.1UF_16V D9 C127 0.1UF_16V
VSSQ VSSQ
QSB0_R 34- B2 DQS0 VSSQ D10 1 2 QSB4_R 34- B2 DQS0 VSSQ D10 1 2
R1293 22_5% VSSQ D11 VSSQ D11
E6 C141 0.1UF_16V E6 C128 0.1UF_16V
R1296 22_5% VSSQ VSSQ
F6 TH_GND VSSQ E9 1 2 F6 TH_GND VSSQ E9 1 2
F7 TH_GND VSSQ F5 R1303 22_5% GDQMB(7) 31- 1 2 34- GDQMB_R(7) F7 TH_GND VSSQ F5
F8 F10 C145 0.1UF_16V F8 F10 C149 0.1UF_16V
TH_GND VSSQ C1344 TH_GND VSSQ
GDQMB(3) 31- 1 2 34- GDQMB_R(3) F9 TH_GND VSSQ G5 1 2 R1306 22_5% GDQMB(6) 31- 1 2 34- GDQMB_R(6) F9 TH_GND VSSQ G5 1 2
G6 G10 1 G6 G10 1 C1345
TH_GND VSSQ C124 0.1UF_16V TH_GND VSSQ C129 0.1UF_16V
GDQMB(2) 31- 1 2 34- GDQMB_R(2) G7 TH_GND VSSQ H5 2 R1300 22_5% GDQMB(5) 31- 1 2 34- GDQMB_R(5) G7 TH_GND VSSQ H5 2 22UF_6.3V
G8 TH_GND VSSQ H10 1 2 G8 TH_GND VSSQ H10 1 2
GDQMB(1) 31- 1 2 34- GDQMB_R(1) G9 TH_GND VSSQ J5 R1304 22_5% GDQMB(4) 31- 1 2 34- GDQMB_R(4) G9 TH_GND VSSQ J5
H6 J10 C122 0.1UF_16V H6 J10 C126 0.1UF_16V
TH_GND VSSQ TH_GND VSSQ
GDQMB(0) 31- 1 2 34- GDQMB_R(0) H7 TH_GND VSSQ K5 1 2 H7 TH_GND VSSQ K5 1 2
H8 K10 22UF_6.3V H8 K10
TH_GND VSSQ C143 0.1UF_16V TH_GND VSSQ C130 0.1UF_16V
H9 TH_GND VSS E5 H9 TH_GND VSS E5
J6 TH_GND VSS E7 1 2 J6 TH_GND VSS E7 1 2
J7 TH_GND VSS E8 J7 TH_GND VSS E8
J8 E10 C123 0.1UF_16V J8 E10 C150 0.1UF_16V
TH_GND VSS TH_GND VSS
R1294 22_5% J9 TH_GND VSS K6 1 2 J9 TH_GND VSS K6 1 2
VSS K7 VSS K7
R1298 22_5% VSS K8 VSS K8
VSS K9 VSS K9
R1292 22_5% VSS L5 VSS L5
VSS L10 R1302 22_5% QSB7 31- 1 2 34- QSB7_R VSS L10
R1297 22_5%
31- 1 2 34-
SAM_K4D263238A_GC40_FBGA_144P R1307 22_5% QSB6 QSB6_R SAM_K4D263238A_GC40_FBGA_144P
31- 1 2 34- 31- 1 2 34-
QSB3 QSB3_R R1301 22_5% QSB5 QSB5_R
34-
31- 1 2 31- 1 2 34-
QSB2 QSB2_R R1305 22_5% QSB4 QSB4_R Engineer

QSB1 31- 1 2

2
34-
QSB1_R
34-
David Du
Drawn by
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INVENTEC
31- 1
QSB0 QSB0_R R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
VIDEO RAM-2
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 34 of 67
EE2 Thursday, July 31, 2003 10:55:28 am A02 PC8803

 57- 1 R6037 2 0
R_CRT
USBVCC1
1 C6020
2 OPEN

1 C114 1 C115

2 0.1UF_16V2 10UF_10V

57- 1 R6038 2 0
G_CRT
CN5
1 C6022 1 1
2 2
2 OPEN
3 3
57- 4 4
DOCK_HSYNC 126_VCC 5 5
6 6
30- 1 1 7 7
HSYNC 8
R6039 2 0 1 R139 R140 8
57- 1 9 9
B_CRT R151 2.2K_5% 2.2K_5% 10 10
10K_5% 57- 11 11
1 C6021 DOCK_VSYNC 2 2 12
2 12 G 16
2 OPEN +V3 13 13 G 17
+V3S 14 14
15 15
VSYNC 30- U1017 126_VCC USBVCC1
1
3 VIDEO1 VCC1 2 SYN_7519S_15G2
8 TERM1 VCC2 12
R152 4 1 D2 1N4148
VIDEO2 VCC4
10K_5% 9 11 1 2
TERM2 PWRUP
5 VIDEO3 SD1 23 1 C113
2
10 TERM3 SYNC_OUT1 20 2 0.1UF_16V
19 SYNC_IN1 SD2 24
21 SYNC_IN2 SYNC_OUT2 22
30- 16 DDC_IN1 DDC_OUT1 15 57-
DDCDATA 30- DOCK_DDCDATA
DDCCLK 17 DDC_IN2 DDC_OUT2 18 57-
DOCK_DDCCLK
7 AGND VCC3 14
6 DGND VBIAS 13
CMD_VGA200_QSOP_24P
1 C1341 1 C119
2 2 0.1UF_16V
0.1UF_16V

CN6
1 GND
2
3 GND
4
Y G 5
C G 6
(10/5) (10/5) SIN_2MJ_1572_005
LUMA_Y 57-,30- 1 L10 2
LS_1MH_1.8U
+V3

1 SVIDEO CN
R155 BAV99 D1023
1

75_1%
1 C154 1 C153
2
3

2 82PF 2 82PF
2

(10/5) (10/5)
CHROMA_C 57-,30- 1 L12 2
LS_1MH_1.8U
+V3
BAV99 D1022

1
1

R167 1 C157 1 C156

75_1%
3

2 82PF 2 82PF
2 Engineer
David Du
INVENTEC
2

Drawn by
David Du
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
CRT& SVEDIO CONN
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 35 of 67
EE2 Friday, August 1, 2003 1:31:54 pm A02 PC8803

 +V3S +V3S

1
R1400
47K_5% (20/5) +V3S

2
1 R1401 2 4
G
7 1 C1416 1 C1400 Place as passible as close to connector
100_5% 6 2 10UF_K_6.3V 2 0.1UF_16V RS1055
1 C1399 3 29- 8 1
1
LCM_ID0 29- R1414
Q1049 5 S D 2 7 2
5 2 0.01UF_16V LCM_ID1 29- 0_5%
S1 8 1 6 3
1 LCM_ID2 29- 1 1
29- G1 5 4
DIGON 6 FDR840P Q1050 1 LCM_ID3 R1416 R14152 C1417 0.1UF_16V
D1 R1402 OPEN 4.7K_5%4.7K_5%
D2 4 100_5% R1417 2
1 2
3 G2 LCM_ID4 29- 1
2 2
2 OPEN CN2
S2 (20/5) 2
(20/5) 1
NDC7002N 1
2 2
3 3
4 4
5 5
6 6
7 7
30- 8 8
LCM_DDCCLK 9 9
30- 10 10
LCM_DDCDATA 11
TXOUTL0- 29- 11
29- 12 12
TXOUTL0+ 13
TXOUTL1- 29- 13
29- 14 14
TXOUTL1+ 15
TXOUTL2- 29- 15
29- 16 16
TXOUTL2+ 29- 17
TXCLKOUTL- 17
29- 18 18
TXCLKOUTL+ 19 19
20 20
29- 21 21
TXOUTU0- 22
TXOUTU0+ 29- 22
29- 23 23
TXOUTU1- 24
TXOUTU1+ 29- 24
29- 25 25
TXOUTU2- 26
TXOUTU2+
29- 26
29- 27 27
TXCLKOUTU- 28
TXCLKOUTU+
29- 28
+V3S +V5 29 29
C1396 30 30
1 100UF_10V 31 31
32 32
1 L1028 2 BLM41P800S
1
33 33
R1396 34 34
OPEN 35 35
INV_PWM_3
36 36
2
37 37 G 41
1 R1403 2 1 R1395 2 38 38 G 42
39 39
0_5% 100_5% 40
Q1051 3 40
D
29- 2G 1 C1397 1 C1395 1 C1401 IPEX_20265_040E
BLON#
S 2 0.1UF_16V 2 1000PF_04022 0.1UF_16V
2N7002_OPEN 1

USED M9+X OPEN R1403 , USED M10 OPEN R1396 , Q1051

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
LCD CONN
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 36 of 67
EE2 Thursday, July 31, 2003 10:55:39 am A02 PC8803

 +V3S +V3S
+V3A

R73 R1397 2 R54 +V3A

37- 1 2 1 49-,37- 54-,37- 1 2 +V5S
PIRQH#_3 IRQ15_3 MPCIREQ0#_3 R1429 2
37- 1
8.2K_5% 8.2K_5% 8.2K_5% ALERT_CLK_3
1 R92 2 1 R94 2 1 R56 2 POWER15/5 POWER15/5
2.2K_1%
REQ3#_3 37- 54-,37- PIRQF#_3 NICREQ1#_3 55-,37-
1 37- 1 R1431 2 1 C26
1 ALERT_DAT_3
1 R113 2
59-,51-,42-,40-,37- 1 R53 2 51-,37- 51-,37- 1 R59 2
2 0.1UF_16V
SERIRQ_3 PIRQG#_3 CBREQ2#_3 2.2K_1%
8.2K_5% 8.2K_5% 8.2K_5% R1418 R1427
10K_5% 10K_5% Q1053 5-,37- 1 R39 2
2 2N7002 STBY_SWIN#_3
1 R81 2 1 R72 2
POWER15/5

48-,37- 8.2K_5% 37-

IRQ14_3 REQ4#_3 10K_5%

G
2 2
8.2K_5% 8.2K_5% 1 R1421 2 3 126-,25-,20-,15-,37-

S
8.2K_5% 8.2K_5% ICH_SMCLK_3
33_5% 2 Q1055
U1037 2N7002

G
55-,51-,54- 1 R1428 2 3 1 26-,25-,20-,15-

S
PCI_AD(31:0) ICH_SMDAT_3
PCI_AD(0) H5 PCI_AD0 SM_INTRUDER# W6 37- INTRUDER#_3 33_5%
PCI_AD(1) J3 PCI_AD1 SMLINK0 AC3 37-
PCI_AD(2) H3
System AB1 ALERT_CLK_3
PCI_AD2 37-
PCI_AD(3) K1 Management SMLINK1 AC4 ALERT_DAT_3 +VCCP
PCI_AD3 SMB_CLK
PCI_AD(4) G5 PCI_AD4 I/F SMB_DATA AB4
PCI_AD(5) J4 PCI_AD5 AA5 5-,37-
PCI_AD(6)
SMB_ALERT#/GPIO11 STBY_SWIN#_3 1 POWER15/5

H4 PCI_AD6
PCI_AD(7) J5 PCI_AD7 CPU_A20GATE Y22 40- R1119
GTL4/8
A20GATE_3 56_5%
PCI_AD(8) K2 PCI_AD8 CPU_A20M# AB23 16-
H_A20M#
PCI_AD(9) G2 PCI_AD9 CPU_DPSLP# U23 21-,17- GTL4/8
H_DPSLP# R111 GTL4/8
2
PCI_AD(10) L1 PCI_AD10 CPU_FERR# AA21 1 2 16- GTL4/8 H_FERR_S#
PCI_AD(11) G4 PCI_AD11 CPU_IGNNE# W21 16- GTL4/8
H_IGNNE# 56_5% +V3S
PCI_AD(12) L2 PCI_AD12 CPU_INIT# V22 GTL4/8
59-,16-
H_INIT#
PCI_AD(13) H2 PCI_AD13 CPU I/F CPU_INTR AB22 16- GTL4/8
H_INTR
PCI_AD(14) L3 PCI_AD14 CPU_NMI V21 16- H_NMI R37
PCI_AD(15) F5 PCI_AD15 CPU_PWRGOOD Y23 GTL4/8
17- H_PWRGD ICH_SMDAT_3 26-,25-,20-,15- 1 2
PCI_AD(16) F4 PCI_AD16 CPU_RCIN# U22 GTL4/8
40- KBCPURST#_3 2.2K_1%
PCI_AD(17) N1 PCI_AD17 CPU_SLP# U21 17- GTL4/8
H_CPUSLP# R63 2
PCI_AD(18) E5 PCI_AD18 CPU_SMI# W23 16- H_SMI# ICH_SMCLK_3 26-,25-,20-,15-,37- 1
PCI_AD(19) N2 PCI_AD19 CPU_STPCLK# V23 16-,5- GTL4/8
H_STPCLK# 2.2K_1%
PCI_AD(20) E3 PCI_AD20
PCI_AD(21)
PCI_AD(22)
N3
E4
PCI_AD21 PCI HUB_PD0
L19
L20
HUB_PD(0)
HUB_PD(1)
HUB4/8

21-
RUNSCI0#_3 40-,37- 1 R71 2
PCI_AD22 HUB_PD1 HUB_PD(10:0) 10K_5%
PCI_AD(23)
PCI_AD(24)
M5
E2
PCI_AD23 I/F HUB_PD2
M19
M21
HUB_PD(2)
HUB_PD(3)
HUB4/8

HUB4/8
+V_RTC
PCI_AD24 HUB_PD3 HUB4/8

PCI_AD(25) P1 PCI_AD25 P19 HUB_PD(4)

PCI_AD(26) HUB_PD4 R19 HUB_PD(5)
HUB4/8 POWER15/5

E1 PCI_AD26 HUB_PD5 HUB4/8

PCI_AD(27) P2 PCI_AD27 T20 HUB_PD(6)

HUB_PD6 R20
HUB4/8

R41
PCI_AD(28) D3 PCI_AD28 HUBLINK HUB_PD7 P23
HUB_PD(7) HUB4/8
INTRUDER#_3 37- 1 2
PCI_AD(29) R1 PCI_AD29 HUB_PD(8)
PCI_AD(30) D2 PCI_AD30
I/F HUB_PD8 L22 HUB_PD(9)
HUB4/8

+V1.8S
100K_5%
PCI_AD(31) HUB_PD9 N22 HUB_PD(10)
HUB4/8

P4 PCI_AD31 HUB_PD10 HUB4/8

54-,51-,55- K21 1
PCI_CBE#(3:0) HUB_PD11
PCI_CBE#(0) J2 PCI_C/BE#0 T21 15- R1386
HUB_CLK CLK4/16
CLK_ICHHUB 2 POWER15/5

PCI_CBE#(1) K4 PCI_C/BE#1 36.5_1% +VS_HUBREF

PCI_CBE#(2) M4 N20 21- R1390
PCI_C/BE#2 HUB_PSTRB# HUBST5/10/15-4/8/12
HUB_PSTRB#
PCI_CBE#(3) N4 PCI_C/BE#3 P21 21- 2 150_1%
HUB_PSTRB HUBST5/10/15-4/8/12

R23 HUB_PSTRB
HUB_VREF_ICH
HUB_RCOMP 1 LAYOUT NOTES : R1749 , C179 , C158 , R222
54-,37- C1 PCI_GNT#0 M23
MPCIGNT0#_3 55-,37- HUB_VREF R22
NICGNT1#_3 E6 PCI_GNT#1 HUB_VSWING 2 CLOSE TO ICH4
51-,37- A7 PCI_GNT#2 +V3S
CBGNT2#_3 J19 1 C1389 C1390
POWER15/5

GNT3#_3
37- B7 PCI_GNT#3 INT_APICCLK R83 2 1 0_5% 1 R1389 +V1.8S
37- D6 H19 R84 2 1 10K_5% 150_1%
GNT4#_3 PCI_GNT#4 INT_APICD0 2
0.01UF_16V 2
K20 R98 2 1 10K_5% 0.01UF_16V
INT_APICD1 D5 2
1
54-,37- B1 PCI_REQ#0 INT_PIRQA# 29-,37-
MPCIREQ0#_3 55-,37- Interrupt INT_PIRQB# C2 PIRQA#_3
NICREQ1#_3 A2 PCI_REQ#1 37- PIRQB#_3 R86
51-,37- B3 B4 51-,37- 10K_5%
CBREQ2#_3 37- C7
PCI_REQ#2 I/F INT_PIRQC# A3 51-,37-
PIRQC#_3
REQ3#_3 PCI_REQ#3 INT_PIRQD# C8 PIRQD#_3 1 1
37- B6 PCI_REQ#4 55-
REQ4#_3 INT_PIRQE#/GPIO2 D7 PIRQE#_3 R1387
INT_PIRQF#/GPIO3 54-,37- PIRQF#_3
15- P5 C3 51-,37- 150_1%
CLK_ICHPCI_3R CLK4/16 PCI_CLK INT_PIRQG#/GPIO4 C4 PIRQG#_3
PCI_DEVSEL#_3 55-,54-,51-,37- M3 PCI_DEVSEL# INT_PIRQH#/GPIO5 37- PIRQH#_3 +VS_HUBVSWING 2
55-,54-,51-,37- F1 PCI_FRAME# INT_IRQ14 AC13 48-,37-
PCI_FRAME#_3 AA19 IRQ14_3
RUNSCI0#_3 40-,37- B5 PCI_GPIO0/REQA# INT_IRQ15 49-,37- IRQ15_3
20-,37- A6 J22
59-,51-,42-,40-,37-
THERM_SCI# PCI_GPIO1/REQB#/REQ5# INT_SERIRQ SERIRQ_3 POWER15/5

DMA_GNTA#_3 37- E8 PCI_GPIO16/GNTA#

37- C5 D10 1 C1387
DMA_GNTB#_3 PCI_GPIO17/GNTB#/GNT5# EER_CS
55-,54-,51-,37- L5 D11
PCI_IRDY#_3
55-,54-,51- G1
PCI_IRDY# EEPROM EER_DIN
A8
+V3A 2 0.01UF_16V 1
PCI_PAR_3 PCI_PAR EER_DOUT
PCI_PME#_3 PCI_PERR#_3 55-,54-,51-,37- L4 PCI_PERR# I/F EER_SHCLK C12 POWER15/5
R1388
37- M2 150_1%
55-,54-,51-,37- PCI_LOCK#_3 PCI_LOCK#
W2 PCI_PME# LAN_RXD0 A10
2
U5 A9
55-,54-,51-,40-,37- K5
PCI_RST# LAN LAN_RXD1
A11
PCI_SERR#_3 PCI_SERR# LAN_RXD2 +V3S
PCI_STOP#_3
55-,54-,51-,37- F3 PCI_STOP# I/F LAN_TXD0 B10
PCI_PME#_3
55-,54-,51-,37- F2 PCI_TRDY# LAN_TXD1 C10
PCI_TRDY#_3 A12 55-,54-,51-,37- 1 R1356 2
LAN_TXD2
+V3S LAN_JCLK C11
B11 10K_5% R52 2 R77 2 20-,37-
LAN_RSTSYNC MPCIGNT0#_3 54-,37- 1 1
THERM_SCI#
LAN_RST# Y5 2 8.2K_5% 8.2K_5%
U1039 R40 55-,37- 1
R70 2 1 R85 2 37-
NICGNT1#_3 DMA_GNTA#_3
1
5
6
55-,48-,29-,21- ITL_ICH4_M_BGA_421P 1K_1%
51-,37- 1
R91 2 1 R75 2 37-
+V3S 1 +V3S CBGNT2#_3 DMA_GNTB#_3
PCI_RESET1#_3 8.2K_5% 8.2K_5%
2 FAIR_NC7WZ17_SC70_6P 1 R90 2 1 R93 2
GNT4#_3 37- 37- GNT3#_3
R76 2 R48 2 R6955-,54-,51-,40-,37-
2
8.2K_5% 8.2K_5%
1 29-,37- 55-,54-,51-,37- 1 1
PIRQA#_3 PCI_FRAME#_3 PCI_SERR#_3 8.2K_5% 8.2K_5%
8.2K_5% 8.2K_5% 8.2K_5%
+V3S
1 R51 2 37- 55-,54-,51-,37- 1 R68 2 1 R47 255-,54-,51-,37-
PIRQB#_3 PCI_IRDY#_3 PCI_DEVSEL#_3 Engineer

U1039 5
59-,54-,51-,42-,40-
1 R74
8.2K_5%
2 51-,37- PIRQC#_3 PCI_TRDY#_3 55-,54-,51-,37- 1 R50
8.2K_5%
2 1 R67
8.2K_5%
255-,54-,51-,37-
PCI_PERR#_3
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INVENTEC
3 4 R&D CHK Size
1 R60 2 51-,37- 55-,54-,51-,37- 1 R49 2 1 R1439 2 37- TITLE
PCI_RESET2#_3 PIRQD#_3 PCI_STOP#_3 PCI_LOCK#_3 A3
FAIR_NC7WZ17_SC70_6P
2 8.2K_5%
8.2K_5%
8.2K_5%
8.2K_5%
8.2K_5%
8.2K_5%
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
ICH4-1
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 37 of 67
EE2 Thursday, July 31, 2003 10:55:45 am A02 PC8803

 +V3S +V3S
+V3A +V3S
+V3A
1 1
1 2
R45 R38
1
R1434
OPEN 8.2K_5% U1037 R43
10K_5%
R46
100K_5%
10K_5% 2 2 D1
AGPBUSY#_3
30- R2 PM_AGPBUSY#/GPIO6 2 1
19-,16- Y3 R3 1 3 57-,56-,43-
2 ITP_DBRESET# PM_SYSRST# GPIO_7 PREP
40- AB2 V4 40-
LOW_BAT#_3 PM_BATLOW# GPIO_8 WAKEUP0#_3
30- T3 GPIO_12 V5 49- BAT54
C3_STAT# PM_C3_STAT#/GPIO21 Unmuxed MBAY_ATTACHED#
1 R1430 2 AC2
59-,55-,54-,51-,42-,40- GPIO_13 W3 59-
CLKRUN#_3 PM_CLKRUN#/GPIO24 V2 LID_SW#_3
PM_DPRSLPVR 11- 33_5% V20 PM_DPRSLPVR GPIO GPIO_25 57-
MBAY_DISABLE
59-,57-,40- AA1 PM_PWRBTN# GPIO_27 W1
PM_PWROK PWR_SWIN#_3 W4
40- 1 R1420 2 AB6
0_5% Y1
PM_PWROK Power GPIO_28
PM_RI# Management
VCC1_POR#_3 40-,14- AA6 PM_RSMRST#
15- W18 IDE_PDCS1# Y13 48-
1 SLP_S1#_3R PM_SLP_S1#/GPIO19 AB14 PDCS1#_3
59-,47-,45-,40-,13-,12-,9-,7- Y4 PM_SLP_S3# IDE_PDCS3# 48-
R6020 SLP_S3#_3R AB21 PDCS3#_3
R1433 1 2 OPEN Y2 PM_SLP_S4# IDE_SDCS1# 49-
SDCS1#_3
10K_5% 13- 1 2 0_5% AA2 AC22 49-
SLP_S5#_3R PM_SLP_S5# IDE_SDCS3# SDCS3#_3
15-,11- R1432 W19
2 CPUSTOP#_3 PM_STPCPU#/GPIO20
15- Y21 IDE_PDA0 AA13 48-
PCISTOP#_3 PM_STPPCI#/GPIO18 AB13 PDA(0)
TP550 AA4 PM_SUS_CLK IDE_PDA1 48-
W13 PDA(1)
59-,42-,40-,30- AB3 PM_SUS_STAT#_LPCPD# IDE_PDA2 48-
SUS_STAT#_3 AA20 PDA(2)
TEMP_WARN#_3 20- V1 PM_THRM# IDE_SDA0 49-
SDA(0)
IDE_SDA1 AC20 49-
AC21 SDA(1)
J21 IDE_SDA2 49-
PM_GMUXSEL/GPIO23 SDA(2)
Y20 48-
SB_VGATE 11- V19 PM_CPUPERF#/GPIO22
PM_VGATE/VRMPWRGD
IST IDE_PDD0
AB11 PDD(0)
PDD(15:0)
AC11 PDD(1)
IDE_PDD1 Y10
BITCLK_3_ICH 45- B8 AC_BITCLK IDE_PDD2 PDD(2)
59-,45- C13 AC_RST# AA10 PDD(3)
CODEC_RST#_ICH IDE_PDD3 AA7
+V3S SDATA_IN0_ICH
45- D13 AC_SDATAIN0 IDE_PDD4 PDD(4)
SDATA_IN1_ICH 59- A13
B13
AC_SDATAIN1 AC97 IDE_PDD5
AB8
Y8
PDD(5)
PDD(6)
SDATA_OUT_ICH 59-,45- D9
AC_SDATAIN2
AC_SDATAOUT I/F IDE IDE_PDD6
IDE_PDD7
AA8 PDD(7)
59-,45- C9 AB9 PDD(8)
1
R44
FRAME_SYNC_ICH AC_SYNC
I/F IDE_PDD8
IDE_PDD9
Y9 PDD(9)
LPC_AD(0) 59-,42-,40- T2 LPC_AD0 AC9 PDD(10)
OPEN IDE_PDD10 W9
LPC_AD(1) 59-,42-,40- R4 LPC_AD1 IDE_PDD11 PDD(11)
LPC_AD(2) 59-,42-,40- T4 LPC_AD2 AB10 PDD(12)
2
LPC_AD(3) 59-,42-,40- U2 LPC_AD3 LPC IDE_PDD12
IDE_PDD13
W10
W11
PDD(13)
LPC_DRQ0# 42- U3 LPC_DRQ0# PDD(14)
LPC_DRQ1# 59- U4 LPC_DRQ1# I/F IDE_PDD14
IDE_PDD15
Y11
W17
PDD(15) 49- SDD(15:0)
LPC_FRAME#_3 59-,42-,40- T5 LPC_FRAME# IDE_SDD0 SDD(0)
AB17 SDD(1)
IDE_SDD1 W16
USB_PP0 50- C20 USB_PP0 IDE_SDD2 SDD(2)
50- A21 USB_PP1 AC16 SDD(3)
USB_PP1 IDE_SDD3 W15
USB_PP2 57- C18 USB_PP2 IDE_SDD4 SDD(4)
57- A19 USB_PP3 AB15 SDD(5)
USB_PP3 IDE_SDD5
58- C16 USB_PP4 W14 SDD(6)
USB_PP4 IDE_SDD6 AA14
USB_PP5 A17 USB_PP5 IDE_SDD7 SDD(7)
50- D20 USB_PN0# Y14 SDD(8)
USB_PN0 IDE_SDD8 AC15
USB_PN1 50- B21 USB_PN1# IDE_SDD9 SDD(9)
57- D18 USB_PN2# AA15 SDD(10)
USB_PN2 IDE_SDD10
USB_PN3 57- B19 USB_PN3# USB IDE_SDD11
Y15
AB16
SDD(11)
USB_PN4 58- D16 USB_PN4# SDD(12)
+V5A USB_PN5 B17 USB_PN5# I/F IDE_SDD12
IDE_SDD13
Y16
AA17
SDD(13)
R87 IDE_SDD14 SDD(14)
+V5A B15 USB_OC0# Y17 SDD(15)
10K_5% USB_OC#0 IDE_SDD15
1 2 C14 USB_OC1#
R88 USB_OC#1 A15 USB_OC2# IDE_PDDACK# Y12 48-
PDDACK#_35
+V5A 1 2 B14 USB_OC3# IDE_SDDACK# AB19 49-
SDDACK#_35
A14 USB_OC4# IDE_PDDREQ AA11 48-
10K_5% 210K_5% AB18 PDDRQ_35
R89 1 D14 USB_OC5# IDE_SDDREQ 49-
SDDRQ_35 +V_RTC
+V3S IDE_PDIOR# AC12 48- +V3L
PDIOR#_3
R1398 1 2 A23 USB_RBIAS IDE_SDIOR# Y18 49-
48- SDIOR#_3
22.6_1% B23 USB_RBIAS# IDE_PDIOW# W12 PDIOW#_3
IDE_SDIOW# AA18 49-
SDIOW#_3
R82 1 2 OPEN J20 IDE_PIORDY AB12 48-
GPIO32 AC19 PDIORDY_35 1
R1391 1 2 OPEN G22 IDE_SIORDY 49-
SDIORDY_35
GPIO33

2
F20 R65
VMEM_CFG0 GPIO34 J23 180K_1%
G20 GPIO35 CLK_14 15- CLK_ICH14_3R
VMEM_CFG1 F21 F19 15- D1026
VMEM_CFG2 GPIO36 CLK_48 CLK_ICH48_3R 2
GPIO W7 BAT54C

3
FWH_WP#_3 59- H20 RTCRST# C1403
59- F23 GPIO37 Clocks AC7 C1419 15PF_50V
FWH_TBL#_3 GPIO38 CLK_RTCX1 1 1
+V3S H22 CLK_RTCX2 AC6 1 2

1
G23 GPIO39 Y6 1
SER_SHD#_3 GPIO40 CLK_VBIAS 1 4 3
X1004 R66 2
SHUTDOWN 47- H21 GPIO41 2 C45 OPEN
R1422
VMEM_CFG3
F22 GPIO42 SPKR H23 32.768KHZ 0.1UF_16V 2 1UF_10V
PP_FDD_SMI
42- E23
GPIO43
Misc THRMTRIP# W20
10M_5%
RTCBAT
2 1 2
+V3S R1405
OPEN
2
R117
1 2
R116
1
8.2K_5%
ITL_ICH4_M_BGA_421P C1418
1
15PF_50V
2 2 1K_5% 1
R114 R115
OPEN 8.2K_5% +VCCP C1405
2 1 2 1 5 U1031 1 1
R119 R118
OPEN 8.2K_5% 2 4 42- NPCI_RESET 0.047UF_10V 2 R1406 2 C1404
2 1 2 1 0.1UF_16V
R1392 1 1
1 R1393 2 8.2K_5% TC7S04F 2 10M_5% 1
OPEN 3
2 1 R1139 R112
56_5% 56_5% 45- PCSPKR_ICH_3
2 2

GPIO[34:36,42] VMEM_CFG(3:0)-Memory type GPIO[34:36,42] VMEM_CFG(3:0)-Memory type

16- PM_THRMTRIP# RTC CIRCUITRY
00 00h Samsung 64MB 08 08h Infineon 32MB
1 C6039
$V

01 01h Samsung 128MB 09 09h TBD 2 0.1UF_16V

02 02h Hynix 64MB 10 Ah TBD Engineer
03 03h Hynix 128MB 11 Bh TBD
David Du
Drawn by
David Du
INVENTEC
04 04h Infineon 64MB 12 Ch TBD R&D CHK Size
TITLE
05 05h Infineon 128MB 13 Dh A3
TBD
06 06h Samsung 32MB 14 Eh TBD
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
07 07h Hynix 32MB 15 Fh TBD
ICH4-2
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 38 of 67
EE2 Thursday, August 21, 2003 11:35:30 am A02 PC8803

 +V1.5A +V1.5A_ICH

L1025 0.1UF_16V 0.1UF_16V 0.1UF_16V +V3S

1 2
BLM21B121SD
L1031
U1037 1 C1391 1 C81 1 C66 1 C47 1 2
BLM21A121S
2 2 2 2
A1 VSS0
A4 VSS1 VSS52 G19
A16
A18
VSS2
VSS3
VSS53
VSS54
G21
H1
U1037
A20 VSS4 VSS55 J6 10UF_K_6.3V E12 VCCSUS1.5_0 VCC3.3_0 A5
A22 VSS5 VSS56 K3 +V1.5S E13 VCCSUS1.5_1 VCC3.3_1 B2
AA3 VSS6 VSS57 K11 0.1UF_16V E20 VCCSUS1.5_2 VCC3.3_2 H6
AA9 VSS7 VSS58 K13 +V3S F14 VCCSUS1.5_3 VCC3.3_3 H18
AA12 VSS8 VSS59 K19 G18 VCCSUS1.5_4 VCC3.3_4 J1 1 1 1 1 1 1 1 1 1 1 1
AA16 VSS9 VSS60 K23 +V3S 1 C82 R6 VCCSUS1.5_5 VCC3.3_5 J18 2 2 2 2 2 2 2 2
2 2 2
AA22 VSS10 VSS61 L10 2 T6 VCCSUS1.5_6 VCC3.3_6 K6 C55 C61
C56 C48 C79 C58
AB7 VSS11 VSS62 L11 U6 VCCSUS1.5_7 VCC3.3_7 M10 C49 C1420 C59 C50 C1439
AB20 VSS12 VSS63 L12 1 VCC3.3_8 P6 0.1UF_16V 0.1UF_16V0.1UF_16V 0.1UF_16V 0.1UF_16V 0.1UF_16V 0.1UF_16V 0.1UF_16V 0.1UF_16V 0.1UF_16V 10UF_K_6.3V
AC1 VSS13 VSS64 L13 D1031 VCC3.3_9 P12
AC5 VSS14 VSS65 L14 VCC3.3_10 U1
AC10 VSS15 VSS66 L21 +V5S +V5S_ICHREF F6 VCCLAN1.5_0 VCC3.3_11 V10
AC14 VSS16 VSS67 M1 3 1 C68 F7 VCCLAN1.5_1 VCC3.3_12 V16
+V5L
AC18 VSS17 VSS68 M11 VCC3.3_13 V18
BAT54 2

POWER
AC23 VSS18 VSS69 M12 1 R1423 2 0.1UF_16V VCC3.3_14 AC8 +V1.5S
B9 VSS19 VSS70 M13 1K_1% E9 VCCLAN3.3_0 VCC3.3_15 AC17
B12 VSS20 VSS71 M20 1 1 F9 VCCLAN3.3_1
C1422 C51
B16 VSS21 VSS72 M22 C1407 VCC1.5_0 K10
2 0.1UF_16V 2
VSS

B18 VSS22 VSS73 N5 1UF_16V VCC1.5_1 K12

B20 VSS23 VSS74 N10 1 R1408 2 E7 VCC5REF1 VCC1.5_2 K18 1 1 1 1 1
B22 VSS24 VSS75 N11 1K_1% V6 VCC5REF2 VCC1.5_3 K22 2 C74 2 C57 2 C62 2 C78 2 C1421
C6 VSS25 VSS76 N12 +V3A VCC1.5_4 P10 0.1UF_16V 0.1UF_16V 0.1UF_16V
C15 VSS26 VSS77 N13 1 VCC1.5_5 T18 0.1UF_16V 10UF_K_6.3V
C17 VSS27 VSS78 N14 E15 VCC5REFSUS1 VCC1.5_6 U19
C19 VSS28 VSS79 N19 1UF_16V 2 VCC1.5_7 V14
C21 VSS29 VSS80 N21 0.1UF_16V +V1.8S L23 VCCHI_0
C23 VSS30 VSS81 N23 M14 VCCHI_1 VCCRTC AB5
D1 VSS31 VSS82 P3 1 C67 P18 VCCHI_2
D4 VSS32 VSS83 P11 2 T22 VCCHI_3 VCCSUS3.3_0 E11
D8 VSS33 VSS84 P13 BAT54 VCCSUS3.3_1 F10
D12 VSS34 VSS85 P20 1 3 VCCSUS3.3_2 F15
D1027
D15 VSS35 VSS86 P22 C22 VCCPLL VCCSUS3.3_3 F16 +V_RTC
D17 VSS36 VSS87 R5 VCCSUS3.3_4 F18
D19 VSS37 VSS88 R18 C95 C75 VCCSUS3.3_5 K14
D21 VSS38 VSS89 R21 1 C1388 1 C94 1 C76 1 1 P14 VCC_CPU_IO_0 VCCSUS3.3_6 V7
D22 VSS39 VSS90 T1 2 2 2 2 2 U18 VCC_CPU_IO_1 VCCSUS3.3_7 V8
D23 VSS40 VSS91 T19 AA23 VCC_CPU_IO_2 VCCSUS3.3_8 V9
E10 VSS41 VSS92 T23 VCCSUS3.3_9 F17
E14 VSS42 VSS93 U20 10UF_K_6.3V
E16 VSS43 VSS94 V3 1
0.1UF_16V 0.1UF_16V 0.1UF_16V
E17
E18
VSS44
VSS45
VSS95
VSS96
V15
V17 0.1UF_16V
ITL_ICH4_M_BGA_421P 2
C44
E19 VSS46 VSS97 W5 0.1UF_16V
E21 VSS47 VSS98 W8 +V1.5S
E22 VSS48 VSS99 W22
F8 VSS49 VSS100 Y7
G3 VSS50 VSS101 Y19
G6 VSS51

+V3A_ICH +V3A
ITL_ICH4_M_BGA_421P 1
C77

0.01UF_16V
1 L1027 2
+VCCP BLM21A121S

1 1 1 1 1 1
1 R245 2 C244 C60 C1386
2 C65 2 C80 2 C64 2 C46 2 C63 2 C1406
0_5% 1 1 1 0.1UF_16V 0.1UF_16V 0.1UF_16V 0.1UF_16V 0.1UF_16V 10UF_K_6.3V
2 2 2
0.1UF_16V
1UF_16V 0.1UF_16V

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
ICH4-3
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 39 of 67
EE2 Thursday, July 31, 2003 10:55:59 am A02 PC8803

 +V3S
+V3A +V3A_MSIO +V3S_MSIO

1 L1029 2 0.1UF_16V 1 L1023 2

BLM21A121S C1392 BLM21A121S
1 1 C1410 1 C83 1 C97 1 C98 1 1 C99 1 C85 1 C84
C1409
2 10UF_K_6.3V 2 2 2 0.1UF_16V 2 0.1UF_16V 10UF_K_6.3V 2 2 2 0.1UF_16V

0.1UF_16V 0.1UF_16V 0.1UF_16V

U1033

11
67
81
94

VCC2 30
VCC2 38
VCC2 47
VCC1
VCC1
VCC1
VCC1
SCAN_OUT(11:0) 59-,41- +V3A

SCAN_OUT(0) 17 KSO0 OUT0 99 37-

RUNSCI0#_3
SCAN_OUT(1) 16 KSO1 OUT1_IRQ8# 100 TP573
SCAN_OUT(2) 15 KSO2
SCAN_OUT(3) 14 KSO3 OUT7_SMI# 98 6-
BATSELB_A#
SCAN_OUT(4) 13 KSO4 OUT8_KBRST 97 TP574 37-
KBCPURST#_3 1 1 D1030

General Purpose I/O Interface

20K_5%

20K_5%
SCAN_OUT(5) 12 96 36-

R104

R102
KSO5 OUT9_PWM2 INV_PWM_3 BAT54
10 95

Keyboard/Mouse Interface
SCAN_OUT(6) KSO6 OUT10_PWM0 20-
FAN_PWM_3 3 1
SCAN_OUT(7) 9 KSO7 OUT11_PWM1 93 5-
CHGCTRL_3 58-,54- XMIT_OFF#
SCAN_OUT(8) 7 KSO8 2 2
SCAN_OUT(9) 6 KSO9 GPIO2 62 59-,57-,38- PWR_SWIN#_3

SMSC_LPC47N250_TQFP_100P
SCAN_OUT(10) 5 KSO10 GPIO3 63
SCAN_OUT(11) 4 KSO11 GPIO4_KSO14 64 59- VOL_DN
SCAN_IN(7:0) 41-,59- TP129 3 KSO12_OUT8_KBRST GPIO5_KSO15 66 59- VOL_UP
2 KSO13_GPIO18 R1411 55- AIRACIN2
GPIO7_PWM3 68 1 2 +V3A
SCAN_IN(0) 25 KSI0 GPIO8_RXD 69 5- 10K_5% C315
ACIN# 22PF_50V
SCAN_IN(1) 24 KSI1 GPIO9_TXD 70 38-
LOW_BAT#_3 1 2 +V3A
SCAN_IN(2) 23 KSI2 R1 1 2100K_1% R1410 1 210K_5%
SCAN_IN(3) 22 KSI3 6- R99 1 100K_5% 2
BATSTAT#
SCAN_IN(4) 21 KSI4 GPIO11_AB2A_DATA 71
SCAN_IN(5) 20 KSI5 GPIO12_AB2A_CLK 72 59-
SCROLL_LED#_3
SCAN_IN(6) 19 KSI6 GPIO13_AB2B_DATA 73 59-,40- NUM_LED#_3
SCAN_IN(7) 18 KSI7 GPIO14_AB2B_CLK 74 6- THM_MBAY#
GPIO15_FAN_TACH1 75
IM_CLK_5 41- 26 IMCLK GPIO16_FAN_TACH2 76 6- THM_MAIN# 55-,54-,51-,37-
IM_DAT_5 41- 27 IMDAT GPIO17_A20M 77 37- A20GATE_3
57- 29 PCI_SERR#_3
KB_CLK_5 KCLK
KB_DAT_5 57- 31 KDAT GPIO20_PS2CLK 78 6-,5- AIRACIN#
EM_CLK_5 57- 32 EMCLK GPIO21_PS2DAT 80 59-,47-,45-,38-,13-,12-,9-,7- SLP_S3#_3R
EM_DAT_5 57- 33 EMDAT

Access Bus Interface

AB1A_DATA 86

Power Mgmt
6- SDA_MAIN
59-,55-,54-,51-,42-,38- 44
CLKRUN#_3 CLKRUN# AB1A_CLK 87 6- SCL_MAIN
46
SIRQ
SERIRQ_3 59-,51-,42-,37- SER_IRQ +V3A_MSIO
CLK_KBCPCI_3R 15- 43 PCI_CLK AB1B_DATA 84 57-,6- SDA_MBAY
WAKEUP0#_3 38- 59 EC_SCI# AB1B_CLK 85 57-,6- SCL_MBAY
+V3S 59-,38-,42- R103 1 2 10K_5%
40- PWRGD
R107 1 2 OPEN
LPC_AD(3:0) R108 1 2 1K_1%
LPC_AD(3) 40 LAD3 56 R101 1 2 OPEN
PGM
LPC Bus

LPC_AD(2) 39 LAD2 82 R100 1 2 OPEN

1 FWP# FAIR_NC7WZ17_SC70_6P
LPC_AD(1) 37 LAD1 83 R13991 2 1K_1%
R128 EA# FAIR_NC7WZ17_SC70_6P
LPC_AD(0) 35 48 15- CLK_KBC14_3R

Miscellaneous
LAD0 CLOCK
10K_5% 58 52-,51-S_CLK
32KHZ_OUT +V3S
2 LPC_FRAME#_3 59-,42-,38- 41 LFRAME# RESET_OUT# 49 38- PM_PWROK PWR_GOOD_3 FOR FINE-TUNE SEQUENCE TIME
59-,54-,51-,42-,37- 42 LRESET# 61 1 R105 2 59-,30-,14-,11-
PCI_RESET2#_3 PWRGD
1 R127 2
59-,42-,38-,30- 34 LPCPD# 60 1 R62 2 38-,14-
SUS_STAT#_3 VCC1_PWRGD VCC1_POR#_3 OPEN C314 0.1UF_16V
OPEN 24MHZ_OUT 50 1K_5%
TEST_PIN 1 TP576 1 2
57 1 R106 2 40-
D1065 1N4148
MODE PWRGD
53 XTAL1 10K_5% 1 2
RTC

54 91 5 U1045 5 U1045
X1003
XTAL2 DMS_LED# +V3A R279
51 VCC0 BAT_LED# 88 59-
BAT_LED#_3
CN1006 1 6 1 2 3 4
32.768KHZ 1
52 XOSEL PWR_LED#_8051TX 90 59-,57- 1 150K_1%
55 AGND

PWR_LED#_3 2 1 C316
1 4 FDD_LED#_8051RX 89 59- 2
GND
GND
GND
GND
GND
GND
GND

CAPS_LED#_3 2 2
3 3 G 7 2
NUM_LED#_3 4
2 3 +V_RTC 4 G 8 0.1UF_16V
5
92
79
65
45
36
28

5
8

6 6
1 C1412 1 C1411
1
2 15PF 2 15PF MLX_67451_0006
R1413
300_5%
1 C1413
2
2 0.1UF_16V

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
KBC
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 40 of 67
EE2 Thursday, July 31, 2003 10:56:09 am A02 PC8803

 +V3A

R230
OPEN ROHM_UMP11_SSOP_6P
2
CN13
1 1 ROHM_UMP11_SSOP_6P 41- 40-,41-
R212 2 KSCAN_IN(4) SCAN_IN(4)
1 2 2 4 3
3 3 41- 40-,41-
SCAN_OUT(9)
OPEN 4 KSCAN_IN(0) SCAN_IN(0) 41-
4 4 3 KSCAN_IN(12)
KSCAN_IN(9) 41- 5 5 5
KSCAN_IN(11) 41- 6 6 41- 40-,41- 59-,41-
41- 7 KSCAN_IN(8) SCAN_IN(5) KSCAN_IN(5)
KSCAN_IN(13) 7 5 6 2
SCAN_IN(7) 59-,40-,41- 8 8 40-,41- 59-,41-
41- 9 SCAN_IN(1) KSCAN_IN(1) 41-
KSCAN_IN(6) 9 6 2 KSCAN_IN(13)
KSCAN_IN(5) 59-,41- 10 10 1
SCAN_OUT(1) 11 11 41-
SCAN_OUT(10) 12 KSCAN_IN(9)
12 1 U1028
SCAN_OUT(6) 13 13
SCAN_OUT(7) 14 14
SCAN_OUT(4) 15 15
U1030
SCAN_OUT(8) 16 16
SCAN_OUT(3) 17 17
KSCAN_IN(3) 41- 18 18
59-,41- 19 19 ROHM_UMP11_SSOP_6P
KSCAN_IN(1) ROHM_UMP11_SSOP_6P
KSCAN_IN(2) 41- 20 20
41- 21 41- 40-,41-
KSCAN_IN(4) 21 KSCAN_IN(6) SCAN_IN(6)
41- 22 41- 40-,41-
KSCAN_IN(0) 22 KSCAN_IN(2) SCAN_IN(2) 4 3
41- 23 23 4 3
KSCAN_IN(10)
KSCAN_IN(12) 41- 24 24 41-
41- 25 41- KSCAN_IN(14)
KSCAN_IN(8) 25 KSCAN_IN(10) 5
KSCAN_IN(14) 41- 26 26 5
SCAN_OUT(5) 27 27 40-,41- 41- 6 2
SCAN_OUT(2) 28 SCAN_IN(3) KSCAN_IN(3)
28 6 2
SCAN_OUT(0) 29 29
SCAN_OUT(11) 30 30 41- 1
KSCAN_IN(11)
1
MLX_52610_3094_30P U1027
U1029
59-,40- +V5S
SCAN_OUT(11:0)

L14
1 2
BLM21A121S

+5VS_IM
C173 1
1 1
R1278 R1279 680PF 2
4.7K_5% 4.7K_5%

2 2
CN10
1 1
(15/5) 2 2
40- 3 3
IM_DAT_5 4
40-
+V3A IM_CLK_5 5
4 TOUCH PAD
5
6 6
7 7 G 13
5 1 2 3 4 8 8 G 14
9 9 G 15
$V
RS1056
RS1 KSCAN_IN(0) 41- 4 5 40-,41- 10 10 G 16
40-,41- 59-,41- SCAN_IN(0) 11
47K SCAN_IN(1) 3 6
KSCAN_IN(1) 11
KSCAN_IN(2) 41- 2 7 40-,41- CN8 12 12
40-,41- 41- SCAN_IN(2) 1
SCAN_IN(3) 1 8 1
6 7 8 9 10 KSCAN_IN(3) 2
2 MLX_52559_1292_12P
OPEN 3
3 4
4
5
5 6
9 G 6
10 G 7 7
8
8
MLX_52559_0890_8P
SCAN_IN(0)
41-
$V
RS1057
SCAN_IN(1) KSCAN_IN(4) 4 5 40-,41-
SCAN_IN(4)
SCAN_IN(2) SCAN_IN(5) 40-,41- 3 6 59-,41-
SCAN_IN(3) 41- 40-,41-
KSCAN_IN(5)
KSCAN_IN(6) 1 8
SCAN_IN(4)
SCAN_IN(6)
2 7
SCAN_IN(5)
SCAN_IN(6) OPEN
SCAN_IN(7) POINT STICK

59-,40-,41- Engineer
SCAN_IN(7:0) David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
INT.KBC/POINT DEVICES
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 41 of 67
EE2 Thursday, July 31, 2003 10:56:18 am A02 PC8803

 SRXD_3 +V5S
STXD_3 43-
SDSR#_3 57-,43-
43- 57-,44-
SRTS_3 STRB#_5
57-,43- 57-,44-
SCTS_3 57-,44- ALF#_5
SDTR#_3 43- ERROR#_5
57-,43- 57-,44-
RI#_3
57-,44- ACK#_5 1 +V3S
SDCD#_3 43- BUSY_5
43- 57-,44- R135
57-,44- PE_5 100K_1%
+V3S SLCT_5
2

+V3S
1 C96 1 C112 1 C1364 1 C117
Q1045 6 49-,48-,42-
R1362 2 1 10K_5% D1 MTR0#_3 2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V
R1363 2 1 10K_5% 44-,42- 2 G1
PTF 1
R1364 2 1 10K_5% S1
R1365 2 1 10K_5%
S2 4
5
G2
D2
3
FDG6301N_SC70_6

100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76 VSS
TXD1
NSTROBE
VCC
NDCD2

NDCD1
RXD2

RXD1

NALF
NACK

PE
NDSR2

NDSR1

SLCT
NERROR
NDTR2

NDTR1
TXD2

BUSY
NCTS2
NRTS2

NCTS1
NRTS1
NRI2

NRI1
44-,57-
PDATA(7:0)
+V3S +V3S
49- 1 DRVDEN0 PD7 75 PDATA(7)
DRVDEN0_3
2 DRVDEN1 PD6 74 PDATA(6)
MTR0#_3
49-,48-,42- 3 NMTR0 PD5 73 PDATA(5)
49- 4 NDSKCHG PD4 72 PDATA(4)
FE_DSKCHG#_5 49-
DS0#_3 5 NDS0 PD3 71 PDATA(3)
2 1 6 GP24 PD2 70 PDATA(2)
R1381 10K_5% 7 VSS PD1 69 PDATA(1) 42- 2 R1394 1
49- 8 NDIR
U1026 PD0 68 PDATA(0)
+V3S GP13_IRQIN1
DIR#_3 49- 57-,44- 10K_5%
STEP#_3 9 NSTEP SMSC_LPC47N227_STQFP_100P NSLCTIN 67 SLCTIN#_5
49- 10 NWDATA NINIT 66 57-,44-
WDATA#_3 PINIT#_5
WGATE#_3
49- 11 NWGATE VCC 65
49- 12 NHDSEL GP23_FDC_PP 64 44-,42- +V3S
HDSEL#_3 PTF
49- 13 NINDEX IRMODE_IRRX3 63 59-
FE_INDEX#_5 IR_SD_3
+V3S 49- 14 NTRK0 IRTX2 62 59-
FE_TRK0#_5 49- 59- IR_TX_3
FE_WPROT#_5 15 NWRTPRT IRRX2 61 IR_RX_3
FE_RDATA#_5 49- 16 NRDATA VSS 60 RS1052
17 NIO_PME GP22 59 42-
GP22 GP15
42- 3 10
TP537 42- 42- 42-
18 VTR GP21 58 GP21 GP16 9 1
GP17
59-,38-,40- 15- 19 57 42- 42-
LPC_AD(3:0) CLK_SIO14_3R CLOCKI GP20 GP20 +V3S 2 8
GP20
LPC_AD(0) 20 LAD0 GP16 56 42-
GP16 GP22
42- 6 7 42-
GP21
LPC_AD(1) 21 GP17 55 42- 5 4 42-
LAD1 GP17 +V3S GP14_IRQIN2
LPC_AD(2) 22 GP15 54 42-

GP12_NIO_SMI
GP11_SYSOPT
LAD2 GP15
23 53
NPCI_RESET
LPC_AD(3) LAD3 VCC 10K
59-,40-,38- 24 NLFRAME GP14_IRQIN2 52 42-

NCLKRUN
LPC_FRAME#_3 38- 42- GP14_IRQIN2

SER_IRQ
25 51

PCI_CLK
NLDRQ GP13_IRQIN1
LPC_DRQ0#
NLPCPD GP13_IRQIN1
+V3S

GP30
GP31
GP32
GP33
GP34
GP35
GP36
GP37
GP40
GP41
GP42
GP43
GP44
GP45
GP46
GP47
GP10
VSS RS1054
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
+V3S 42- 1 10
GP37 42- 42-
2 6
GP36 42- GP33
42- 3 7
GP35 GP32
59-,55-,54-,51-,40-,38-

42- 4 8 42-
GP34 42- GP31
+V3S 5 9
GP30
R120
59-,51-,40-,37-

1 2 10K
38- 2 R126 1
NPCI_RESET 47K_5%
0_5% +V3S
15-

42-
42-
42-
42-
42-
42-
42-
42-

42-
42-
42-
42-
42-
42-
42-
38-
R125
49-
59-,54-,51-,40-,37- 2 1
PCI_RESET2#_3
OPEN RS1053
+V3S 42- 3 10
CLK_SIOPCI_3R

GP30
GP31
GP32
GP33
GP34
GP35
GP36
GP37

MB_FDD_IDE#
GP43
GP44
GP45
GP46
GP47
GP10
SYSOPT
PP_FDD_SMI
CLKRUN#_3

SERIRQ_3

GP10
42- 2 9 42-
SYSOPT GP43
42- 4 6 42-
GP47 42- GP46
8 7 42-
GP44 GP45
+V3S +V3S 5 1

R124 R122 R121 10K

2 1 2 1 1 2

10K_5% 2 10K_5% 47K_5%

48-
49-

R123
OPEN
1
HDD_RESET#
MB_RESET
59-,40-,38-,30-
SUS_STAT#_3

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
SUPER I/O
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 42 of 67
EE2 Thursday, July 31, 2003 10:56:25 am A02 PC8803

 +V3S

0.1UF_16V
C1360
1
2 RS1051
43- 1 8 43-
0.1UF_16V R1IN 2 7
R1IN_R
+V3S R2IN 43- 43- R2IN_R
C1359 26 43- 3 6 43-
R3IN 4 5
R3IN_R
VCC R4IN 43- 43- R4IN_R
1 28 C116 0.1UF_16V
C1+ V+ 27 33
2 24 C1- 1 2
1 C1361 0.1UF_16V
R138 1 V- 3
1 1 2
100K_5% C2+
2 2 C2-
C1362
57-,42-
2
0.1UF_16V 14 T1IN
U1023
SRTS_3
T1OUT 9 43- T1OUT RS1050
STXD_3 57-,42- SDTR#_3 57-,42- 13 R5IN 43- 1 8 43- R5IN_R
T2IN 2 7
T2OUT 10 43- T2OUT T1OUT 43-
3 6
43- T1OUT_R
12 T3IN T2OUT 43- 43- T2OUT_R
T3OUT 11 43- 43- 4 5 43-
T3OUT T3OUT T3OUT_R
20 R2OUTB
33
19 R1OUT
R1IN 4 43- R1IN
SRXD_3 42-,43- RI#_3 42-,43- 18
R2OUT
42-,43-
R2IN 5 43- R2IN
17 R3OUT
SDSR#_3
42-,43-
R3IN 6 43- R3IN
16 R4OUT
SCTS_3
+V3S
42-,43-
R4IN 7 43- R4IN
15
SDCD#_3 R5OUT
R5IN 8 43- R5IN
23 FORCEON
+V3S 330PF_50V 330PF_50V 330PF_50V 330PF_50V
22 FORCEOFF# INVALID# 21
GND C1103
C1101 C1102
25
1
MAX_3243E_SSOP_28P 1 1 1 1
R1360 2 2 2 2 C1104
10K_5% CN17
2
R5IN_R 43- 1
R3IN_R 43- 6
R1IN_R 43- 2
T1OUT_R 43- 7
Q1044 3 T3OUT_R 43- 3
D R4IN_R 43- 8
PREP 57-,56-,38- 2G T2OUT_R 43- 4 G TP578
S R2IN_R 43- 9 G
5 TP579
NDS7002A 1

SYN_7517P_09G2T
C1124
1 1 1 1
C1125 2 2 2 2 330PF_50V
330PF_50V

C1127 C1126
330PF_50V 330PF_50V

+V5S +V5S
+V5
U1014 +V5
1 NC VCC 16
2 BE0 BE3 15 U1015
57- 3 A0 A3 14 57-
SRXD_3R
57- 1 VCC 5
SCTS_3R RI#_3R A
42-,43- 4 B0 B3 13 42-,43- +V5S
SCTS_3 5 BE1 BE2 12 RI#_3 42-,43- 2 B
57- 6 A1 A2 11 57- SRXD_3
SDSR#_3R SDCD#_3R
42-,43- 7 B1 B2 10 42-,43- 3 GND OE 4
SDSR#_3 8 GND NC 9 SDCD#_3
FAIR_NC7SZ66P5X_SC70_5P
PER_PI5C3126Q_QSOP_16P

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
SERIAL PORT&IR
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 43 of 67
EE2 Thursday, July 31, 2003 10:56:30 am A02 PC8803

 +V5S

RS4
4 10
D1010 BAT54
3 6 3 1
2 7

C228

C1206

C1203

C1224

C1226

C1247

C1250

C1295

C1297
1 8
5 9
1 1 1 1 1 1 1 1 1
4.7K 2 2 2 2 2 2 2 2 2

100PF_50V

100PF_50V

100PF_50V

100PF_50V

100PF_50V

100PF_50V

100PF_50V

100PF_50V

100PF_50V
C1205

C1204

C1227

C1225

C1248

C1246

C1249

C1296
1 1 1 1 1 1 1 1 CN9
RS1032 2 2 2 2 2 2 2 2 44- 1 1
STRB#_5R 2

100PF_50V

100PF_50V

100PF_50V

100PF_50V

100PF_50V

100PF_50V

100PF_50V

100PF_50V
STRB#_5 57-,42- 4 5 44- STRB#_5R PDATA(0)_R
57-,42-,44- 2
ALF#_5 57-,42- 3 6 44- 57-,42-,44- 3 3
PDATA(0) ALF#_5R PDATA(1)_R 4
2 7 57-,42-,44- PDATA(0)_R PDATA(2)_R
57-,42-,44- 4
57-,42- 1 8 RS1028 44- 57-,42-,44- 5 5
PDATA(1) ERROR#_5 ERROR#_5R PDATA(3)_R 6
8 1 57-,42-,44- PDATA(1)_R 57-,42-,44- 6
10_5% PDATA(4)_R 7
PDATA(2)
PINIT#_5 57-,42- 7 2 44- PINIT#_5R PDATA(5)_R
57-,42-,44- 7
6 3 57-,42-,44- 57-,42-,44- 8 8
PDATA(2)_R PDATA(6)_R 9
SLCTIN#_5 57-,42- RS1023 5 4 44- SLCTIN#_5R 57-,42-,44- 9
PDATA(7)_R 10
PDATA(3) 8 1 57-,42-,44- PDATA(3)_R ACK#_5R
44- 10
PDATA(4) 7 2 10_5% 44- 11 11
PDATA(5) BUSY#_5R 12
6 3 57-,42-,44- PDATA(4)_R PE_5R
44- 12
PDATA(6) RS1018 5 4 44- 13 13
PDATA(7) SLCT_5R 14
4 5 57-,42-,44- PDATA(5)_R 44- 14
10_5% ALF#_5R 15
ACK#_5
3 6
ERROR#_5R
44- 15
2 7 57-,42-,44- 44- 16 16
BUSY_5 PDATA(6)_R PINIT#_5R 17
1 8 44- 17
PE_5 57-,42- 1 2 SLCTIN#_5R 18
SLCT_5 57-,42-,44- PDATA(7)_R +V5S 18
10_5% R234 R1196 19 19
10_5% 44- 10K_5% 20 20
ACK#_5R 21 21
RS6 22 22 G 26

2
44- BUSY#_5R PTF42-,44-
4 10 23 23 G 27
3 9 44- 24 24
PE_5R
2 8 25 25
1 7 44- SLCT_5R EXTFDD_VCC
5 6 SYN_7518S_25G2
PDATA(7:0) 57-,42-,44-
4.7K

4.7K_5% 1 R233 2

C229 1 1
2 C227
47UF_6.3V_METAL 0.1UF_25V

EXTFDD_VCC
+V5

(20/5) Q1018 (20?5)

+V5 4 1
S D
2
5
3 G
6
1 C1202
FDC638P
2 4.7UF_10V
1 1
R1165 R1174
47K_5% 47K_5%
2 2
LAYOUT NOTES : PUT THESE CIRCUIT CLOSE TO PARALLER PORT

Q9 3
B C
PTF 42-,44- 2

E
1
DTC124EK

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
PARALLER PORT
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 44 of 67
EE2 Thursday, July 31, 2003 10:56:35 am A02 PC8803

 +V5
+V3S
AUDIO_VCC

(20/5)
1 C1468
R1586 1 C1467 1 1 100PF_50V
OPEN 1
2 2 C1466 U1044 C1464
1UF_10V 1 IN R1462 1
2 R12 R13 R11 49.9K_1%
OUT 5
1 2 1 2 1 2 46-,45- PHONE_AMP 22UF_10V 22UF_6.3V
Q1061 3 OPEN OPEN OPEN 2 GND 2
1 C1462
D ADJ 4
MPCI_PWM 54- 2G SLP_S3#_3R 59-,47-,40-,38-,13-,12-,9-,7- 3 EN 1 2 0.1UF_16V
S
1 C12 1 C10 1
MIC_MIC5205BM5_SOT23_5P R1464 1 C1465
2N7002_OPEN 1 R1466 143K_1%
2 OPEN 2 0_1206_1/4W 2 0.01UF_16V
OPEN 2
2

AVDD AUDIO_VCC
+V3S

LAYOUT NOTES : R697 MUST BE PLACED ACROSS DIGITAL & ANALOG GROUND
1 L1036 2
BLM21A121S
C1460
1 C17 1 C29 1 C18 1 1 C1463
1 1 1 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V
C1461 C1458 10UF_10V
10UF_10V 2 C14592
0.1UF_16V 0.1UF_16V

AUDIO_VREF
C1456 2.2UF_0805_16V 1 R1456 2 49- A_CD_L
C1435 1 2 4.7K_5%

AVDD1 25
AVDD2 38
AVDD3 43
U1043 OPEN C1434 R1455 2

DVDD1 1
DVDD2 9
59- 1
AC97_BIT_CLK 1 1 0.1UF_16V1
4.7K_5%
VREF 27 2
VREFOUT 28
2 C14332 C1454 2.2UF_0805_16V 1 R1457 2 49-
1UF_10V A_CD_GND
1 2 2.7K_5% R1452
1 2
R15 HPSENSE
SDATA_OUT_ICH 59-,38- R22 1 2 33_5% 5
SDATA_OUT JS1 16 1 2 47-
2.7K_5%
BITCLK_3_ICH 38- R21 1 2 33_5% 6 BIT_CLK 2.2K_5%
38- R20 1 2 33_5% 8 JS0 17 1 2
SDATA_IN0_ICH SDATA_IN C1455 2.2UF_0805_16V R1454
FRAME_SYNC_ICH 59-,38- R19 1 2 33_5% 10 SYNC R16 OPEN 1 2 49- A_CD_R
CODEC_RST#_ICH 59-,38- 11 RESET# CD_L 18 1 2 4.7K_5% 1 R1453 2

ADI48M 15- 2 XTL_IN CD_GND_REF 19 4.7K_5%

3 XTL_OUT
CD_R 20
C30 1 2 270PF_50V 29 AFILT1 LINE_IN_L 23 C1431 2.2UF_0805_16V 1 R1438 2 57- LINEINL
1 2 4.7K_5%
C31 1 2 270PF_50V 30 AFILT2 LINE_IN_R 24 C1432 2.2UF_0805_16V
1 2 1
C1436 1 2 270PF 31 LINE_OUT_L 35 47-
AFILT3 A_LEFT R1437
C1437 1 2 270PF 32 AFILT4 LINE_OUT_R 36 47- 4.7K_5%
A_RIGHT
C1438 OPEN 2
33 AVSS4 MONO_OUT 37 54- A_MPCI_IN 46-,45- PHONE_AMP
AVDD 1 2
C32 0.1UF_16V R14
34
AVDD4 PHONE_IN 13 C1457 1 2 OPEN 1 2
1 2 OPEN +V3S
MIC1 21 C1453 1 2 1UF_10V 46- MIC1 1
42 NC 1
45 ID0# MIC2 22 C1430 1 2 1UF_10V 46- R1458 1 R1441 2 57-
MIC2 OPEN R280 LINEINR
46 ID1# 4.7K_5%
59-,47- 47 EAPD AUX_L 14 10K_5%
EAPD 2
57- 48 SPDIF
SPDIF 2
AUX_R 15 1 C13 1 C11 1 C27 1
1
2 OPEN 2 2 OPEN 3 D Q1059 R1440
R23 HP_OUT_L 39 47- G 2 51- 4.7K_5%
4.7K_5% HPL PCSPKB_3
OPEN S 2
HP_OUT_R 41
4 DVSS1
7 DVSS2

26 AVSS1
40 AVSS2
44 AVSS3

2
47- HPR 1 2N7002
NC 12 C16 0.1UF_16V 1 R18 2 C28 1 2 0.1UF_16V
1 1 1 2 1 4.7K_5% C15 1 2 0.1UF_16V
R1460 R1459 AD_1981B_TQFP_48P 1 C14 R17
1K_1% 1K_1% 1K_5%
2 0.1UF_16V
2 2 2
+V3S

1
R281
10K_5%
2

3 D Q1060
G 2 38- PCSPKR_ICH_3
S
1 2N7002 Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
AC97 CODEC
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 45 of 67
EE2 Thursday, July 31, 2003 10:56:41 am A02 PC8803

 C1423 100PF_50V
1 2
AUDIO_VCC AUDIO_VREF AUDIO_VCC R1426 2
1
C6042 100K_5%
AUDIO_VREF
C23
1 1 C4 1
2 2 U1 2
4 0.1UF_16V
1 C6 12 +
PHONE_AMP 45-
2 45- 14 MIC1
C40 0.22UF_K_10V R30 OUT
46- 1 2 13 -
EXT_MIC1 MAX4492AUD
4 1 2 10K_5% 100PF_50V
5 + U1 11
C41 4700PF 1 R31 2 0.01UF_16V
OUT 7
46-
0.01UF_16V INT_MIC_SW
6 - 1 2 100K_5%
MAX4492AUD 1 C8
11
2 OPEN C42 R32 C25 100PF_50V
4700PF 1 2
1 2 100K_5% 1 2
1 R35 2
AUDIO_VREF AUDIO_VCC 100K_5%
1 C7
1 2 OPEN C6043
R34
0_5%
1
2
2 U1
4
59-,54- C24 1 R36 2 10 +
PHONE 45-
1 2 OPEN OUT 8 MIC2
OPEN 46- C43 0.22UF_K_10V 2 R33 1 9 -
EXT_MIC2 MAX4492AUD
1 2 10K_5% 100PF_50V 11

AUDIO_VCC

1 1
R25 R24
C22 680PF_50V 470_5% 470_5%
1 2 2 2

1 R29 2
AUDIO_VCC 100K_5%
AUDIO_VREF

C6041 1 C1441 1 1 1 C1442

1 C3 R1442 R1443
C5 2 4.7UF_K_6.3V 3.92K_1% 3.9K_1% 2 4.7UF_K_6.3V
1 1 2 0.1UF_16V
46- 0.01UF_16V 2 2
INT_MIC_CN 2 2
AUDIO_VCC OPEN 4
3 + U1
1 46-
R27 R26 C21 R28 OUT INT_MIC 1 C1440
1 2 1 2 1 2 2 -
MAX4492AUD
3K_5% 3K_5% 1 2 10K_5% 2 470PF_50V
0.22UF_16V 11
1 C19
JACKGND
2 1UF_10V
1 C1443
2 470PF_50V
1 JACK1
46- L1034
EXT_MIC1 1 2 2
BLM21A121S 6
46- L1033
EXT_MIC2
1 2 3
46- BLM21A121S 4
INT_MIC_SW
5
46- 7
INT_MIC JA9033L_1F0
8

CN3
3 G 1 1 46-
INT_MIC_CN
4 G 2 2
JST_BM2B_SRSS

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
EQ&MIC JACK
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 46 of 67
EE2 Friday, August 15, 2003 1:50:14 pm A02 PC8803

 LAYOUT NOTES : C1568 C1973 C1565 CLOSE TO PIN 6

R1446 2 OPEN LAYOUT NOTES : C1971 C1972 C1566 CLOSE T0 PIN 15

1
+V5

C1448 C1424 C1429

1 C1447 1 C1451 C1449 C1450
1 1 1 1 1

U1042 2 2 2 2 2 150UF_10V
C6017 1UF_10V 0.1UF_16V
C9 0.047UF_16V 4.7UF_K_6.3V 4.7UF_K_6.3V 1000PF_0402 0.1UF_16V 150UF_10V
45- 1 R1447 2 0_5% 1 2 5 LIN- 16
A_LEFT VDD
1 2 9 LIN+ PVDD 15
C1425 1 PVDD 6
19
SHUTDOWN#
0.47UF_10V2
2 1 C1427 10 BYPASS
2 1 C1426
1UF_16V
LOUT- 8 47-
SPK_OUT_L-
10UF_K_6.3V
LOUT+ 4 47-
SPK_OUT_L+
A_RIGHT 45- C1452 1R1450 2 C6018 1UF_10V 17
RIN- INTERNAL SPEAKER
+V3A 1 2 1 2 7 RIN+ 14 47-
0_5%
0.047UF_16V ROUT- 18 SPK_OUT_R-
ROUT+ 47- SPK_OUT_R+
CN1005
GND 20 (LEFT) 1
R1451 2 GAIN0 13
GND 11 SPK_OUT_L- 47- 1

2
3 47- 2 2
59-,45-,40-,38-,13-,12-,9-,7- 1 5 U1040 1 C1428 12 GAIN1 GND 1 SPK_OUT_L+ 3 3
SLP_S3#_3R 0.47UF_10V NC GND
4 2 4 4
C34 1 1 C35
2 +V5 TI_TPA6017A2_PWP_20P

1
TC7S08F OPEN 100PF_50V 2 2 MLX_53398_0490
3 100PF_50V

+V3A R10
1 2

OPEN
U1041 R9 +V5
1 2

SHUTDOWN 38- 1 5 4 0_5%

1 R1465 2
59-,45- 2
EAPD TC7S02F 1 R1449 2
0_5% 3
0_5% (RIGHT)
2

R1463 R1448 2
1 47-
SPK_OUT_R-
OPEN 47-
OPEN SPK_OUT_R+
1

C36
1 1 C37

100PF_50V 2 2 100PF_50V

AUDIO_VCC

2
R55
AUDIO_VCC
100K_5%

1
1
R57
EARPHONE 100K_5%
PR_HPSENSE# 57-
2 R58
1 2
C33
1
100K_5% AUDIO_VCC
2 OPEN

2
57- PR_AOUTL Q1056 5 R1461
LACATE AT JACK 1 S1
LACATE IN AUDIO G1 100K_5%

1
1 JACK2 6 45-
C1446 R1445 2 L1035 D1 HPSENSE
D2 4
45- 1 1 2 2
HPL
1 150UF_10V 33 BLM11A121S 6 3 G2
3 2
C1 R2 L1 S2
HPR 45- 1 2 1 2 4 C6019
NDC7002N

1
1 33 BLM11A121S 5
150UF_10V
7

2
8 JA9033L_1F0 1UF_10V
1 1 1 C1445 1 C2
R3 R1444 2 470PF_50V2 470PF_50V 57-
1K_1% 1K_1% PR_AOUTR
2 2 JACKGND
C6040
1 2 Engineer
0.01UF_16V David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
AUDIO AMP & HP JACK
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 47 of 67
EE2 Wednesday, August 13, 2003 10:34:34 pm A02 PC8803

 +V3S

CN7 U1025 5 1 42-

R146 2 HDD_RESET#
1 1 1 4
2 2 2 55-,37-,29-,21-
33_5% PCI_RESET1#_3
3 3 PDD(7) TC7S08F
4 3
4 PDD(8)
5 5 PDD(6)
6 6 PDD(9)
7 7 PDD(5) 38-
8 PDD(15:0)
8 PDD(10)
9 9 PDD(4)
10 10 PDD(11)
11 11 PDD(3)
12 12 PDD(12)
13 13 PDD(2)
14 14 PDD(13)
15 15 PDD(1)
16 16 PDD(14)
17 17 PDD(0)
18 18 PDD(15)
19 19
20 20 +V3S
21 21 38-
22 PDDRQ_35 1 R165 2
22
23 23 38- 4.7K_5%
24 PDIOW#_3
24
25 25 38-
26 PDIOR#_3
26
27 27 38-
28 2 470_5%
PDIORDY_35
28 R166 1
29 29 38-
30 PDDACK#_35
30
31 31 37-
32 IRQ14_3
32
33 33 PDA(1) 38-
34 PDA(2:0)
34
35 35 PDA(0)
36 36 PDA(2)
37 37 38-
38 38 38- PDCS1#_3
39 59-,48- PDCS3#_3
39 HDDASP#_5 +V5S
40 40
41 41
42 42 (20/5)
43 43
44 44 1 C1333 1 C1327
2 2 0.1UF_16V 1 C6028 1 C6029 1 C1332 LAYOUT NOTES : THE WIDTH NEED 20 MILS
SYN_200227MB044S414ZA_44P 2 180PF_50V 2 180PF_50V 2 1000PF_0402

0.1UF_16V +V5S

1
R1587
47K_5%
2
HDDASP#_5 59-,48-

+V5S

1
+V5S
R1291
47K_5%

49-,42-
2
1 5 U1016
MTR0#_3
4 59- MBLED#_3
MBDASP#_5 49- 2
TC7S08F
3

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
HDD CONN
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 48 of 67
EE2 Thursday, July 31, 2003 10:57:01 am A02 PC8803

 +V5S_MB

+V5S
1 R200 2 38-,49-
C1285 SDIORDY_35
4.7K_5%
1
+V5S_MB
49-
2 0.1UF_16V
IRQ15_3R 3 D Q1027 +V5S_MB
0.1UF_16V
G 2
C1315 C1316(20/5)
S
1 NDS7002A SDD(15:0)
38- CN11 1 1
SDD(15) 18 SD15 VCC_LOGIC 41 2 2
16 0.1UF_16V
IRQ15_3 37- SDD(14) SD14 VCC_MOTOR 42
SDD(13) 14 SD13 VCC 49
SDD(12) 12 SD12 GND 19
SDD(11) 10 SD11 GND 22
SDD(10) 8 SD10 GND 24 +V5S 1
SDD(9) 6 SD9 GND 26
4 R1239
SDD(8) SD8 MPBID0 52 10K_5%
SDD(7) 3 SD7
5 38-
SDD(6) SD6 DMARQ 21 38-,49- SDDRQ_35 C1283 2
SDD(5) 7 SD5 IORDY 27 SDIORDY_35
9 1
CSEL 28
SDD(4) 1 R201 2
SD4 38-
+V3S SDD(3) 11 SD3 DMACK 29 SDDACK#_35
470_5% 2
13 48- 0.1UF_16V
+V3A SDD(2) SD2 DASP# 39 38- MBDASP#_5
SDD(1) 15 SD1 CS1# 38 SDCS3#_3
17 38- U1013 5 U1013 5
SDD(0) SD0 CS0# 37 SDCS1#_3 1 R1238 2
6 R1237 2 4
RST# 1 1 3
38- 1
1 1 SDA(2:0) 38-
SDA(2) 36 SA2 IOW# 23 SDIOW#_3 33_5% 1K_5%
R1280 R42 33 38- C1284
10K_5% 10K_5%
SDA(1) SA1 IOR# 25 49- SDIOR#_3 2 2 1
SDA(0) 35 SA0 IRQ 31 IRQ15_3R FAIR_NC7WZ17_SC70_6P FAIR_NC7WZ17_SC70_6P
42-
2 2 PDIAG# 34 2 0.1UF_16V
MB_FDD_IDE# 20 MPBID1
38-,49- 58 45-
MBAY_ATTACHED# MPBID2 LOUT 44 A_CD_L
45-
32 NC LRTN 45 A_CD_GND
RRTN 46 45-
FE_RDATA#_5
42-,49- 66 RDATA ROUT 47 A_CD_R +V5S
FE_WPROT#_5
42-,49- 64 WRPRO#
DRVDEN0_3 42- 55 DEN0 GND 2
53 MID0 GND 60
62 R136
GND 63
42-,49- 42-,49- 1 2
FE_TRK0#_5 TRK0# FE_WPROT#_5
WGATE#_3 42- 61 WGATE# GND 65 330_5%
42- 59 WDATA GND 30
WDATA#_3
57 3 D Q1026
STEP#_3 42-
STEP# GND 40 RS2
HDSEL#_3 42- 68 HDSEL# GND 43 G 2 42- MB_RESET FE_RDATA#_5
42-,49- 4 5
DIR#_3 42- 56 DIR S FE_DSKCHG#_5
42-,49- 1 8
MTR0#_3 48-,42- 54 MOTORON# GND 67 1 NDS7002A FE_INDEX#_5
42-,49- 2 7
FE_DSKCHG#_5
42-,49- 51 DCHANGE# G 69 FE_TRK0#_5
42-,49- 3 6
DS0#_3 42- 50 DS0#
FE_INDEX#_5
42-,49- 48 INDEX# 1K
70 G

MLX_SD_87537_6873_68P
+V5A

C183
1
(20/5)
22UF_10V

+V5A Q4
4 S D 1
2 +V5S_MB
5

LAYOUT NOTES : R215

1 1
R198
1 R199

220K_5%
2 3 G
6
FDC638P
(20/5) NFM41R11C223
L1006 1 2
(20/5)

C1313
470K_5% 47K_5% 4 3
1 C184 1 C1314 1
2 2 2 0.047UF_16V 2 0.1UF_16V 2 10UF_K_6.3V 1

R197
38-,49- 100_5%
MBAY_ATTACHED#
2
2

D1020 Q8 6
2 D1
G1 Q5 3
1
3

S1 D

BAT54C 2G
S2 4
1

S
5
G2 NDS7002A 1
SLP_S3_5R 32-,13- 1 D2 3
R1240 FDG6301N
100K_5%
2

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
MULTIBAY CONN
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 49 of 67
EE2 Thursday, July 31, 2003 10:57:06 am A02 PC8803

 USBVCC1
+V5A
U3
(20/5) (20/5)
7 VIN VOUT 8
5 VIN VOUT 6 C69
1 C1414 1 1 C1394 1 C1393
2 OC# R79
2 0.01UF +V5 ILIM 4 1 2
2 0.1UF_16V 2 1UF_10V
150UF_6.3V_S18_METAL
1 EN 115_1%
GND 3
MIC_MIC2545A_1BM_SOP_8P

L1030
38- 1 2 USB_PN1_B
USB_PN1

38- 4 3 USB_PP1_B
USB_PP1
DLW21SN900SQ2L CN1
1 VCC 9
GND
2 D- GND 10
3 D+
4
5 GND
6 VCC
7 D-
8 D+
GND
SYN_020122MR008SX20ZU_8P+2G

USBVCC0

U2
+V5A (20/5) (20/5)
7 VIN VOUT 8
5 VIN VOUT 6 C20
1 1 C39 1 C38
2 OC# R80
+V5 ILIM 4 1 2
2 0.1UF_16V 2 1UF_10V
150UF_6.3V_S18_METAL
1 C1415 1 EN 76.8_1%
GND 3
2 0.01UF
MIC_MIC2545A_1BM_SOP_8P

L1032
38- 1 2 USB_PN0_B
USB_PN0

38- 4 3 USB_PP0_B
USB_PP0
DLW21SN900SQ2L

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
USB&IR CONN
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 50 of 67
EE2 Thursday, July 31, 2003 10:57:19 am A02 PC8803

 C1027 1 C1030 1 C1024 1 C1022 1 C1025 1 C1029 1 C1023 1 C1031 C1026
+V3S 1 1
2 2 2 2 2 2 2 2 2
10UF_10V 0.1UF_16V 0.1UF_16V 0.1UF_16V 0.1UF_16V 0.1UF_16V 0.1UF_16V 10UF_10V
0.1UF_16V
+V3 52- A_CAD(31:0)

A_CAD(31)
A_CAD(30)
A_CAD(29)
A_CAD(28)
A_CAD(27)
A_CAD(26)
A_CAD(25)
A_CAD(24)
A_CAD(23)
A_CAD(22)
A_CAD(21)
A_CAD(20)
A_CAD(19)
A_CAD(18)
A_CAD(17)
A_CAD(16)
A_CAD(15)
A_CAD(14)
A_CAD(13)
A_CAD(12)
A_CAD(11)
A_CAD(10)
A_CAD(9)
A_CAD(8)
A_CAD(7)
A_CAD(6)
A_CAD(5)
A_CAD(4)
A_CAD(3)
A_CAD(2)
A_CAD(1)
A_CAD(0)
C1009 C1010 ACARDVCC
1 1
2 2

10UF_10V 0.1UF_16V

W15
M19
M18
M15
M17

W11
1 C1011 1 C1012

R19

R14
N17
P18

N14
R17

U15
P14
U11
P10
U10
CORE_VCC R10

CORE_VCC B10

L18

V10
AUX_VCC L15

T19
CORE_VCC J18

W9

W7

W6
M6

R9
U9
U8
R8

U7
P9

P8
U6
V7
P5
F2
J5
2 0.1UF_16V 2 10UF_K_6.3V
55-,54-,37-,51-

PCI_VCC
PCI_VCC
PCI_VCC
PCI_VCC

A_CAD31
A_CAD30
A_CAD29
A_CAD28
A_CAD27
A_CAD26
A_CAD25
A_CAD24
A_CAD23
A_CAD22
A_CAD21
A_CAD20
A_CAD19
A_CAD18
A_CAD17
A_CAD16
A_CAD15
A_CAD14
A_CAD13
A_CAD12
A_CAD11
A_CAD10
A_CAD9
A_CAD8
A_CAD7
A_CAD6
A_CAD5
A_CAD4
A_CAD3
A_CAD2
A_CAD1
A_CAD0
PCI_AD(31:0)
A_SKT_VCC R7
PCI_AD(31) E1 AD31 A_SKT_VCC R13
PCI_AD(30) E2 AD30
PCI_AD(29) F3 AD29 A_CC_BE3# N15 52-
F1 A_CCBE3#
PCI_AD(28) AD28 A_CC_BE2# V14 52- A_CCBE2#
PCI_AD(27) G5 AD27 A_CC_BE1# V11 52-
H6 A_CCBE1#
PCI_AD(26) AD26 A_CC_BE0# W8 52- A_CCBE0#
PCI_AD(25) G3 AD25
PCI_AD(24) G2 AD24
PCI_AD(23) H2 AD23 A_CCLK V13 52-
H1 A_CCLK
PCI_AD(22) AD22 A_CFRAME# U14 52- A_CFRAME#
PCI_AD(21) J1 AD21 A_CIRDY# P13 52-
J2 A_CIRDY#
PCI_AD(20) AD20 A_CTRDY# W14 52- A_CTRDY#
PCI_AD(19) J3 AD19 A_CDEVSEL# U13 52- A_CDEVSEL#
PCI_AD(18) J6 AD18 A_CSTOP# W13 52-
K1 A_CSTOP#
PCI_AD(17) AD17 A_CPAR R11 52- A_CPAR
PCI_AD(16) K2 AD16 A_CPERR# V12 52- A_CPERR#
PCI_AD(15) M5 AD15 A_CSERR# R18 52-
N2 A_CSERR#
PCI_AD(14) AD14 A_CREQ# P17 52- A_CREQ#
PCI_AD(13) N1 AD13 A_CGNT# R12 52-
N3 A_CGNT#
PCI_AD(12) AD12 A_CINT# P12 52- A_CINT#
PCI_AD(11) N6 AD11 A_CBLOCK# U12 52- A_CBLOCK#
PCI_AD(10) P1 AD10 A_CCLKRUN# L17 52- A_CCLKRUN#

U2054
PCI_AD(9) P3 AD9 A_CRST# P15 52-
N5 A_CRST#
PCI_AD(8) AD8 A_R2_D2 L19 52- A_D2
PCI_AD(7) P6 AD7 A_R2_D14 V8 52- +V3S
R2 A_D14
PCI_AD(6) AD6 A_R2_A18 P11 52- A_A18
PCI_AD(5) R3 AD5 A_CVS1 W10 52- A_CVS1
PCI_AD(4)
PCI_AD(3)
PCI_AD(2)
T1
W4
R6
AD4
AD3
AD2
O2_OZH31B_MINI_BGA_224P A_CVS2
A_CCD1#
A_CCD2#
W16
V6
L14
52-
52-
52-
A_CVS2
A_CCD1#
A_CCD2# 1 R1004 2 20K_5%
PCI_AD(1) U5 AD1 A_CAUDIO M14 52-
P7 A_CAUDIO
PCI_AD(0) AD0 A_CSTSCHG N19 52- A_CSTSCHG
55-,54-,37- G1 C_BE3# 52-
PCI_CBE#(3)
55-,54-,37- K3 C_BE2# SCLK_A_VCC_5# K14 52-,40-
S_DATA
PCI_CBE#(2) M3 S_CLK
55-,54-,37- C_BE1# SDATA_B_VCC_3# K15
PCI_CBE#(1)
55-,54-,37- R1 C_BE0# SLATCH_B_VCC_5# K17 52-
PCI_CBE#(0) IRQ3_A_VCC_3# W12 S_LATCH
1 R1031 2 100_5% H5 IDSEL IRQ9_A_VPP_VCC_PGM P19
PCI_AD(22) 55-,54-,37-,51- E3 PCI_CLK 1 R1003 2 20K_5%
CLK_CBPCI_3R 15- L3 DEVSEL# B_CSTSCHG F8 52-
PCI_DEVSEL#_3 55-,54-,37- K6 FRAME# B_CAUDIO C8 B_CSTSCHG
PCI_FRAME#_3 55-,54-,37- L1 IRDY# B_CCD2# C6 52- B_CAUDIO
+V3 PCI_IRDY#_3 L2 TRDY# B_CCD2#
55-,54-,37- B_CCD1# J15 52-
PCI_TRDY#_3 55-,54-,37- L5 STOP# B_CVS2 A10 52- B_CCD1#
PCI_STOP#_3 55-,54-,37- M2 PAR B_CVS1 E18 52- B_CVS2
+V5S PCI_PAR_3 L6 B_CVS1
55-,54-,37- PERR# B_R2_A18 C14 52-
PCI_PERR#_3 55-,54-,37- M1 SERR# B_R2_D14 G17 52- B_A18
1 PCI_SERR#_3 55-,54-,40-,37- G6 REQ# B_R2_D2 F7 52- B_D14
R1010 Q6005 3 CBREQ2#_3 F5 B_D2
37- GNT# B_CRST# C10 52-
10K_5% 2G
D
CBGNT2#_3 37- B5 B_CCLKRUN# A5 52- B_CRST#
PIRQC#_3 INTA# B_CCLKRUN#
37- F6 INTB#_IRQ4_A_VPP_PGM B_CBLOCK# A14 52-
2 U1003 S
PIRQD#_3 V5 B_CBLOCK#
PCI_RESET2#_3 1 37- INTC#_LOCK# B_CINT# F12 52-
5 2N7002 PIRQG#_3 37- D1 B_CGNT# E13 52- B_CINT#
RST# B_CGNT#
2 4 59-,54-,42-,40-,37- N18 GRST# B_CREQ# C9 52-
B_CSERR# A9 52- B_CREQ#
TI_SN74LVC1G17DBVR_SOT_5P E6 B_CPERR# A15 52- B_CSERR#
3 IRQ7_B_VPP_PGM_EXT_REQ# B_CPERR#
52- 1 R1008 2 F19 B_CPAR C15 52-
C1014 1 GRST# IRQ10_B_VPP_VCC_PGM_EXT_GNT# B_CPAR
0_5% B_CSTOP# C13 52-
B14 B_CDEVSEL# B13 52- B_CSTOP#
2 PCI_PME#_3 IRQ12_PME# B_CDEVSEL#
55-,54-,37- A4 IRQ14_CLKRUN# B_CTRDY# A13 52-
CLKRUN#_3 59-,55-,54-,42-,40-,38- C5 B_CIRDY# C12 52- B_CTRDY#
SERIRQ_3 IRQ5_SERIRQ# B_CIRDY#
0.01UF_16V
59-,42-,40-,37- V9 IRQ15_RI_OUT# B_CFRAME# B12 52-
K19 B_CCLK E12 52- B_CFRAME#
PCSPKB_3 SPKR_OUT# B_CCLK
45- 52-
J19 LEDO#_SKTA_ACTV B_CC_BE0# G14 52-
E8 IRQ11_SKTB_ACTV B_CC_BE1# A16 B_CCBE0#
SC_RSVD8_SD_DATA1

B_CCBE1#
SC_VCC3#_SD_VCC3#

+V3S B_CC_BE2# A12 52-

B_CCBE2#
SC_RSVD4_SD_WP#

SC_OC#_SD_DATA3

E5 NC B_CC_BE3# F9 52-
SC_DET#_SD_DET#

SC_RST#_SD_CMD

B_CCBE3#
SC_IO_SD_DATA0

SC_VCC_SD_VCC

52-
SC_CLK_SD_CLK

B_SKT_VCC G19 BCARDVCC

B_SKT_VCC F13
B_SKT_VCC E7
MS_VCC3#

SD_DATA2
SC_VCC5#

R1009 2
MS_DET#

B_CAD31
B_CAD30
B_CAD29
B_CAD28
B_CAD27
B_CAD26
B_CAD25
B_CAD24
B_CAD23
B_CAD22
B_CAD21
B_CAD20
B_CAD19
B_CAD18
B_CAD17
B_CAD16
B_CAD15
B_CAD14
B_CAD13
B_CAD12
B_CAD11
B_CAD10
1
MS_SDIO

MS_VCC
MS_CLK

B_CAD9
B_CAD8
B_CAD7
B_CAD6
B_CAD5
B_CAD4
B_CAD3
B_CAD2
B_CAD1
B_CAD0
MS_BS

10K_5% C1007 1 1 C1005

GND
GND
GND
GND
GND
GND
GND

2 2 10UF_K_6.3V
0.1UF_16V
E11

V15
W5
H3
K18

C11
A11
P2

V16

E10

E14

E17
G15
E19

G18

J14
J17
K5

T2
T3

C4

B6
A6
B7
C7
A7
B8
A8

B9
D18

B15

C16

B16

U16
T18
T17
D17

F10
F11

B11

D19
F15

F14

F18
F17

H15
H14
H17
H18
H19
V4

E9
U4

D2
B4

D3

NOTS : U2054 WILL BE OZH31B IN THE FEATURE

B_CAD(31)
B_CAD(30)
B_CAD(29)
B_CAD(28)
B_CAD(27)
B_CAD(26)
B_CAD(25)
B_CAD(24)
B_CAD(23)
B_CAD(22)
B_CAD(21)
B_CAD(20)
B_CAD(19)
B_CAD(18)
B_CAD(17)
B_CAD(16)
B_CAD(15)
B_CAD(14)
B_CAD(13)
B_CAD(12)
B_CAD(11)
SD_CD# B_CAD(10)
B_CAD(9)
B_CAD(8)
B_CAD(7)
B_CAD(6)
B_CAD(5)
B_CAD(4)
B_CAD(3)
B_CAD(2)
B_CAD(1)
B_CAD(0)
53-
SD_DAT0 53-
SD_DAT1 Engineer
SD_WP
SD_CMD
SD_CLK
53-
53-
53-
53-
52- B_CAD(31:0)
David Du
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INVENTEC
SD_DAT2 C1020 R&D CHK Size
53- VCC_SD TITLE
SD_DAT3 53- 1 A3
SD_PWREN# 53-
2 0.1UF_16V
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
CARDBUS CONTROLLER
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 51 of 67
EE2 Thursday, July 31, 2003 10:57:24 am A02 PC8803

 CN18 75
+V12 +V5 +V3 150 GND1 GND9 74
149 GND2 GND10 73
ACARDVPP A_CCD1# 51- 148 51- B_CCD1#
A_CD1# B_CD1# 72
A_CAD(0) 51- 147 51- B_CAD(0)
U1001 A_D3 B_D3 71
A_CAD(2) 51- 146 B_D11 70 51- B_CAD(2)
A_D11
15 3.3V_1 AVPP 8 ACARDVCC A_CAD(1) 51- 145 A_D4 B_D4 69 51- B_CAD(1)
16 3.3V_2 AVCC_1 9 A_CAD(4) 51- 144 A_D12 B_D12 68 51- B_CAD(4)
17 3.3V_3 AVCC_2 10 A_CAD(3) 51- 143 A_D5 B_D5 67 51- B_CAD(3)
1 5V_1 AVCC_3 11 142 GND3 GND11 66
2 5V_2 BCARDVCC A_CAD(6) 51- 141 B_D13 65 51- B_CAD(6)
A_D13
30 5V_3 BVCC_1 20 BCARDVPP A_CAD(5) 51- 140 A_D6 B_D6 64 51- B_CAD(5)
7 12V_1 BVCC_2 21 A_D14 51- 139 A_D14 B_D14 63 51- B_D14
24 12V_2 BVCC_3 22 A_CAD(7) 51- 138 A_D7 B_D7 62 51- B_CAD(7)
BVPP 23 A_CAD(8) 51- 137 A_D15 B_D15 61 51- B_CAD(8)
6 RESET A_CCBE0# 51- 136 A_CE1# B_CE1# 60 51- B_CCBE0#
GRST# 51- 14 RESET# NC_2 25 A_CAD(10) 51- 135 B_CE2# 59 51- B_CAD(10)
NC_3 A_CE2#
26 134 GND4 GND12 58
S_DATA 51- 3 DATA NC_4 27 +V3 A_CAD(9) 51- 133 A_A10 B_A10 57 51- B_CAD(9)
S_CLK 51-,40- 4 CLOCK NC_5 28 A_CVS1 51- 132 B_RFSH 56 51- B_CVS1
C1001 A_RFSH
S_LATCH 51- 5 LATCH A_CAD(11) 51- 131 A_OE# B_OE# 55 51- B_CAD(11)
NC_6 29 1 R1002 2 1 C1002 1 C1006 1 51- 130 51-
A_CAD(13) A_IORD# B_IORD# 54 B_CAD(13)
19 NC OPEN 2 0.1UF_16V2 0.1UF_16V2 4.7UF_K_25V A_CAD(12) 51- 129 B_A11 53 51- B_CAD(12)
A_A11
13 NC_1 GND 12 A_CAD(15) 51- 128 A_IOWR# B_IOWR# 52 51- B_CAD(15)
18 OC# A_CAD(14) 51- 127 A_A9 B_A9 51 51- B_CAD(14)
126 GND5 GND13 50
O2_OZ2206_SSOP_30P A_CAD(16) 51- 125 51- B_CAD(16)
A_A17 B_A17 49
A_CCBE1# 51- 124 51- B_CCBE1#
A_A8 B_A8 48
A_A18 51- 123 B_A18 47 51- B_A18
C1004 A_A18
ACARDVCC A_CPAR 51- 122 51- B_CPAR
1 C1094 1 C1098 1 ACARDVPP A_A13 B_A13 46
NOTES: U2055 WILL BE OZ2216S IN THE FEATURE A_CBLOCK# 51- 121 A_A19 B_A19 45 51- B_CBLOCK#
2 0.1UF_16V 2 0.1UF_16V 2 4.7UF_K_25V A_CPERR# 51-,52- 120 A_A14 B_A14 44 51-,52- B_CPERR# BCARDVCC BCARDVPP
A_CSTOP# 51-,52- 119 51-,52- B_CSTOP#
C1008 A_A20 B_A20 43
118 GND6 GND14 42
1 C1096 1 C1097 1 51- 117 51-
A_CGNT# A_WE# B_WE# 41 B_CGNT#
2 0.1UF_16V2 0.1UF_16V2 4.7UF_K_25V A_CDEVSEL# 51-,52- 116 51-,52- B_CDEVSEL#
A_A21 B_A21 40
A_CINT# 51-,52- 115 51-,52- B_CINT#
A_RDY_BSY# B_RDY_BSY#
114 39
A_VCC B_VCC 38
113 A_NONE B_NONE 37
R1132 2 112 A_VPP1_VPP2 B_VPP1_VPP2 R1133 2
51- 1 111 36 1 51-
A_CCLK A_A16 B_A16 35 B_CCLK
A_CTRDY# 51- 110 51- B_CTRDY#
10_5% A_A22 B_A22 34 10_5%
A_CIRDY# 51- 109 51- B_CIRDY#
A_A15 B_A15 33
108 GND24 GND15 32
C1013 51- 107 51-
1 C1095 1 C289 1 A_CFRAME# A_A23 B_A23 31 B_CFRAME#
A_CCBE2# 51- 106 A_A12 B_A12 30 51- B_CCBE2#
2 0.1UF_16V 2 0.1UF_16V A_CAD(17) 51- 105 51- B_CAD(17)
2 4.7UF_K_25V A_A24 B_A24 29
A_CAD(18) 51- 104 51- B_CAD(18)
A_A7 B_A7 28
A_CAD(19) 51- 103 A_A25 B_A25 27 51- B_CAD(19)
A_CAD(20) 51- 102 51- B_CAD(20)
A_A6 B_A6 26
A_CVS2 51- 101 51- B_CVS2
A_RFU B_RFU 25
100 GND23 GND16 24
A_CAD(21) 51- 99 51- B_CAD(21)
A_A5 B_A5 23
A_CRST# 51- 98 51- B_CRST#
A_RESET B_RESET 22
A_CAD(22) 51- 97 51- B_CAD(22)
A_A4 B_A4 21
A_CSERR# 51-,52- 96 51-,52- B_CSERR#
A_WAIT# B_WAIT# 20
A_CAD(23) 51- 95 51- B_CAD(23)
A_A3 B_A3 19
A_CREQ# 51-,52- 94 51-,52- B_CREQ#
A_INPACK# B_INPACK#
51- 93 18 51-
A_CAD(24) A_A2 B_A2 17 B_CAD(24)
ACARDVCC BCARDVCC 92 GND21 GND17 16
A_CCBE3# 51- 91 51- B_CCBE3#
A_REG# B_REG# 15
A_CAD(25) 51- 90 51- B_CAD(25)
A_A1 B_A1 14
A_CAUDIO 51-,52- 89 51-,52- B_CAUDIO
A_BVD2 B_BVD2 13
A_CAD(26) 51- 88 51- B_CAD(26)
A_A0 B_A0 12
A_CSTSCHG 51- 87 51- B_CSTSCHG
R1131 2 R1110 2 A_BVD1 B_BVD1 11
51-,52- 1 51-,52- 1 51- 86 51-
A_CSERR# B_CSERR# A_CAD(27) A_D0 B_D0 10 B_CAD(27)
A_CAD(28) 51- 85 51- B_CAD(28)
22K_5% 22K_5% A_D8 B_D8 9
84 GND7 GND18 8
51-,52- 1 R1130 2 51-,52- 1 R1109 2 51- 83 51-
A_CREQ# B_CREQ# A_CAD(29) A_D1 B_D1 7 B_CAD(29)
A_CAD(30) 51- 82 51- B_CAD(30)
22K_5% 22K_5% A_D9 B_D9 6
A_D2 51- 81 51- B_D2
R1129 2 R1108 2 A_D2 B_D2 5
51-,52- 1 51-,52- 1 51- 80 51-
A_CAUDIO B_CAUDIO A_CAD(31) A_D10 B_D10 4 B_CAD(31)
A_CCLKRUN# 51-,52- 79 51-,52- B_CCLKRUN#
OPEN OPEN A_WP B_WP 3
A_CCD2# 51- 78 51- B_CCD2#
R1135 2 R1113 2 A_CD2# B_CD2# 2
51-,52- 1 51-,52- 1 77
A_CDEVSEL# B_CDEVSEL# GND8 GND22 1
22K_5% 22K_5% 76 GND26 GND19
51-,52- 1 R1136 2 51-,52- 1 R1114 2 153 155
A_CSTOP# B_CSTOP# GND27 GND29 156
22K_5% 22K_5% 154 GND28 GND30 G17
G1
1 R1137 2 R1115 2 G1 G17 G18
A_CPERR# 51-,52- B_CPERR# 51-,52- 1 G2 G2 G18 G19
22K_5% 22K_5% G3 G3 G19 G20
G4
R1134 2 R1112 2 G4 G20 G21
A_CINT# 51-,52- 1
B_CINT# 51-,52- 1 G5 G5 G21 G22
22K_5% 22K_5% G6 G6 G22 G23
G7 G7 Screw G23 G24
51-,52- 1 R1127 2 51-,52- 1 R1107 2 G8
A_CCLKRUN# B_CCLKRUN# G8 G24 G25
22K_5% 22K_5% G9 G9 Ground G25 G26
G10 G10 G26 G27
G11 G11 G27 G28
G12
G12 G28 G29
G13 G13 G29 G30
G14 G14 G30 G31
G15 Engineer
G15 G31 G32
G16 G16

AMP_C97_25852_EMI
G32 David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
PC CARD SLOT
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 52 of 67
EE2 Thursday, July 31, 2003 10:57:30 am A02 PC8803

 +V3 VCC_SD

Q1000
4 S D 1
2
5
3 G
6
C1017
1 FDC638P
1 C1018 1 C1019 1 C1021
2 10UF_K_6.3V
2 0.01UF_16V 2 0.01UF_16V 2 2.2UF_K_10V

+V3 1
R1025
47K_5%
2

+V3
5 U1005 VCC_SD
1
4
SD_PWREN# 51- 2
3 NC7SZ08M5 1 1 1 1
+V3 1 1 1
R1028 R1029 R1034 R1007
47K_5% 47K_5% 47K_5% 47K_5% R1027 R1033 R1032
47K_5% 47K_5% 47K_5%
2 2 2 2
2 2 2
U1004 5
SD_WP 51- 6 1 CN1000
13 WP GND 14
NC7WZ14 10 GND 11
2 CD 12
SD_DAT3 51- 1 CD_DAT3 GND
51- 2 DAT2 9 51-
SD_CMD CMD 8 SD_DAT2
3 DAT1 51- SD_DAT1
VSS1 7
4 VDD DAT0 51- SD_DAT0
51- 1 R1030 2 5 VSS2 6
+V3 SD_CLK CLK
10_5%
MLX_54786_0991_14P
1 C1028
U1004 5
2 10PF
SD_CD# 51- 4 3

2 NC7WZ14

Engineer
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TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
SD CARD CONN
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 53 of 67
EE2 Thursday, July 31, 2003 10:57:35 am A02 PC8803

 +V3

+V3 +V5S +V3

1 C1061 1 C1076 1 C1079 1 C1062

LAYOUT NOTES : +V3 15~20 mil
2 2 2 2
0.1UF_16V
1 C1078 1 C1075 1 C1063 1 C1080 1 C1077 1 C1081
0.1UF_16V 0.1UF_16V 0.1UF_16V
2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V
2 0.1UF_16V
2 0.1UF_16V

55-,51-,37-,54-
PCI_AD(31:0) CN1001
2 RING TIP 1
4 8PMJ-1 8PMJ-3 3
6 8PMJ-2 8PMJ-6 5
8 8PMJ-4 8PMJ-7 7
10 8PMJ-5 8PMJ-8 9
12 LED2_YELP LED1_GRNP 11 59- LED_WLAN_LINK
14 LED2_YELN LED1_GRNN 13 58-,40-
16 15 XMIT_OFF#
RESERVED_0 CHSGND
18 5V_0 INTB# 17 37-,54- PIRQF#_3
PIRQF#_3 37-,54- 20 INTA# 3.3V_0 19
22 RESERVED_1 RESERVED_2 21
24 3.3VAUX_0 GROUND_0 23
15-
PCI_RESET2#_3 59-,51-,42-,40-,37- 26 RST# CLK 25 CLK_MINIPCI_3R
Q1009 28 3.3V_1 GROUND_1 27
37- R1072 30 29 37-
MPCIGNT0#_3 GNT# REQ# MPCIREQ0#_3
1 2 32 GROUND_2 3.3V_2 31
55-,51-,37- 3 1 34 33 PCI_AD(31)
PCI_PME#_3 PME# AD31
D S
OPEN 36 RESERVED_3 AD29 35 PCI_AD(29)
NDS7002A PCI_AD(30) 38 AD30 GROUND_3 37
G 1 40 39
2 3.3V_3 AD27 PCI_AD(27)
+V3 R1069 PCI_AD(28) 42 AD28 AD25 41 PCI_AD(25)
47K_5% CH_CLK 58- PCI_AD(26) 44 AD26 RESERVED_4 43 58- CH_DATA
PCI_AD(24) 46 AD24 C_BE3# 45
2
48 IDSEL AD23 47 PCI_AD(23)
50 GROUND_4 GROUND_5 49
PCI_AD(22) 52 AD22 AD21 51 PCI_AD(21) 55-,51-,37- PCI_CBE#(3)
55-,51-,37-,54- 1 R1111 2 PCI_AD(20) 54 53 PCI_AD(19)
PCI_AD(20) AD20 AD19
56 PAR GROUND_6 55
100_5% PCI_AD(18) 58 57 PCI_AD(17)
AD18 AD17
PCI_AD(16) 60 AD16 C_BE2# 59 55-,51-,37- PCI_CBE#(2)
55-,51-,37- 62 GROUND_7 IRDY# 61 55-,51-,37- PCI_IRDY#_3
PCI_PAR_3 55-,51-,37- 64 63
PCI_FRAME#_3 FRAME# 3.3V_4
55-,51-,37- 66 TRDY# CLKRUN# 65 59-,55-,51-,42-,40-,38- CLKRUN#_3
PCI_TRDY#_3 55-,51-,37- 68 67 55-,51-,40-,37-
PCI_STOP#_3 STOP# SERR# PCI_SERR#_3
70 3.3V_5 GROUND_8 69 55-,51-,37-
PCI_PERR#_3
55-,51-,37- 72 DEVSEL# PERR# 71 55-,51-,37- PCI_CBE#(1)
PCI_DEVSEL#_3 74 73
GROUND_9 C_BE1#
PCI_AD(15) 76 AD15 AD14 75 PCI_AD(14)
PCI_AD(13) 78 AD13 GROUND_10 77
PCI_AD(11) 80 AD11 AD12 79 PCI_AD(12)
82 GROUND_11 AD10 81 PCI_AD(10)
PCI_AD(9) 84 AD09 GROUND_12 83
55-,51-,37- 86 C_BE0# AD08 85 PCI_AD(8)
PCI_CBE#(0) 88 87 PCI_AD(7)
3.3V_6 AD07
PCI_AD(6) 90 AD06 3.3V_7 89
PCI_AD(4) 92 AD04 AD05 91 PCI_AD(5)
PCI_AD(2) 94 AD02 RESERVED_5 93 +V5S
PCI_AD(0) 96 AD00 AD03 95 PCI_AD(3)
98 RESERVED_WIP5_0 5V_1 97
100 RESERVED_WIP5_1 AD01 99 PCI_AD(1)
102 101
GROUND_13 GROUND_14 103
104 M66EN AC_SYNC
106 105
AC_SDATA_OUT AC_SDATA_IN 107
108 AC_CODEC_ID0# AC_BIT_CLK
110 109
AC_RESET# AC_CODEC_ID1#
112 111 45-
RESERVED_6 MOD_AUDIO_MON 113 MPCI_PWM
114 GROUND_15 AUDIO_GND 115 1
59-,46- 116 SYS_AUDIO_IN SYS_AUDIO_OUT 45-
PHONE 118 117 A_MPCI_IN
SYS_AUDIO_IN_GND
SYS_AUDIO_OUT_GND 119 R1090
120 AUDIO_GND_0 AUDIO_GND_1 8.2K_5%
122 121
+V3S MPCIACT# RESERVED_7 2
124 123
3.3VAUX_1 VCC5VA +V5S
1 R1116 2 146 G2 G1 145
10K_5%
148 G4 G3 147 1 L1002 2
+V3 BLM21B121SD

AMP_1318228_1_124P

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
MINIPCI CONN
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 54 of 67
EE2 Thursday, July 31, 2003 10:57:40 am A02 PC8803

 +V3S

PCI_AD(0:31) 51-,54-,37-,55- U1024

PCI_AD(0) N7 A7
AD00 VDDIO_PCI10
PCI_AD(1) M7 AD01 VDDIO_PCI01 E1
PCI_AD(2) P6 P2 1 C1358 1 C1357 1 C110 1 C108 1 C93 1 C1471 1 C317 1 C318
AD02 VDDIO_PCI03
PCI_AD(3) P5 G1 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V2 10UF_K_6.3V 2 0.1UF_16V 2 0.1UF_16V
AD03 VDDIO_PCI02
PCI_AD(4) N5 AD04 VDDIO_PCI07 C5
PCI_AD(5) M5 AD05 VDDIO_PCI08 N6
PCI_AD(6) P4 E4
AD06 VDDIO_PCI09
PCI_AD(7) N4 AD07 VDDIO_PCI04 B3 +V3_LAN
PCI_AD(8) P3 AD08 VDDIO_PCI05 K3
PCI_AD(9) N3 L4
AD09 VDDIO_PCI06
PCI_AD(10) N2 AD10
PCI_AD(11) M1 AD11 VDDIO_01 A11
PCI_AD(12) M2 AD12 VDDIO_02 F11
PCI_AD(13) M3 K12 1 C1398 1 C103 1 C104 1 C1470 1 C319
AD13 VDDIO_03
PCI_AD(14) L1 L12 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V2 10UF_K_6.3V 2 0.1UF_16V
AD14 VDDIO_04
PCI_AD(15) L2 AD15
PCI_AD(16) K1 AD16
PCI_AD(17) E3
AD17
PCI_AD(18) D1 AD18
PCI_AD(19) D2 AD19 REGSUP25 B11
PCI_AD(20) D3 C11
AD20 REGCTL25
PCI_AD(21) C1 AD21 REGSEN25 C10
PCI_AD(22) B1 AD22
PCI_AD(23) B2
AD23
PCI_AD(24) B4 AD24
PCI_AD(25) A5 AD25
PCI_AD(26) B5 +V3S +V3_LAN
AD26
PCI_AD(27) B6 AD27 REGSUP12 B9
PCI_AD(28) C6 AD28 REGCTL12 B10
PCI_AD(29) C7 A9
AD29 REGSEN12
PCI_AD(30) A8 AD30
PCI_AD(31) B8 1 C109 1 C73
AD31
2 0.1UF_10V 2 0.1UF_10V
PCI_CBE#(0:3) 54-,51-,37-
VESD_1 P1
PCI_CBE#(0) M4 G2 +V3A
CBE0# VESD_2
PCI_CBE#(1) L3 CBE1# VESD_3 A1
PCI_CBE#(2) F3 CBE2#
PCI_CBE#(3) C4 1 R95 2 1 R96 2 U1034 +V3_LAN
CBE3# 5 4
EEDATA P10 4.7K_5% 4.7K_5%
6 SDA GND 3 Q1037
PCI_PAR_3 54-,51-,37- J1 PAR EECLK M10 1 R97 2 7 SCL A2 2 4 S D 1 1 L1017 2
R1357 2
A4 IDSEL 8 WP A1 1 2
GPIO0 H12
54-,51-,37-,55- 1 1K_5% BLM21B121SD
PCI_AD(30) VCC A0 5 1
CLK_NICPCI_3R 15- 100_5% A3 PCI_CLK GPIO1 K13
J13 3 G
6 1 C71 1 C72 1 C1355 R1350
GPIO2 ATM_AT24C64A_SOIC_8P 100_5%
FDC638P 2 0.1UF_10V 2 0.1UF_10V 2 10UF_K_6.3V
PIRQE#_3 37- H2 INTA# 2
PCI_RESET1#_3 48-,37-,29-,21- C2 L14
PCI_RST# NC_01
NICGNT1#_3 37- J3 GNT# NC_02 J11
NICREQ1#_3 37- C3 REQ# NC_03 L11
PCI_FRAME#_3 54-,51-,37- F2 FRAME#
PCI_IRDY#_3 54-,51-,37- F1 IRDY#
+V3_LAN PCI_TRDY#_3 54-,51-,37- G3 TRDY# MAC_PLLVDD3 P7 +V3 +V3A 1
PCI_DEVSEL#_3 54-,51-,37- H3 DEVSEL# MAC_PLL_VSS M6
54-,51-,37- H1 R1352
PCI_STOP#_3 STOP# 220K_5%
PCI_PERR#_3 54-,51-,37- J2 59-,9-,55- LAN_ON_3
PERR#
PCI_SERR#_3 54-,51-,40-,37- A2 SERR# 1 5 U1022
2
C12 1 R132 2 4 15 Q1036 3
TCK R6034 2 D
R1353 B12 TP554
OPEN AIRACIN 57-,5- 1 2 4 G
100K_5% A10 TDO U1021
1 2
SMB_CLK TMS A12 TP555
OPEN 3 2
R1354 1 2 100K_5% C9 SMB_DATA D11 1 R133 2 TC7S32F NC7SZ00M5 2
S

TRST# R6033 2 3 1
D12 TP556
4.7K_5% AIRACIN2 40- 1
R109 2 TDI NDS7002A
1 J12 VAUX_PRSNT 0_5%
4.7K_5% F4 M66EN VSS_01 N1
A6 E2
R13552 PME# VSS_02
1
VSS_21 F8
OPEN VSS_19 D8
G8
3 1 VSS_22
PCI_PME#_3 54-,51-,37- VSS_20 E8
D

Q1038 VSS_23 D9
VSS_24 E9
G

2 NDS7002A VSS_25 F9
D1024 1N4148 D4
VSS_04
1 2 VSS_03 K2
59-,9-,55-
R1358
1 2 G6
LAN_ON_3 VSS_13
1M_5% L6
1 C1356 VSS_14
VSS_15 D7
2 3300PF_50V VSS_05 G4
D5
VSS_06
VSS_07 E5
VSS_08 F5
G5
VSS_09
VSS_10 D6
VSS_11 E6
F6
VSS_12
VSS_18 G7
VSS_16 E7
F7
VSS_17

SO G11
SI E10
SCLK E11
J4 H11 +V2.5_LAN
NC_04 CS#
+V2.5L
CLKRUN#_3 59-,54-,51-,42-,40-,38- H4
CLK_RUN# L1020
K4 VDDP_01 P11 2 1
NC_06 VDDP_02 L13 1 C100 1 C87 1 C88
BLM11A601S
K14 Engineer
VDDP_03
L7
NC_07 2 0.01UF_16V 2 0.01UF_16V 2 0.1UF_16V David Du
Drawn by
David Du
INVENTEC
BCM_BCM5705M_BGA_196P R&D CHK
TITLE
Size
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
LAN INTERFACE-1
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 55 of 67
EE2 Thursday, July 31, 2003 10:57:45 am A02 PC8803

 +V_LAN

1 L1021 2
BLM11A601S
1 C102 1 C1374
2 0.1UF_16V 2 0.1UF_16V

+V2.5_LAN
+V1.2L
1 L1016 2
BLM11A601S
1 L1022 2
BLM11A601S
1 L1026 2
BLM41P800S 1 C1354 1 C1376
2 0.1UF_16V 2 0.1UF_16V
+V2.5_LAN
+V_LAN

+V3S
U1024
K5
VDDC_03 AVDDL_01 F12 1 1 1 1 1 1 1 1
L5 F13

49.9_1%

49.9_1%

49.9_1%

49.9_1%

49.9_1%

49.9_1%

49.9_1%

49.9_1%
VDDC_04 AVDDL_02

R1377

R1376

R1374

R1375

R1348

R1349

R1346

R1347
C1378 H6
1 1 C91 1 C92 1 C106 1 C1379 1 C320 1 C321 VDDC_05
J6 VDDC_06
2 10UF_K_6.3V2 0.1UF_16V2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V2 0.1UF_16V K6 A13
VDDC_07 AVDD_01 2 2 2 2 2 2 2 2
H7 VDDC_08 AVDD_02 F14 CN4
J7 U9
VDDC_09 Y1 Y2 10
K7 VDDC_10 1 TCT1 MCT1 24 9 56- LED_ACT#
H8 VDDC_11 TRD0M B14 TRD0M 3 TD1- MX1- 22 57- TD- TD+ 57- 1 TX+
J8 B13 TRD0P 2 TD1+ MX1+ 23 57- TD+ TD- 57- 2 TX-
VDDC_12 TRD0P
K8 VDDC_13 4 TCT2 MCT2 21 RD+ 57- 3 RX+ G 13
P8 TRD1M P4
1 C105 1 C101 1 C107 1 C86 1 C322 1 C323 VDDC_14 TRD1M C14 TRD1P
6 TD2- MX2- 19 57- RD- C+ 57- 4
P5
J9 C13 5 TD2+ MX2+ 20 57- RD+ C- 57- 5
VDDC_15 TRD1P RX- G 14
2 0.1UF_16V2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V2 0.1UF_16V K9 VDDC_16 7 TCT3 MCT3 18 RD- 57- 6
J10 TRD2M P7
VDDC_17 TRD2M D14 TRD2P
9 TD3- MX3- 16 57- C- D+ 57- 7
P8
K10 D13 8 TD3+ MX3+ 17 57- C+ D- 57- 8
VDDC_18 TRD2P G1 G2 12
L10 VDDC_19 10 TCT4 MCT4 15 11 56- LED_LINK#
E12 VDDC_20 TRD3M E14 TRD3M 12 TD4- MX4- 13 57- D- +V3S
P12 E13 TRD3P 11 TD4+ MX4+ 14 57- D+
VDDC_21 TRD3P AMP_C_1470693_1_RJ45
P13 VDDC_22 +V2.5_LAN
M14 VDDC_23 BIASVDD A14 1 L4008 2 LANK_LG_2402S_24P
1 C1381 1 C1382 1 C90 1 C1383 1 C324 1 C325 H5
VDDC_01 BLM11A601S
2 0.1UF_16V2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V J5 VDDC_02 1.18K_1%
N14 1 C1353
RDAC D10
1 2
VDDC_24
P14 VDDC_25 R134 2 0.1UF_16V 1 1 1 1

75_1%

75_1%

75_1%

75_1%
1 C1352 1 C1371 1 C1372 1 C1373

R137

R129

R130

R131
+V2.5_LAN 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V
C8 DC_01 2 2 2 2

1 C1370

1 C89 2 2200PF_2000V
2 0.1UF_16V

H10 NC_08 MC_16 K11

MC_15 N9
M9
MC_14
J14 XTALVDD 4.7K_5%2
N11 XTALI LOW_PWR M11
1
R110 +V5S
R13851 N10 XTALO MC_12 P9
2 57-,43-,38-
X1002 PREP
200_5% N13 XTAL_VSS
1 2 U7
MC_11 M8
L8 1
IXO 8 IXO
25MHZ MC_10 VCC

C70
MC_09 N8 2 3 IXO 1
+V_LAN LED_ACT#_R 56- IXO 56-
LED_ACT#
1 C1384 1 C1385 2
G10 VSS_27 7
IXO 0.1UF_16V
2 27PF 2 27PF F10 1 L1024 2
VSS_26
M12 VSS_28 BLM11A601S
N12 1 C1375 1 C1380 56- 5
IXO 6 IXO 56-
VSS_29 LED_LINK#_R LED_LINK#
G9 2 0.1UF_16V 2 2.2UF_0805_16V 4 GND
IXO
VSS_30
H9 VSS_31
L9 VSS_32 PLLVDD2 H14 PER_PI5C3306_TSSOP_8P
B7
VSS_33
GPHY_PLL2_VSS M13
G13 1 R1378 2 56-
LED_LNK# LED_LINK#_R
LED_100# H13 470_5%
LED_1000# G12
G14 1 R1379 2 56-
LED_ACT# LED_ACT#_R
470_5% Q1048 5
+V3S 1 S1
G1
6 57-
BCM_BCM5705M_BGA_196P D1
D2 4 57-
LED_LINK#_R_DUCK
LED_ACT#_R_DUCK Engineer
R1384 2
1
10K_5%
3 G2
S2 2
NDC7002N
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
LAN INTERFACE-2
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 56 of 67
EE2 Wednesday, August 13, 2003 10:36:22 pm A02 PC8803

 +V3

2
+V5 R6040 2 L8
LAYOUT NOTES : 40~60 MIL R180 B_CRT 35-,57- 1 1 2
L15 30- B
10K_5% 0
1
1 2 1 C138 BLM11B750S
FBM_11_321611_3A PWR_LED_3 Q3
NDS7002A 2
3D 18PF
1 C170 G 2
1 C171 PWR_LED#_3
2 1UF_10V +V3 S
+V3 +V5 +V12 +VADPTR 2 0.1UF_16V 1
C328
C172 1 C6025
1 1 0.01UF_16V R6041 2 L9
2 +V5S G_CRT 35-,57- 1 1 2
1 C6026 G
2
2 2 CN1004 C6030 100PF_50V 0
30-

P1 5V_03 GND G1 1 2 1 C137 BLM11B750S

0.01UF_16V 100PF_50V P2 G2 R6021 R6022 R6023 R6024
VA GND 1 1 1 1 2 18PF
0.1UF_25V A1 12V_03 NBSWON# B1 59-,40-,38- PWR_SWIN#_3
R1220 1 2 1K_5% A2 B2 1 R179 2 13-
DETECT1 NC SLP_S3#_5R
A3 B3 1K_5% 1K_5% 1K_5%
3V_03 3V_03 0_5% C329
A4 VA_ON# B4 1K_5%
PWRLED PWR_LED_3 2 2 2 2
1
AIRACIN 55-,5- A5 ACIN PR_KB_DATA B5
A6 B6 40- KB_DAT_5
GND PR_KB_CLK KB_CLK_5 2 100PF_50V
A7 PR_CTS PR_MS_DATA B7 40-
SCTS_3R
SRTS_3
43-
43-,42- A8 PR_RTS# PR_MS_CLK B8 40- EM_DAT_5
R_CRT 35-,57- 1
R6042 2 1 L13 2
A9 B9 40- EM_CLK_5 30- R
SDSR#_3R PR_DSR# I2C_DATA SDA_MBAY 0
43- A10 PR_RI I2C_CLOCK B10
RI#_3R 43- SCL_MBAY 1 C165 BLM11B750S
SDCD#_3R A11 PR_DCD# GND B11
43- A12 B12 R12241 2 0_5%
SRXD_3R PR_SIN TV_COMP COMP_B 2 18PF
STXD_3
43-
43-,42- A13 PR_SOUT TV_CHROMA B13 R170 1 2 0_5% C330
43-,42- A14 B14 R169 1 2 0_5% CHROMA_C 1
SDTR#_3 PR_DRT# TV_LUMA LUMA_Y
A15 GND GND B15 2 100PF_50V
SLCTIN#_5 44-,42- A16 PPT_SLIN# CRTVS B16
44-,42- A17 B17 35- DOCK_VSYNC 1 1 1
PINIT#_5 PPT_INIT# CRTHS DOCK_HSYNC R168 R1223
A18 B18 35-
ERROR#_5 PPT_ERR# CRT_DDC_CLK DOCK_DDCCLK OPEN R178 75_1%
44-,42-
44-,42- A19 B19 35-
ALF#_5 PPT_AFD# CRT_DDC_DATA DOCK_DDCDATA OPEN
A20 B20 35-
SLCT_5 PPT_SLCT HPD 2 2 2
44-,42- A21 PPT_PE AGND B21
PE_5 44-,42-
BUSY_5 A22 PPT_BUSY CRT_B B22
PDATA(7:0) 44-,42- A23 B23 35-,57- B_CRT
ACK#_5 PPT_ACK# CRT_G G_CRT
44-,42- STRB#_5
44-,42-
44-,42- A24 PPT_STB# CRT_R B24 35-,57-
PDATA(7) A25 B25 35-,57- R_CRT
PPT_PD7 AGND
PDATA(6) A26 PPT_PD6 DVI_DDC_CLK B26
PDATA(5) A27 B27 57- DVIDDCCLK_D
PPT_PD5 DVI_DDC_DATA DVIDDCDATA_D
PDATA(4) A28 B28 57- R284 0_5%
PPT_PD4 GND
PDATA(3) A29 PPT_PD3 GND B29 1 2
PDATA(2) A30 B30 30- HPD
PPT_PD2 DVI_D2- TX2M
PDATA(1) A31 B31 30- D7
PPT_PD1 NC

K
1
PDATA(0) A32 PPT_PD0 DVI_D2+ B32 R285
A33 B33 30- TX2P FAIR_LM431SACMF_3P
GND GND 100K_5%
A34 B34

A
USBOC4# GND
A35 USBOC3# DVI_D1- B35 2
1 C1329 1 C1331 1 C161 1 C159 1 C163 1 C1320 1 C1318 1 C158 1 C169 A36 B36 30- TX1M OPEN
GND NC
2 33PF_50V 2 33PF_50V 2 33PF_50V
2 33PF_50V
2 33PF_50V 2 33PF_50V
2 33PF_50V 2 33PF_50V
2 33PF_50V
USB_PN2 38- A37 USB4- DVI_D1+ B37
A38 B38 30- TX1P
NC GND
USB_PP2 38- A39 USB4+ GND B39
1 C1328 1 C155 1 C160 1 C164 1 C162 1 C1317 1 C166 1 C1319 A40 B40
GND DVI_CLK- TXCM
2 33PF_50V
2 33PF_50V 2 33PF_50V
2 33PF_50V 2 33PF_50V
2 33PF_50V 2 33PF_50V
2 33PF_50V USB_PN3 38- A41 USB3- NC B41 30-
A42 NC DVI_CLK+ B42 +V3S +V5S
38- A43 B43 30- TXCP
USB_PP3 USB3+ GND
A44 GND B44
A45 GND B45
C1330 100PF_50V GND DVI_D0- 30- TX0M
A46 NC NC B46
C1335 100PF_50V A47 B47 1 1
1 2 NC DVI_D0+ TX0P
1 2 47- A48 PR_HPSENSE# B48 30- R156 R157
PR_HPSENSE# GND 4.7K_5% 2.2K_5%

2
MBAY_DISABLE 38- A49 NC GND B49

G
45- A50 SPDIF B50 Q1
SPDIF DVI_D5- 2 2
C1334 A51 AUDIO_GND B51 DVIDDCCLK 30- DVIDDCCLK_D

D
A52 NC B52

3
1 2 NC DVI_D5+
OPEN A53 B53 NDS7002A
AUDIO_GND GND
LINEINL 45- A54 LINEINL GND B54 NDS7002A
A55 B55

3
LINEINR 45- LINEINR DVI_D4- DVIDDCDATA 30- DVIDDCDATA_D

D
S
A56 AUDIO_GND NC B56 1 1
A57 LINEOUTL DVI_D4+ B57 Q2
1 C1337PR_AOUTL R158

2G
47- A58 LINEOUTR B58 R159
PR_AOUTR 47- GND 4.7K_5% 2.2K_5%
2 OPEN A59 AUDIO_GND GND B59
1 C1336 A60 B60
1 C1338 GND DVI_D3- 2 2
2 100PF_50V A61 1394TPBN1 NC B61
2 100PF_50V A62 NC DVI_D3+ B62 +V3S +V5S
A63 1394TPBP1 GND B63
A64 GND B64 +V5
A65 GND B65
1394TPAN1 NC
A66 NC NC B66
1 R154 2 A67 1394TPAP1 NC B67
1K_5% A68 GND GND B68
LED_ACT#_R_DUCK 56- A69 RJ45ACTLED DETECT2 B69 R141 1 2 1K_5%
A70 PREP RJ45_LILED B70
PREP 56-,43-,38- A71 B71 56- LED_LINK#_R_DUCK
RJ45_GND RJ45_GND
D+ 56- A72 D+ C+ B72
56- A73 B73 56- C+ 1 C6027
D- D- C- C-
A74 B74 56-
RJ45_GND RJ45_GND 2 100PF_50V
RD+ 56- A75 RJ45_RX+ RJ45_TX+ B75
56- A76 B76 56- TD+
RD- RJ45_RX- RJ45_TX- TD-
A77 B77 56-
RJ45_GND RJ45_GND
1 G G 3
2 G G 4
Engineer

JAE_WD_154S4VH_VF_154P David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
PORT PARALLER
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 57 of 67
EE2 Thursday, August 21, 2003 11:41:59 am A02 PC8803

 +V3

+V3S +V3 BLUETOOTH_VCC

1
R275
10K_5%
1
2 Q14
R1056
100K_5% 4 S D 1
2
2 Q1006 3 5 1 C304 C305 1
D
54-,40- 2G 1 R276 2 3 6
XMIT_OFF# G 2 10UF_K_6.3V 2
S 220K_5% FDC638P 0.1UF_16V
NDS7002A 1 ADD NOTES : 32 AWG MUST BE USED FOR THE CABLE

CN21
1
L1001 2 1
2
38- 1 2 3
USB_PP4 4 3
5 4
5
38- 4 3 6 G 9
USB_PN4 7 6
8 7 G 10
DLW21SN900SQ2L 8

JST_FM_SM8B_SRSS_TB_8P

BLUETOOTH_LED 59-

54- 1 R1057 2 100_5%

CH_DATA
54- 1 R1058 2 100_5%
CH_CLK

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
BLUETOOTH
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 58 of 67
EE2 Thursday, July 31, 2003 10:58:02 am A02 PC8803

 +V5S

+V3A

+V3A
LID SWITCH +V3S

CN22
38- CN23 54-,51-,42-,40-,37- 1 1
LID_SW#_3 1 PCI_RESET2#_3 2
1 FWH_WP#_3
38- 2
2 2 38- 3 3
3 FWH_TBL#_3 37-,16- 4
SCAN_OUT(1)
41-,40-,59- 3 H_INIT# 4
SCAN_IN(7) 41-,40-,59- 4 4 11- 5 5
1 5 MCH_GOOD 6
SDATA_OUT_ICH 45-,38- 5 6
45-,38- 6 6 7 7
D3 L7 CODEC_RST#_ICH
3 1 2 +V3A KSCAN_IN(5) 41- 7 7 55-,9- 8 8
LAN_ON_3
BAV99 BLM11B141S 8 8 47-,45-,40-,38-,13-,12-,9-,7- 9 9
FRAME_SYNC_ICH 45-,38- 9 SLP_S3#_3R
10
SW1 SDATA_IN1_ICH 38- 9 PHONE 54-,46- 10
45- 10 10 42-,40-,38-,30- 11 11
2 AC97_BIT_CLK 11 SUS_STAT#_3 12
SCAN_OUT(3)
41-,40- 11 LPC_DRQ1# 38- 12
55-,54-,51-,42-,40-,38- 12 12 13 13
CLKRUN#_3
51-,42-,40-,37- 13 13 14 14
R153 SERIRQ_3 14 15
1 2 15- 14 57-,40-,38- 15
CLK_FWHPCI_3R 15 PWR_SWIN#_3 16
3

100K_1% LPC_AD(0)
42-,40-,38- 15 NUM_LED#_3
40- 16
16 16 17 17
LPC_AD(1)42-,40-,38- 17 CAPS_LED#_3
40-
18
LPC_AD(2)42-,40-,38- 17 40- 18
1 C136 18 SCROLL_LED#_3 19
4
2

LPC_AD(3)
42-,40-,38- 18 PWR_LED#_3 57-,40-,59- 19
19 19 20 20
2 0.1UF_16V LPC_FRAME#_342-,40-,38- 41- 20 21
KSCAN_IN(1) 20 21
21 21 22 22
+V5A 22 +VCCP 23
PWR_GOOD_3 22 3A_120mil 23
40-,30-,14-,11- 23 23 24 24
SW_DT006_PT11ABH_E 41-,40- 24 24 25 25
SCAN_OUT(8) 1
25 25 26 26
26 C326 27
26 27
27 27 68UF_4V_METAL +VBATR 28 28
+V1.8S 28 29
28 29
29 29 30 30
3A_120mil 30 4A_160mil 31
30 31
31 31 32 32
32 32 33 33
33 33 34 34
34 34 35 35
35 35 36 36
+V1.2L 36 36 +V1.5A 37 37 G 41
37 37 G 41 38 38 G 42
4A_160mil 38 38 G 42 39 39
39 3A_120mil 40
39 40
40 40
MLX_53643_0404_40P
MLX_53643_0404_40P
1 C327

+V3S +V3A
C1292 68UF_4V_METAL
1 C1293
C1294 1 1 2
2 2 CN12
0.1UF_16V 0.1UF_16V 1
0.1UF_16V 1
2 2
3 RTCBAT
3
4 4
57-,40-,59- 5 5
PWR_LED#_3 6
BAT_LED#_3 40- 6
48- 7 7 CN6002
HDDASP#_5 8 1 1
LED_WLAN_LINK 54- 8 G 3
47-,45- 9 9 2 2 G 4
EAPD
BLUETOOTH_LED 58- 10 10
MBLED#_3 48- 11 11 JST_BM2B_SRSS
40- 12
VOL_UP 40-
12
VOL_DN 13 13
SCAN_IN(7) 41-,40-,59- 14 14
42- 15 15 G 21
IR_TX_3 16
IR_RX_3 42- 16 G 22
42- 17 17 G 23
IR_SD_3 18
SCAN_OUT(1)
41-,40-,59- 18 G 24
19 19
20 20
MLX_52559_2092_20P
FIX1 FIX2
S5 S6 S13 S14 S18 S19
S26 FIX_MASK FIX_MASK

FIX3 FIX4
SCREW2.8_6_7_5P SCREW2.8_6_7_5P SCREW2.8_6_5P SCREW2.8_6_7_5P SCREW2.8_6_5P SCREW2.8_6_5P
S7 S8 S15 SCREW2.8_8_5P
FIX_MASK FIX_MASK
S20 S21
FIX5 FIX6
PAD1003
1 1
FIX_MASK FIX_MASK
SCREW2.8_6_7_5P SCREW2.8_6_7_5P SCREW2.8_6_7_5P
SMDPAD3UM_5_1P SCREW2.8_6_5P SCREW2.8_6_5P
S9 S1 S3
Engineer
PAD1004
1 1
SCREW2.8_6_7_5P SCREW2.8_6.5_8_5PSCREW2.8_6.5_8_5P
S16 S17 David Du
Drawn by
David Du
INVENTEC
SMDPAD3UM_5_1P S11 S12 S2 R&D CHK Size
TITLE
A3
SCREW2.8_8_5P SCREW2.8_8_5P DOC CTRL CHK

MFG ENGR CHK

DIAMOND
SCREW2.8_6_7_5P SCREW2.8_6_7_5P SCREW2.8_6.5_8_5P SWITCH BUTTON & LED
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 59 of 67
EE2 Thursday, July 31, 2003 10:58:07 am A02 PC8803

 +V3S_BN

1
R4020
0_5%

2 (15/5)

C4019 1 1 C4018 1 C4017

2 2 0.01UF 2 0.01UF
1
R4024 4.7UF_K_6.3V
FWH_VPP_BN +V3S_BN
0_5% CN4002 AMP_C822273-1_SOKT_32P
2
25 VCC1 FWH0 13 63-,62-
LPC_AD_BN(0)
32 VCC2 FWH1 14 63-,62-
LPC_AD_BN(1)
27 VCCA FWH2 15 63-,62-
LPC_AD_BN(2) POWER15/5

C4028 1 FWH3 17 63-,62-

LPC_AD_BN(3) 1 1
C4031 1 1 C4029 1 C4030 1

2 2 2 2 0.1UF_16V 1 VPP FWH4 23 63-,62-

LPC_FRAME#_3_BN R4044 R4039 R4038
OPEN OPEN OPEN
0.1UF_16V 0.1UF_16V
PCI_RESET2#_3_BN 63-,62- 2 RST# FWH5 22 2 2 2
4.7UF_K_6.3V FWH_WP#_3_BN 63- 7 WP#
FWH_TBL#_3_BN 63- 8 TBL# FGPI0 6 PCBREV0
18 CLKRUN# FGPI1 5 PCBREV1
FWH_INIT#_3_BN 63- 24 INIT# FGPI2 4 PCBREV2
29 IC FGPI3 3 R4035 1 2 100_5%

CLK_FWHPCI_3R_BN 63-,62- 31
CLK4/20
CLK FGPI4 30 R40231 2 100_5%
1 1 1
LEGACY_FRE_EN#
1 R4043 R4036
ID0 12 R4037
R4021 19 FDIS 11 100_5% 100_5% 100_5%
OPEN
ID1

GND1
16 GND2
26 GND3
20 DPPO ID2 10 2 2 2
2
21 RFU ID3 9

28

FHW ON BUTTON DAUGHTER BOARD Engineer

David Du
Drawn by INVENTEC
David Du
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
FHW
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 60 of 67
EE2 Thursday, July 31, 2003 10:58:37 am A02 PC8803

 +V3S_BN POWER15/5

L4002
1 2
BLM41P800S
C4023
1 1 C4022
10UF_6.3V 2 0.1UF_16V

+V3S_BN
CN4003
1 MONO_OUT_PC_BEEP AUDIO_PWRDN 2
3 GND MONO_PHONE 4 63-AUDIO4/12
PHONE_BN +V5S_BN
5 AUXA_RIGHT RESERVED 6
7 AUXA_LEFT GND 8
9 CD_GND 5VMAIN 10
1 C4013 11 CD_RIGHT 12
RESERVED 1 C4048
2 0.1UF_16V 13 CD_LEFT RESERVED 14
15 GND PRIMARY_DN 16 2 0.1UF_16V
17 3.3VAUX 5VD 18
19 GND GND 20
21 3.3VMAIN SYNC 22 63- FRAME_SYNC_ICH_BN
63-
R4009 1 2 33_5% 23 24
SDATA_OUT_ICH_BN SDATA_OUT SDATA_INB R4048 1
CODEC_RST#_ICH_BN 63- 25 RESET# SDATA_INA 26 2 33_5% 63- SDATA_IN1_ICH_BN
27 GND GND 28
29 30 R4049 1 2 33_5% 63-
MSTRCLK BITCLK AC97_BIT_CLK_BN
31 G1 G2 32
33 G3 G4 34
35 G5 G6 36
1 C4042
AMP_3_179397_5_30P+6G 2 OPEN

MDC CONN

MDC CONN ON BUTTON DAUGHTER BOARD Engineer

David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
MDC CONN
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 61 of 67
EE2 Thursday, July 31, 2003 10:58:42 am A02 PC8803

 +V3S_BN
+V3S_BN
POWER15/5

CN4000
C4034 1 1
CLK_FWHPCI_3R_BN 63-,60- 1
2 2
1 4.7UF_K_6.3V 2
3 3
R4046 4 4
10K_5% 63- 1 R4047 2 OPEN 5 5
LPC_DRQ1#_BN
6 6
2
63- 7 7
SERIRQ_3_BN 8 8
63-,60- 9 9
R4045 2 LPC_AD_BN(0) 10
63- 1 10
SUS_STAT#_3_BN 11
OPEN LPC_AD_BN(1) 63-,60- 11
63- 12 12
CLKRUN#_3_BN 13
LPC_AD_BN(2) 63-,60- 13
14 14
63-,60- 15 15
LPC_AD_BN(3) 16 16
63-,60- 17 17
LPC_FRAME#_3_BN 18 18
63-,60- 19 19 25 25
PCI_RESET2#_3_BN
20 20 26 26
21 21 27 27
22 22 28 28
23 23 29 29
24 24 30 30

ACES_88028_2400_24P

AMP 20PIN CONNECTOR

MOTHERBOARD SIDE
ACES_88028_2400

TCPA CONN ON BUTTON DAUGHTER BOARD Engineer

David Du
Drawn by INVENTEC
David Du
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
TCPA
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 62 of 67
EE2 Thursday, July 31, 2003 10:58:47 am A02 PC8803

 +V3S_BN

+V3A_BN R4018
1
330_5%
R4016 2
1.3K_1% 60-
FWH_INIT#_3_BN
1 R4011 2100K_5% 63- PWR_SWIN#_3_BN 2 3
C
+V3S_BN
2 B
Q4002
E
D4003 DSLED_CL150YG 1 R4014 2
Q4001 3 1 63-
SST3904 1 2
63- 1 R4015 2 2B C
NUM_LED#_3_BN 270_5%
1 SW4003 H_INIT#_BN
C4014 330_5% E
2 1
2 1000PF_J_50V
SST3904 1 D4002
63-
DSLED_CL150YG 1 R4013 2
+V3A_BN
3 SWTT_TC003_PS11AT_A 1 2
CAPS_LED#_3_BN 270_5%

2 1 +V5S_BN
D4000 D4001
63-
DSLED_CL150YG 1 R4012 2
+V3A_BN
BAV99 1 2
+V3S_BN SCROLL_LED#_3_BN 270_5%
1 C4047
2 0.1UF_16V
1 C4045
C4046 1 CN4005
2 0.1UF_16V
2 62-,60- 1 1
CN4004 0.1UF_16V PCI_RESET2#_3_BN 2
FWH_WP#_3_BN 60- 2
1 1 60- 3 3
2 FWH_TBL#_3_BN 63- 4
2 H_INIT#_BN 4
63- 3 3 10- 5 5
SCAN_OUT_BN(1)
4 MCH_GOOD_BN 6
SCAN_IN_BN(7) 63- 4 6
61- 5 5 7 7
SDATA_OUT_ICH_BN
61- 6 6 10- 8 8
CODEC_RST#_ICH_BN 7 LAN_ON_3_BN
9
KSCAN_IN_BN(5) 63- 7 10-,8- 9
SLP_S3#_3R_BN
61- 8 8 61- 10 10
FRAME_SYNC_ICH_BN PHONE_BN
61- 9 9 62- 11 11
SDATA_IN1_ICH_BN 10 SUS_STAT#_3_BN 12
AC97_BIT_CLK_BN 61- 10 LPC_DRQ1#_BN 62- 12
63- 11 11 13 13
SCAN_OUT_BN(3)
62- 12 12 14 14
CLKRUN#_3_BN 13 15
SERIRQ_3_BN 62- 13 PWR_SWIN#_3_BN 63- 15
62-,60- 14 14 63- 16 16
CLK_FWHPCI_3R_BN 15 NUM_LED#_3_BN
17
LPC_AD_BN(0) 62-,60- 15 CAPS_LED#_3_BN
63- 17
62-,60- 16 16 63- 18 18
LPC_AD_BN(1) 17 SCROLL_LED#_3_BN 19
LPC_AD_BN(2) 62-,60- 17 PWR_LED#_3_BN 19
18 18 20 20
LPC_AD_BN(3) 62-,60- 19 21
LPC_FRAME#_3_BN 62-,60- 19 21
KSCAN_IN_BN(1) 63- 20 20 +VCCP_BN 22 22
21 21 23 23
+V5A_BN 22 24
PWR_GOOD_3_BN 22 24
10- 23 23 25 25
63- 24 24 26 26
SCAN_OUT_BN(8)
25 25 27 27
26 26 +VBATP_BN 28 28
SW4001 P2 +V1.8S_BN 27 27 29 29
28 30
SCAN_OUT_BN(1)
63- 2 1 63- KSCAN_IN_BN(5)
INTERNAL 29
28
29 31
30
31
SWTT_TC003_PS11AT_A 30 30 32 32
31 31 33 33
32 32 34 34
33 33 35 35
34 34 36 36
35 35 +V1.5A_BN 37 37 G 41
36 36 38 38 G 42
SW4000 +V1.2L_BN 37 39
P1 37 G 41 39
2 1 38 38 G 42 40
SCAN_OUT_BN(8)
63- 63- SCAN_IN_BN(7)
E-MAIL 39 39
40
SWTT_TC003_PS11AT_A 40 40 MLX_52885_0404_40P

S4 S23 MLX_52885_0404_40P

FIX7 FIX9 FIX11

P3 FIX_MASK FIX_MASK FIX_MASK

SW4002 SCREW2.8_6_5P SCREW2.8_6_5P
SCAN_OUT_BN(3)
63- 2 1 63- KSCAN_IN_BN(1) SERCH S25
FIX8 FIX10 FIX12
SWTT_TC003_PS11AT_A
S22 S24 FIX_MASK FIX_MASK FIX_MASK
SCREW3.3_5_5P

SCREW2_6_5P SCREW2_6_5P

Engineer
David Du
INVENTEC
SWITCH & CONN & LED ON BUTTON DAUGHTER BOARD Drawn by
David Du
R&D CHK
TITLE
Size
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
CONN & SWITCH & LED
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 63 of 67
EE2 Thursday, July 31, 2003 10:58:55 am A02 PC8803

 +V3A_LD
+V3S_LD
64- 1 R6000 2
VOL_UP_LD

1
47_5%
S
1 +V3A_LD

4
5
3
64-
64- D6003 1 R6008 2 MBLED#_3_LD
2G BAV99
PWR_LED#_3_LD D FIX13 FIX16 3
1 2 1
270_5% BSS84 3
Q6002
DSLED_CL150YG FIX_MASK FIX_MASK
2 C6000 TC010-PS11CET_B
2 1 SW6001
0.1UF_16V

2
+V3S_LD DSLED_CL150YG
FIX14 FIX17 D6000
D6007 LEDBOARD_GND

1
FIX_MASK FIX_MASK LEDBOARD_GND
1
S
1 LEDBOARD_GND
64- R6013
HDDASP#_3_LD
2G D
270_5% FIX15 FIX18
BSS84 3
Q6004 2
FIX_MASK FIX_MASK

+V3S_LD
LEDBOARD_GND
1 R6012 2 D6006
1 2
270_5%
DSLED_CL150YG

2
LEDBOARD_GND
LED_WLAN_LINK_LD 64-
D6001

1
SML011BBT 1
1
LEDBOARD_GND R6003
R6001 Q6000 5
S1 270_5% SW6000
1 64- 1 R6002 2
+V3A_LD 100K_1% G1 2 VOL_DN_LD
6

1
2 D1 47_5% 1
D2 4 +V3A_LD
3 G2 2 C6001
S2 2

4
5
3
LEDBOARD_GND 0.1UF_16V
3 BAV99
64-
NDC7002N
BLUETOOTH_LED_LD
LEDBOARD_GND
D6004 R6007 2 TC010-PS11CET_B
BAT_LED#_3_LD 64- 1 2 1
1 2
270_5% 1
CL_150TY_LED D6002
R6005
100K_1%
LEDBOARD_GND
2
LEDBOARD_GND
+V3S_LD
+V3A_LD
LEDBOARD_GND LEDBOARD_GND
1 C6007 1 C6006
2 2 1 C6008
1 R6010 2
2 0.1UF_16V +V3S_LD
0.1UF_16V 0.1UF_16V 47K_5%
LEDBOARD_GND CN6000 +V3S_LD
1 SW6002 (15/5) R6011 2 (15/5)
LEDBOARD_GND 1 1
2 2 64- 1 2 64-
3 SCAN_OUT_LD(1) SCAN_IN_LD(7) 2.7_2010_1/2W
3
4 4 3 4
64- 5 5 D6005
PWR_LED#_3_LD 6
BAT_LED#_3_LD 64- 6 10 LEDA VCC 1
7 7 ALPS_SKQHFSE010_4P 1 R6004 2 9 7
HDDASP#_3_LD 64- IR_TX_3_LD 64- TXD
64- 8 8 64- 8 RXD GND 2 1 C6005 1 C6003 1 C6004 1 C6002
LED_WLAN_LINK_LD
9 270_5% IR_RX_3_LD AGND
EAPD_LD 64- 9 3 FIR_SEL NC 6 2 2 2 2 10UF_K_6.3V
64- 10 10 64- 5 MD1 11
BLUETOOTH_LED_LD
11 IR_SD_3_LD GND
MBLED#_3_LD 64- 11 4 MD0
64- 12
VOL_UP_LD 64-
12
VOL_DN_LD 13 13 HSDL_3600_008 0.47UF_16V 4.7UF_K_6.3V 0.1UF_16V
64- 14 Q6001
SCAN_IN_LD(7) 14
64- 15 15 G 21 3
IR_TX_3_LD 16
D

IR_RX_3_LD 64- 16 G 22 EAPD_LD 64- 2G

64- 17 17 G 23 LEDBOARD_GND
IR_SD_3_LD 18
S 1
SCAN_OUT_LD(1) 64- 18 G 24 1
19 19 NDS7002A R6009
20 20
R6006
1 4.7K_5%
IR
2
MLX_52559_2092_20P 100K_1%
2

LEDBOARD_GND
LEDBOARD_GND LEDBOARD_GND LEDBOARD_GND

LEDBOARD_GND

Engineer

LED & VOL BUTTON ON LED DAUGHTER BOARD David Du

Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
LED & VOL BUTTON
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 64 of 67
EE2 Thursday, July 31, 2003 10:59:01 am A02 PC8803

 SHEET 50
SHEET 10 SHEET 31
1. Change CN2068 for mechanical
1.R1096 change from 10K to 200K and add CAP (0.01UF) to GND
NOTE: For ATI power sequence SHEET 56 1. CHANGE C1982 C1983 TO 10 PF THESE TWO CAPACITORS VALUSE CAN BE TUNED
1. Change CN2062 point name 2. ADD SERIES RESISTORS R237 R238 ON EACHOF THE TWO SIGNAL (DIMB_0 DIMB_1 )
SHEET 11 MAKE A NOTE TO ONLY INSTALL THESE RESISTORS FOR ELPIDA MEMORY
NOTE: Modify LAN signal to right
1. Add PM_VGATE DELAY CIRCUIT: U18, D23, R156, C90, C107
SHEET 63 SHEET 32
2. Add CAP (0.1UF) in R2024 pin1 to GND
1.Change SW4 for mechanical 1. ADD L21 TO POWER PIN( P8, Y8, AC11,AC20,Y23, L23,H20,H11)
NOTE: For PCI_RESET, PCI_CLOCK , PM_VGATE TIMING MAKE A NOTES: THIS RAIL HAVE JUMPER TO SWITCH FOR +V1.5S FOR M10 , +V1.8S FOR M9+X
SHEET 64
SHEET 12 1.Change D21 for mechanical SHEET 33

1. Del PAD2 , PAD515 and to short power 1. CHANGE THE TITLE , THESE IS A TYPO" VEDIO". IT SHOULD BE " VIDEO"
CHANGE LIST FEBRUARY 12

SHEET 13 SHEET 11
1. R1122 change from 220K to 100K and add CAP(0.1UF) in R1122 pin1 to GND CHANGE LIST FEBRUARY 17
1.Change C65 TO CONNECTED TO PIN2 OF R2024(REF.RUBY)
2. Add CAP (OPEN) in Q25 pin3 to GND 2.CHANGE R1061 TO OPEN(REF.RUBY) SHEET 32
NOTE: For ATI power sequence
SHEET 13 1. OPEN L12 AND L21 PUT BLM21A121S TO USED M9+X +V1.8S
1.CHANGE R1122 FROM 220K TO 100K (REF.RUBY) SHEET 42
SHEET 29
1. Add SERIES RESISTORS on SB_STBS(R208), ADSTBS_0(R211), ADSTBS_1(R212) SHEET 29 1. OPEN L12 AND L21 PUT BLM21A12. CHANGE SIGNAL NAME R252 PIN2 FROM PCI_RESET TO NPCI_RESET

2. Add SERIES RESISTORS DBI_LO(R198), DBI_HI(R197) 1. ADD NOTE TO M9+X , M10 R153, R154 USED OR NOT CHANGE LIST FEBRUARY 20
3. Change R72 from 10K to 20K 2. Change AGPTEST DBI_LO & DBI_HI TO +V1.5ATIAGP RAIL TO MATCH RUBY
SHEET 11
4.Add TEST POINT in GPIO(4:7) GPIO(9:14) SHEET 30
1. U2010 PIN2(TON) TO ADD RESISTOR (OPEN) THEN PULL UP TO +VCCP
5. Add 1K pull down on GPIO8 1.OPEN R2102 TO MATCH RUBY SCH (REF.RUBY)
2.ADD NOTE : R687&R1766 FOR M9+X OR M10 USED SHEET 13
6. Add 1K pull down RESISTOR to prvent leakage for some ZV_LCDDATA, ZV_LCDCNTL pin
3. ADD 10K PULL-UP +V3S TO AUXWIN PIN AF26 (REF.RUBY)
(ZV_LCDDATA(5:15), (18:19), ZV_LCDCNTL(0:3) ) SHEET 32 1. CHANGE C66 VAULE FROM 22UF TO 68UF
7. Add 10K pull down RESISTOR to prevent leakage for ZV_LCDDATA(16:17) 1.ADD L20 NFM41P11C204 TO MATCH RUBY SCH (REF.RUBY) 2. ADD THE CAP 10UF C91 PIN1 TO LINK Q26 (PIN1,2,5,6) C91 PIN2 TO GND
2.CHANGE L19,L1062, L1056, L1063, L1064, L1059,&L1060 TO MATCH RUBY SCH (REF.RUBY)
NOTE: Above items for ATI recommed
3.CHANGE L5/L4,&L12 TO MATCH RUBY SCH(REF.RUBY)
SHEET 30
20
8. R153,R154, change form 1K to 3K
NOTE: For +V3S power rail ( ATI- VREFG) 1. CHANGE U2019 , U2329 FROM ADM1032 TO ADM1031 TWO PACKAGE THERMAL MONITOR
9. Add SERIES RESISTORS STOP(R192) DEVSEL(R199) TRDY(R200) IRDY(R217) FRAME(R216) SHEET 38
10. Add SERIES RESISTORS WBF(R205) RBF(R215) AD_STBF_0(R202) AD_STBF_1(R203) SB_STBF(R204)
11. R189 , R190 PIN2 TO GND 1. CHANGE GPIO42 TO VMEM_CFG3 AND PULL UP TO +V3S & 8.2K TO GROUNDTO MATCH RUBY SCH (REF.RUBY)
12. R72 PIN 1 TO LINK +V3S 2. ADD INVERTER BETWEEN PIN H22 (GPIO39) AND U2038 (PIN26) TO MATCH RUBY SCH (REF.RUBY)
SHEET 50 CHANGE LIST FEBRUARY 21
SHEET 30 SHEET 20
54
1.CHANGE USB POWER FROM +V5A TO +V5 TO MATCH RUBY SCH(REF.RUBY)
1. Add 0 OHM series resistor on the path of osc output to XTAL and XTALOUT 1. ADD THE BLUETOOTH SIGNAL AT CN1020 PIN43(CH_DATA) , PIN36(CH_CLK)
NOTE: Select frequency enter chalnnel
CHANGE LIST FEBRUARY 14 20
SHEET 56
SHEET 29,30, 31, 32 SHEET 33 2. REMOVE C1671 C1673 C1674 C1675 THEN C1672 PIN2 CHAISY GND CHANGE TO DIGITAL GND
1. Change for ATI M9+X , M10 dual footprint schematic 1. CHANGE DEPEND RESISTORS PACKAGE TO LAYOUT ROUTES SHEET 58

SHEET 36 1. ADD TWO SIGNAL AT CN1036 PIN6(CH_DATA) , PIN7(CH_CLK) THEN ADD TWO SERIES RESISTORS

1. Add R219 TO JUMP M10 OR M9+X CHANGE LIST FEBRUARY 15 100 OHM TO THESE PIN

SHEET 38
SHEET 10 CHANGE LIST FEBRUARY 23
1. U509 -V19 (PM_VGATE/VRMPWRGD) change from PM_VGATE to SB_VGATE
1. ADD U22 SCHMITT BUFFER FROM PIN2 R1096
2. Add U509 GPIO42 resistors R236 pull up +V3S and R237 pull down to GND 1. ADD RESISTOR 100K PULL UP TO +V3S ANOTHER PIN TO LINK Q53 PIN2(XMIT_OFF#)
AFTER THE RC CIRCUIT TO PIN10 OF U2008
NOTE: To chose memory type
SHEET 29
SHEET 41 CHANGE LIST FEBRUARY 27
1. Rotate CN8 (the touch-pad conect):180 point of view and pin5,6 link to GND, pin7,8 link to CN7 pin3 1. MAKE A NOTE R1957 R1958 TO INSTALL M9+X OR M10 BE USED SHEET 22
20
2. Change CN7 (stick point) geoetric ( layout pattern) 2. MAKE A NOTE R1956 TO INSTALL M9+X OR M10 BE USED
1. ADD BYPASS CAPACITORS C308, C309, C310 (220P)

SHEET 49
SHEET 25 26
1. Change R155 from 10K to 100K 1. ADD BYPASS CAPACITORS , C311, C313 (150UF)

Engineer
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
CHANGE LIST
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 65 of 67
EE2 Thursday, July 31, 2003 10:59:06 am A02 PC8803

FOR SI SCHEMATIC CHANGE
2003/03/24 update 2003/03/30 update
SHEET 17
1. FOR PSI# PULL HIGH +VCCP TO OPEN R1089 SHEET 31 & 34 SHEET 5
1. ADD DDR_CSB1# SIGNAL FOR 8M*32 VRAN USED 1. ADD R6021 RESISTOR OPEN TO MODIFY OCP
SHEET 38 AND ADD R6016 RESISTOR DEPEND TO LINK U1018 & U1019 PIN M4
SHEET 33
1. REMOVE PWM_GOOD_3 SIGNAL DELETE R1419 SHEET5 1. CHANGE THE VALUE OF SERIAL TERMINATION RESISTORS ON THE DATA ,
DQM AND QS LINES TO 22-OHMS
1.CHANGE R1068 VALUE FROM 150K TO 10K AND R1070 VALUE
SHEET 40 FROM 20K TO 1.3K FOR AC DETECT LEVEL
SHEET 34
1. R1049 FOR PCI_SERR#_3 PULL DOWN TO OPEN SHEET15 1. CHANGE THE VALUE OF SERIAL TERMINATION RESISTOR OF QS LINE TO 22-HHMS
2. KBC INITIAL NEED TO PULL DOWN 100K RESISTOR R1 1.CHANGE R6015 VALUE FROM OPEN TO 33 AND R1361 VALUE
3. ADD U4004 , D6008 , R6014 , C6011 , C6012 THIS CIRCUIT TO FINE_TUNE POWER ON SEQUENCE TIME
CHANGE TO OPEN FOR AC97 FRQUENCE CHANGE 14.318MHZ
SHEET 40
SHEET 41 SHEET42 1. R105 SHOULD BE OPEN TO FINE TUNE KBC POWER UP SEQUENTIAL

1. RNET FOR KAHUNA PROGRAMMING. NEED ONLY FOR FLASH RECOVERY SATURATION 1.CHANGE R126 VALUE TO 0 AND R125 VALUE CHANGE
FROM 0 TO OPEN FOR SUPER I/O USED_NPCI_RESET SHEET 55
SHEET 50 SHEET44 1. ADD TWO 0.1uF DECAPS C6018 AND C6019 TO +V3S RAIL
2. ADD 0.1uF DECAPS C6019 TO +V3_LAN
1. REMOVE USB_OC#0 U2 , U3 PIN_2 TO OPEN 1.CHANGE R1165_PIN-1 VOLTAGE FROM +5VA TO +V5
2. U2 , U3 PIN_1(EN) CONNECT +5V
3. U2 , U3 PIN_5 CONNECT +V5A SHEET 56
4. REMOVE L3 AND TO SHORT SHEET45
1. ADD SIX 0.1uF DECAPS C6021 , C6022 , C6023 , C6024 , C6025 , C6026 TO +V_LAN RAIL
1.CHANGE R1460 FROM OPEN TO 1K FOR AC97 CHOOSE FRQUENCE

SHEET 52 2003/03/26 update

1. REMOVE R1126 , R1128 TO A_CCLKRUN# , B_CCLKRUN# SIGNAL PULL UP REPEAT 2003/04/03 update
SHEET13
SHEET 45
1. CHANGE P MOS Q1041 , Q1046 , Q10 , Q11 HIGH CURRENT AND LOW RDS ON
SHEET 64 1. ISOLATE PCSPKB_3 USING A 2N7002 WITH DRAIN CONNECTED TO +V3S THROUGH A 10K PULL-UP ,
SOURCE TO GROUND , & GATE TO PCSPKB_3 . PIN 2 OF C28 SHOULD BE CONNECTED TO DRAIN OF 2N7002 ,
1. ADD Q6004 TO PREVENT THE CURRENT FROM D6006 INTO HDDLED LOGIC OUTPUT SHEET36 WHICH FEEDS THE AUX INPUT OF CODEC

1. CHANGE P MOS , Q1050 HIGH CURRENT AND LOW RDS ON 2. ISOLATE PCSPKB_ICH_3 USING A 2N7002 WITH DRAIN CONNECTED TO +V3S THROUGH A 10K PULL-UP ,
SOURCE TO GROUND , & GATE TO PCSPKB_ICH_3 . PIN 2 OF C15 SHOULD BE CONNECTED TO DRAIN OF 2N7002 ,
2003/03/18 update SHEET 40
WHICH FEEDS THE AUX INPUT OF CODEC

SHEET 15 1. REMOVE R1409 , D1028 AND TO SHORT PCI_SERR#_3

SHEET 46
SHEET 50 1. ISOLATE PHONE USING A 2N7002 WITH DRAIN CONNECTED TO +V3S THROUGH A 10K PULL-UP ,
1. ADD R6013 RESISTOR OPEN TO JUMP CLK_SIO14_3R & ADI48M SOURCE TO GROUND , & GATE TO PHONE . PIN 1 OF C24 SHOULD BE CONNECTED TO DRAIN OF 2N7002 ,
1. REMOVE L2 AND TO SHORT WHICH FEEDS THE AUX INPUT OF CODEC

SHEET 40 SHEET 52 SHEET 47 , 64

1. CHANGE R1132 , R1133 FROM 47 OHM TO 22 OHM FOR A_CCLK & B_CCLK TIMING 1. CHANGING FDD ACTIVITY LED TO MULTI-BAY ACTIVITY LED
AND HDD ACTIVITY LED TO JUST THE FIXED HDD
1. ADD C6013 18P CAPICATOR BYPASS TO LOW_BAT#_3 THIS SIGNAL
SHEET 55
2003/04/05 update
1. CHANGE VALUE C1358 , C1357 , C1398 FROM 0.01UF TO 0.1UF FOR BCM MODIFY
2003/03/19 update SHEET 31
2. ADD CAPACITORS C6015 , C6014 10UF FOR BCM MODIFY
1. CAPS C120 AND C125 ON CLOCK LINES CHANGE TO 10NF
SHEET 20
1. ADD U4005 , R6016 , Q6005 , D6009 , C6015 , C6014 THIS CIRCUIT AND CN6001 TO SECOND FAN
SHEET 57
1. THE HPD CIRCUIT REQUIRES A 2.5V ZENER (IN PARALLEL WITH R1264) , AND ADDITIONAL 20K IN SERIES.
SHEET 59
SEE THE ATI REFERENCE DESIGN BOARD
1. REMOVE CN22_PIN-5-RTCBAT
2. ADD CN6002 TO RCT CONNECTOR FOR MECHICNAL CHANGE

SHEET 63
1.REMOVE CN4001 RTC CONNECTOR , CN1010_PIN-5-RTCBAT FOR MECHICNAL CHANGE

SHEET 64
Engineer
1. CHANGE SW6001 AND SW6000 FOR MECHICNAL MODIFY
2. CHANGE D6005 I.R. SIZE FOR MECHICNAL MODIFY
David Du
Drawn by
David Du
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
CHANGE LIST
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 66 of 67
EE2 Thursday, July 31, 2003 10:59:10 am A02 PC8803

 FOR PV SCHEMATIC CHANGE FOR PVR SCHEMATIC CHANGE 2003/07/17 FOR MV B SCHEMATIC CHANGE 2003/08/15
SHEET 5
SHEET 30 SHEET 57
1. CHANGE CAPACITOR VALUE C6027, C1335 FROM OPEN TO 100PF FOR EMI SOLUTION FOR OCP circuit add R6043(0ohm) between U1002-8 and U1002-5
1. ADD R6026 , R6027 , R6028 75 OHM RESISTORS TO PULL DOWN TO CRT SIGNAL R G B 2. ADD CAPACITOR C6030_100PF FOR EMI SOLUTION add R6044(open) and D6009(BAT54C) between U1002-13 and U1002-5

SHEET 46
SHEET 35 SHEET 28
1. ADD CAPACITOR C6042_100PF between U1 pin 12 , pin 13 .
1. ADD C6020 , CC6021 , C6022 CAPACITORS PULL DOWN TO OPEN 1. ADD CAPACITORS C6031 , C6032 , C6033 , C6034 , C6035 , C6036 , C6037 100PF FOR EMI SOLUTION
2. ADD CAPACITOR C6041 open between U1 pin 2 , pin 3 .
2. CHANGE L4 , L5 , L6 FROM BEAD TO 0 OHM RESISTORS
2. CHANGE CAPACITOR VALUE C256 FRPM 0.1uF TO 100PF
3. ADD CAPACITOR C6043_100PF between U1 pin 9 , pin 10 .
SHEET 45
1. CHANGE C1435 FROM 4.7UF TO OPEN
FOR PVR SCHEMATIC CHANGE 2003/07/23
SHEET 9
FOR MV B SCHEMATIC CHANGE 2003/08/21
2. SWAP MPCI_PWM THIS SIGNAL FROM C24 PIN1 TO Q1061 PIN 2 THAN Q1061 PIN 3 SWAP TO LINK R12 PIN 1
1. R1582 , R1583 , R6019 , C1469 , Q1057 , Q1058 CHANGE TO OPEN FOR HP REQUIREMENT
SHEET 46 SHEET 6
1. SWAP PHONE THIS SIGNAL FROM R12 PIN1 TO C24 PIN 2
SHEET 20 1. CHANGE RESISTOR VALUE R1581 FROM 2.7K OHM TO 3.3K OHM FOR BATTERY SOLUTION
2. CHANGE C5 , C6 , C23 FROM 0.1UF TO 0.01UF
1. CN24 NOT TO USE
SHEET 51 SHEET 9
SHEET 47
1. ADD Q6005 NMOS TO CLEAR BACKWARD CURRENT 1. CHANGE CAPACITOR VALUE C6016 FROM OPEN TO 12000PF FOR ATI RECOMMEND
1. R1465 , R1449 CHANGE VALUE FROM OPEN TO 0 OHM
SHEET 57 2. R1463 , R1448 CHANGE VALUE FROM 0 OHM TO OPEN
SHEET 13
1. KB_DAT_5 , KB_CLK_5 , EM_DAT_5 , EM_CLK_5, THIS SIGNAL SHEET 5 54
ADD R6021 , R6022 , R6023 , R6024 , RESISTORS TO PULL UP +V5S 1. CHANGE CAPACITOR VALUE C187 FROM 0.1UF TO 39000PF FOR ATI RECOMMEND
1. MOVE Q1009 , R1071 FOR LAYOUT PLACEMENT BECAUSE MECHANICAL COVER HAVE TO SHORT
2. CHANGE L8 , L9 , L13 FROM 110 OHM FITTER BEAD TO 39 NH FITTER BEAD

3. CHANGE L4007 , L4006 , L4005 FROM 75 OHM FITTER BEAD TO 110 NH FITTER BEAD
4. CHANGE C137 , C138 , C165 FROM OPEN TO 18PF CAPICATORS
FOR PVR SCHEMATIC CHANGE 2003/07/28
SHEET 5 57
FOR PV-R SCHEMATIC CHANGE 2003/07/15 1. Change resistors value R6021,R6022 ,R6023 , R6024 from 4.7k ohm to 1k ohm for KBC PS2 microsoft keyboard to match .

SHEET 9
1. CHANGE CAPACITOR C230 IMPROVE VGA/VCC BYPASS CAPACITOR ESR FOR PVR SCHEMATIC CHANGE 2003/07/31
SHEET 54 SHEET 32
1. CHANGE CAPACITOR C1075 , C1076 , C1077 , C1078 , C1079 , C1080 , SIZE FROM 0603 TO 0402
TO FIX INTEL WIRELESS CARD TO TOUCH CAPACITOR MECHANICAL ISSUE 1. change capacitor value C1268 from 22uF to 68uF

SHEET 56 FOR PVR SCHEMATIC CHANGE 2003/08/01

1. CHANGE RESISTOR R134 VALUE FROM 1.24K TO 1.21K TO INCREASE THE SIGNAL VOLTAGE LEVEL TO MEETING THE IEEE SPEC.
2. CHANGE R1351 FROM 4.7OHM TO BLM11A601S FITTER BEAD (L4008) TO INCREASE THE SIGNAL VOLTAGE LEVEL TO MEETING THE IEEE SPEC. SHEET 35
1. change ferrite-bead from L4, L5 , L6 (BLM11B750S) to resistors R6037 , R6038 , R6039 0 ohm
SHEET 57
1. ADD CAPACITOR C328 , C329 , C330 TO 150PF FOR EMI SOLUTION SHEET 57
1. change ferrite-bead from L4007, L4006 , L4005 (111XJBC_110NH) to resistors R6040 , R6041 , R6042 0 ohm
SHEET 58
1. MOVE R1057 , R1058 FOR LAYOUT PLACEMENT BECAUSE MECHANICAL COVER HAVE TO SHORT 2. change ferrite-bead from L8, L9 , L13 (111XJBC_39NH) to ferrite-bead L8 , L9 , L10 BLM11B750S

SHEET 59 FOR MV B SCHEMATIC CHANGE 2003/08/13

1. CLEAR PAD1003 LINK TO GND FOR EMI SOLUTION SHEET 32
2. ADD PAD1004 FOR THERMAL
1. ADD P-MOS Q6006 PIN4 LINK TO SLP_S3_5R , PIN5,8 LINK TO +AGP_V3S & PIN1, 2, 3, 6, 7, LINK TO +V3S
2.REMOVE L1014
SHEET 63
1. DELETE R4010 AND LED_POWER_SWITCH CIRCUIT CHANGE TO SWITCH CIRCUIT FOR MECHANICAL REQUIREMENT SHEET 20
1. CHANGE CAPACITOR VALUE C286 2200pF TO NON-INSTALL
SHEET 64 SHEET 38
1. IR_PIN11 LINK TO GND
1. ADD C6039 0.1UF BYPASS CAPACITOR .

LAYOUT NOTE: SHEET 47 Engineer

1. CLK_CBIPCI_3R==>L5 CHANGE TO L3 1. CHANGE RESISTOR R6035 0 OHM TO C6040 0.01UF CAPACITOR .

David Du
Drawn by
David Du
INVENTEC
2. CLK_MINIPCI_3R==>L5 CHANGE TO L3 R&D CHK Size
SHEET 56 TITLE
A3
1. CHANGE RESISTOR VALUE R134 FROM 1.21K TO 1.18K OHM.
DOC CTRL CHK

MFG ENGR CHK

DIAMOND
CHANGE LIST
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 67 of 67
EE2 Thursday, August 21, 2003 11:48:22 am A02 PC8803