Unit0 Introduction Nazarian EE477 Fall12 PDF

University of Southern California
Viterbi School of Engineering
EE477L
MOS VLSI Circuit Design
Introduction
Shahin Nazarian Fall 2012

Evolution of transistor in ICs
BJT invention, Bell Labs, 1947

Single transistor, TI, 1958
CMOS gate, Fairchild, 1963
First processor, Intel, 1970
Very Large Scale Integration, 1978
Up to 20k transistor
Ultra Large Scale Integration, 1989

More than 1 million per chip
System-on-Chip, 2002
20 to 30 million transistors
Shahin Nazarian/EE477L/Fall 2012 2

The First Computer
The Babbage
Difference Engine
(1832)
25,000 parts
cost: 17,470

ENIAC - The First Electronic Computer
(1946)

The Transistor Revolution
First transistor
Bell Labs, 1947

(Optional) BJT
NPN and PNP
The bipolar (point-contact) transistor was invented in December

1947 at the Bell Telephone Laboratories by John Bardeen and
Walter Brattain under the direction of William Shockley
The junction version, invented by Shockley in 1948, enjoyed three
decades as the device of choice in the design of discrete and
integrated circuits. Nowadays, the use of the BJT has declined in
favor of CMOS technology in the design of digital integrated
circuits

The First Integrated Circuit
Bipolar logic
1960s
ECL (Emitter Coupled Logic)

3-input Gate Motorola 1966

Intel 4004 Micro-Processor
1971
1000 transistors
1 MHz operation

A Leading Edge Example
Intel Core i7-965 (64bit x86-64) processor

for desktop PC
Process: 45nm
Clock speed: 3.33 GHz
731 million transistors
Cache 8MB
Addressable memory 64GB
263 mm2 die size

MOS Transistor Review
3-terminal device
______ input: the control input; its ______
determines whether _________ can flow
_____ & ______: terminals that current flows
from/to
Gate Gate
+1.2V Transistor Transistor
is on 0V
Source Drain Source Drain is off
- - High voltage at
-- Low voltage at
gate allows current
- - - Silicon
- to flow from source
to drain Silicon
gate prevents
current from
flowing from
source to drain

Fundamental Blocks: Logic Gates
All digital circuits are built from __________
(_______ controlled switches) which can be
on or off
The arrangement of transistors leads to a
few basic functions that express ________
operations
These constructs are known as ______ or
___________
L L
A
A B
Voltage B
Voltage
Source
Source
L = A and B L = A or B
Transistors in SERIES = AND Transistors in PARALLEL = OR

AND Gates
An AND gate outputs a 1 (true) if ______ inputs are

1 (true)
Gates can have several inputs
Behavior can be shown in a truth table (listing all
possible input combinations and corresponding output)
X Y Z F
0 0 0 0
X Y F 0 0 1 0
0 1 0 0
X 0 0 0 X
F F 0 1 1 0
Y 0 1 0 Y
1 0 0 0
1 0 0
F=XY Z
F=XYZ 1 0 1 0
1 1 1 1 1 0 0
1 1 1 1
2-input AND 3-input AND

OR Gates
An OR gate outputs a 1 (true) if ______ input is

1 (true)
Gates can also have several inputs
X Y Z F
0 0 0 0
X Y F 0 0 1 1
X 0 1 0 1
0 0 0 X
F F 0 1 1 1
Y 0 1 1 Y
1 0 0 1
1 0 1 Z
F=X+Y F=X+Y+Z 1 0 1 1
1 1 1 1 1 0 1
1 1 1 1
2-input OR 3-input OR
NOT Gate
A NOT gate outputs a 1 (true) if the input is 0

(false)
X F
1 0
X F
0 1
F=X

NAND and NOR Gates
X X
Z Z
Y Y
NAND NOR
Z X Y Z X Y
X Y Z X Y Z X Y Z X Y Z
0 0 0 0 0 1 0 0 0 0 0 1
0 1 0 0 1 1 0 1 1 0 1 0
1 0 0 1 0 1 1 0 1 1 0 0
1 1 1 1 1 0 1 1 1 1 1 0
AND NAND OR NOR
True if NOT ALL True if NOT ANY
inputs are true input is true
Shahin Nazarian/EE477L/Fall 2012

XOR and XNOR Gates
X X
Z Z
Y Y
XOR XNOR
Z X Y Z X Y
X Y Z X Y Z
0 0 0 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 1
True if an odd # of inputs are true True if an even # of inputs are true
= True if inputs are ___________ = True if inputs are ___________
Shahin Nazarian/EE477L/Fall 2012

Logic Functions
Map input combinations of n-bits to desired

m-bit output
Can describe function with a _______ table
and then find its circuit implementation
IN0 IN1 IN2 OUT0 OUT1
0 0 0 0 1
0 0 1 1 1
Inputs Logic Outputs
Circuit

1 1 1 0 0

Logic Circuits
___________ logic
Perform a specific function (mapping of 2n input
combinations to desired output combinations)
No internal state or feedback
Given a set of inputs, we will always get the
same output after some time (propagation) delay
____________ logic (Storage devices)
Registers made up of flip-flops/latches are the
fundamental building blocks
Controlled by a _______ signal
Sample data on a ______ edge and remember
that value until the next edge

Functions & Logic Networks
We can generate arbitrary logic
functions using multiple levels of logic X Y Cin Cout S
Example: Full Adder performs one 0 0 0 0 0
column of addition of two numbers

0 0 1 0 1
0 1 0 0 1
Adds a bit from each number plus a 0 1 1 1 0
carry-in from the previous column 1 0 0 0 1
and generates a sum bit & carry-out

1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Cout Cin 0 1
110 X Y
0110 = X
1 Cout Full Cin 0
Adder
+ 0111 = Y S
1101
Shahin Nazarian/EE477L/Fall 2012 0 19
Find patterns in the input combinations that

uniquely identify the rows where the output
is true
X Y Ci Co
0 0 0 0 X
0 0 1 0 Y
0 1 0 0
0 1 1 1 Co
Ci
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1 Level 1 Level 2

Decompose function into smaller sub-_____

that can easily be implemented. Then
recombine sub-_______ to create overall
function
X Y Ci Co XY XCi YCi
0 0 0 0 0 0 0 X
0 0 1 0 0 0 0 Y
0 1 0 0 0 0 0
0 1 1 1 0 0 1 Co
Ci
1 0 0 0 0 0 0
1 0 1 1 0 1 0
1 1 0 1 1 0 0
1 1 1 1 1 1 1 Level 1 Level 2

Functions with multiple outputs can be

generated by considering each output as a
separate function of the inputs
Example: A dedicated 4-bit adder
A3A2A1A0 = A A3 B3 A2 B2 A1 B1 A0 B0
+ B3B2B1B0 = B Cout Cin

S4S3S2S1S0 = S
S3 S2 S1 S 0

Combinational Functional Blocks
We can take our logic gates and build up a

set of commonly used functional blocks
Some common functional blocks include
_________
__________
________ (Arithmetic and Logic Units)

Example: Building a Mux
To build a Mux
Decode the _______ bits and include the
corresponding data input
Finally _______ all the first level outputs
together
0 1
1 0
I1 I0
1 0
1 0

Delay in Combinational Logic
Beyond the functionality, it is important to

understand the timing of logic circuits
Each gate (transistor) has inherent

_________ delay
________________ Delay = time from the
instant the inputs change until the output becomes
stable and correct
Delay of a circuit is proportional to the

longest ______ (chain) of gates from any
input to the output
Delay Example
Initial Values
1 P
0 C 0
1
1 P 0
0 0
1 R
1 V 0
0 B
0 T

Delay Example (Cont.)
1 P
1
0 C 0
1
1 P 1 0
0 1 0
1 R
0 1 V 1 0
0 B 4 Levels of Logic
0 T
Change in V, B, or T must propagate

through the 4 levels of logic

0
1 P 1 1
0 C 0
0 0
1
1 P 0
0 0
1 R
1 V 0
0 B 2 Levels of Logic
0 T
Change P must propagate

through only 2 levels of logic

Delay Example
Assume that we were adding one set of inputs
and then change to a new set of inputs:
Old inputs: 0000 New inputs: 1 _
1111 = X 1111 = X
+ 0000 = Y + 0001 = Y
1111 0000
1 0 1 0 1 0 1 0
X Y X Y X Y X Y
0 0 0 0
Cout Full Cin Cout Full Cin Cout Full Cin Cout Full Cin 0
Adder Adder Adder Adder
S S S S
1 1 1 1
At the time just before we enter the new

input values, all carries are 0s
New inputs: 1 _
1111 = X Time
+ 0001 = Y 0
0000
1 0 1 0 1 0 1 1
X Y X Y X Y X Y
0 0 0 0
S S S S
1 1 1 1
The first adder updates its carry and sum but
meanwhile other adders output incorrect values due to
the lack of correct carries
New inputs: 1 _
1111 = X Time
+ 0001 = Y 1
0000
Old inputs:
1 0 1 0 1 0 1 1
X Y X Y X Y 1 X Y
0 0 0 0
S S S S
1 1 1
0 0 0 0
The second adder updates its carry and sum

but later adders are still incorrect
New inputs: 1 _
1111 = X Time
+ 0001 = Y 2
0000
Old inputs:
1 0 1 0 1 0 1 1
X Y X Y 1 X Y 1 X Y
0 0 0 0
S S S S
0 1
1 1
0 0 0 0
The third adder is now correct but the last

adder is still incorrect
New inputs: 1 _
1111 = X Time
+ 0001 = Y 3
0000
Old inputs:
1 0 1 0 1 0 1 1
X Y 1 X Y 1 X Y 1 X Y
0 0 0 0
S S S S
0 1 0 1
1
0 0 0 0
Finally, all the adders are correct
New inputs: 1 _
1111 = X Time
+ 0001 = Y 4
0000
Old inputs:
1 0 1 0 1 0 1 1
1 X Y 1 X Y 1 X Y 1 X Y
0 0 0 0
S S S S
0 1 0 1 0 1
0 0 0 0
Sequential Devices (Registers)
___________ outputs are only a function of the
current inputs
Outputs only depend on what the inputs are right
now, not one second ago
This implies they have no memory (cant remember
a value)
_________ logic devices provide the ability to retain or
remember a value by itself (even after the input is
changed or removed)
Usually have a controlling signal that indicates when
the device should update the value it is
remembering vs. when it should simply remember
that value
This controlling signal is usually the _____ signal
Clock Signal
Alternating high/low voltage
pulse train
Clock Signal
Op. 1 Op. 2 Op. 3

Controls the ordering and 1 (5V)
timing of operations performed 0 (0V)
in the processor 1 cycle
2.8 GHz
= 2.8*109 cycles per second
Cycle measurement = 0.357 ns/cycle
Processor
# of cycles per second (e.g.
2.8 GHz = 2.8 * 109 cycles
per second)

D Flip-Flop
Fundamental sequential building block

q-output samples the d-input at the instant
of the rising clock _______ and then
retains that value until the next clock edge
Positive-Edge Triggered D-FF t = 0 ns t = 2 ns t = 6 ns t = 10 ns t = 14 ns
clk
d(t) D Q q(t)
d(t)
D-FF
Clock Signal
CLK q(t)
q(t) d(-2) d(2) d(6) d(10) d(14)

Positive-Edge Triggered D-FF
Q looks at D only at CLK D Q*

the positive-edge 0 x Q
1 x Q
0 0
1 1
CLK
Q only samples D at the positive edges and then

holds that value until the next edge
Registers
A Register is a group of D-FFs

tied to a common clock and 1
clear (reset) input

SET
D0 D Q Q0
CLR
_______ input allows 1
register to be initialized to D1 D
SET
Q Q1
0s CLR
Used to store multiple bit 1
values on each clock cycle

SET
D2 D Q Q2
CLR
1
CLK /AR Di Qi*
SET
D3 D Q Q3
X 0 X 0
CLR
1,0 1 X Qi
1 0 0 /AR
CLK
1 1 1
4-bit Register
Registers
Whatever the D value is at the clock

edge, is sampled and passed to the output
until the next clock edge
CLK
/AR
D[3 :0 ] 0010 0011 0100 0101 0110 0111 1000 1001 1010
Q[3 :0 ] 0000 0011 0100 0101 0110 0111 1000 1001
4-bit Register On clock edge, D is passed to Q

Clocking Methodologies
Typical designs use both combinational and sequential
logic
Sequential logic: saves and synchronize data
Combinational logic: performs some operation on
the data
Can use feed-forward or feed-back methodology
Inputs
Sequential Logic
Sequential Logic
Register
Inputs
Combo Combo Combo
Logic Logic Logic
Combinational Sequential
Logic CLK Logic CLK CLK
Manipulates Synchronizes &
(Processes) Data Save Data
Feed-forward Style Feed-back Style

Clocking Example
for(i=0; i < 100; i++)

C[i] = (A[i] + B[i]) / 4;
10ns per input set = 1000ns total

Feed-forward (Pipelining) Example
for(i=0; i < 100; i++)
C[i] = (A[i] + B[i]) / 4;
Stage 1 Stage 2
Stage 1 Stage 2
Clock 0 A[0] + B[0]
Clock 1 A[1] + B[1] (A[0] + B[0]) / 4
Clock 2 A[2] + B[2] (A[1] + B[1]) / 4
Need for Registers
Provides separation between combinational functions

Without registers, fast signals could catch-up
to data values in the next operation stage
5 ns
Signal i
Register
Register
Signal j
2 ns
CLK CLK
Performing an We dont want signals from two

operation yields different data values mixing.
signals with different Therefore we must collect and
paths and delays synchronize the values from
the previous operation before
passing them on to the next
Counter Example
Adder (+)
Register
Q
CLK

Evolution of minimum feature size
65nm 25nm ?nm
2005 2010 2015

Economic Impact
As a result of the continuously increasing

integration density and decreasing unit
costs, the semiconductor industry has been
one of the fastest growing sectors in the
worldwide economy
Moores Law
In 1965, Gordon Moore noted that the number of

transistors on a chip doubled every _________ months
He made a prediction that semiconductor technology
will double its effectiveness every 18 months

(Optional) Moores Law (Cont.)
Moore's original statement that transistor counts had doubled every year
can be found in his publication "Cramming more components onto integrated
circuits", Electronics Magazine April 19, 1965:
The complexity for minimum component costs has increased at a rate of
roughly a factor of two per year ... Certainly over the short term this
rate can be expected to continue, if not to increase. Over the longer
term, the rate of increase is a bit more uncertain, although there is no
reason to believe it will not remain nearly constant for at least 10 years.
That means by 1975, the number of components per integrated circuit for
minimum cost will be 65,000. I believe that such a large circuit can be
built on a single wafer 16
COMPONENTS PER INTEGRATED FUNCTION
15
14
13
LOG2 OF THE NUMBER OF
12
11
10
9
8
7
6
5
4
3
2
1
0
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
Evolution of Memory Capacity

Evolution in Complexity

Frequency and Voltage Trends

Delay Trend

Productivity Trends
(M)
10,000
10,000,000 100,000
100,000,000
1,000 Logic Tr./Chip 10,000
Logic Transistor per Chip
1,000,000 10,000,000
(K) Trans./Staff - Mo.

Tr./Staff Month.
100
100,000 1,000
1,000,000
Complexity
Productivity
58%/Yr. compounded
10,00010 Complexity growth rate
100
100,000
1,0001 10
10,000
x x
0.1
100 1
1,000
xx
x
21%/Yr. compound
x x Productivity growth rate
x
0.01
10 0.1
100
0.001
1 0.01
10
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2003
2005
2007
2009
Source: Sematech
Complexity outpaces design productivity
Courtesy, ITRS Roadmap

Die Cost
Single die
Wafer
Going up to 12 (30cm)
From http://www.amd.com
Cost per Transistor
cost:
-per-transistor
1
0.1 Fabrication capital cost per transistor (Moores law)
0.01
0.001
0.0001
0.00001
0.000001
0.0000001
1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012

Yield
No. of good chips per wafer
Y 100%
Total number of chips per wafer
Wafer cost
Die cost
Dies per wafer Die yield
wafer diameter/2 2 wafer diameter
Dies per wafer
die area 2 die area

Defects

defects per unit area die area
die yield 1

is approximately 3
die cost f (die area) 4

Some Examples (1994)
Chip Metal Line Wafer Def./ Area Dies/ Yield Die

layers width cost cm2 mm2 wafer cost
386DX 2 0.90 $900 1.0 43 360 71% $4
486 DX2 3 0.80 $1200 1.0 81 181 54% $12
Power PC 4 0.80 $1700 1.3 121 115 28% $53

601
HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73
DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149
Super Sparc 3 0.70 $1700 1.6 256 48 13% $272
Pentium 3 0.80 $1500 1.5 296 40 9% $417

Power Dissipation
Instantaneous power:
p(t) = v(t)i(t) = Vsupplyi(t)
Peak power:
Ppeak = Vsupplyipeak
Average power:
1 t T Vsupply t T
Pave p(t )dt isupply t dt
T t T t

Power Density
Example: Go to IKEA store and find a 500Watt light bulb with
the area of 50cm2. Ask the store manager to turn it ON if its
not
Cooling for 60W/cm2

A First-Order RC Network
Vdd
E0->1 = C LVdd2
R PMOS i
vout supply
A1 NETWORK
vAinN CVLout
CL
NMOS
NETWORK
T T Vdd
E 0 1 = P t dt = V dd i sup ply t dt = Vdd CL dV out = C L V dd 2

0 0 0
T T Vdd
1 2
E ca p = P cap t dt = V out i ca p t dt = C L Vout dVout = --- C V dd
2 L
0 0 0

Multi Layer VLSI
Cross-section of a 5 Layer Chip

Typical Chip Cross-section

ITRS (International Technology Roadmap
for Semiconductors)
ITRS (http://www.itrs.net/) is the fifteen-year assessment of
the semiconductor industrys future technology requirements.
These future needs drive present-day strategies for world-
wide research and development among manufacturers research
facilities, universities, and national labs without regard to any
commercial considerations pertaining to individual products or
equipment. The following areas are considered by ITRS:
System Drivers/Design Test & Test Equipment
Front End Processes Photolithography
IC Interconnects Factory Integration
Assembly & Packaging Environment, Safety & Health
Yield Enhancement
Metrology
Modeling & Simulation
Emerging Research Devices
Emerging Research Materials

ITRS Prediction

Shrinking Device Dimensions

Increasing Function Density

Increasing Clock Frequency

Decreasing Supply Voltage

System-on-Chip (SoC)
SoC Integrates (combines) all or most of the components of a
hybrid system on a single substrate (silicon or MCM), rather
than building a conventional printed circuit board
Advantages: More compact system realization, cost effective,
higher speed, performance and reliability
One of the best hopes to solve the productivity gap is
design reuse. Intellectual property (IP) blocks can be
purchased and used as black boxes within a SOC in much
the same way chips are purchased for a board-level design
Typical SoC components: controller/processor, Memory blocks,
oscillators, PLLs, some peripherals (counter/timer, real-time
timers, power-on reset generators, external interfaces e.g.
USB, FireWire, Ethernet, USART, SPI), ADC/DAC, voltage
regulators, & power-management systems

SoC (Cont.) [Optional] SiP
SoC components are connected by bus (proprietary or industry standard)

e.g., AMBA from ARM
If it is not feasible to construct an SoC for a particular application, an
alternative is a system in package (SiP) comprising a number of chips in a
single package. In large volumes, SoC is believed to be more cost effective
than SiP since it increases the yield of the fabrication and because its
packaging is simpler
Product Lifecycle Trend

VLSI Design Strategies

VLSI Design Strategies (Cont.)

The Y-Chart
There is a need for structured design methodologies to handle
the high level of complexity !

Simplified VLSI Design Flow

Simplified VLSI Design Flow (Cont.)

Structured Design Principles
Hierarchy: Divide and conquer technique involves
dividing a module into sub-______ and then repeating
this operation on the sub-______ until the ________
of the smaller parts becomes managable
Regularity: The hierarchical decomposition of a large
system should result in not only simple, but also
_______ blocks, as much as possible. Regularity usually
_______ the number of different modules that need to
be designed and verified, at all levels of abstraction
Modularity: The various functional blocks which make up
the larger system must have well-defined _______ and
_________
Locality: Internal details remain at the local level. The
concept of locality also ensures that connections are
mostly between ________ modules, avoiding
_________ connections as much as possible
VLSI Design Syles

Full-custom Design

Full-custom Design (Cont.)

Full-custom Design (Cont.)

Full-custom SRAM Cell Design

Mapping Design into Layout

Cell-based (HDL-based) Design

Cell-based Design (Cont.)

Standard Cells

Standard Cells (Cont.)



Mask Gate Array Design

Mask Gate Array Design (Cont.)

FPGA Design
Field Programmable Gate Array (FPGA)

FPGA Design (Cont.)
Structure of a CLB (configurable logic block)

FPGA Design (Cont.)
Detailed view of switch matrices and

interconnection routing between CLBs

Challenges in Digital Design
Microscopic Problems Macroscopic Issues

Ultra-high speed design Time-to-Market
Interconnect Millions of Gates
Noise, Crosstalk High-Level Abstractions
Reliability, Manufacturability Reuse & IP: Portability
Power Dissipation Predictability
Clock distribution etc.
etc.

Reliability Noise in Digital Integrated
Circuits
v( t) VDD
i( t)
Inductive coupling Capacitive coupling Power and ground

noise


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University of Southern California

Viterbi School of Engineering

Shahin Nazarian Fall 2012

BJT invention, Bell Labs, 1947

Ultra Large Scale Integration, 1989

Shahin Nazarian/EE477L/Fall 2012 2

Shahin Nazarian/EE477L/Fall 2012 3

Shahin Nazarian/EE477L/Fall 2012 4

Shahin Nazarian/EE477L/Fall 2012 5

The bipolar (point-contact) transistor was invented in December

Shahin Nazarian/EE477L/Fall 2012 6

ECL (Emitter Coupled Logic)

Shahin Nazarian/EE477L/Fall 2012 7

Shahin Nazarian/EE477L/Fall 2012 8

Intel Core i7-965 (64bit x86-64) processor

Shahin Nazarian/EE477L/Fall 2012 9

Shahin Nazarian/EE477L/Fall 2012 10

Transistors in SERIES = AND Transistors in PARALLEL = OR

An AND gate outputs a 1 (true) if ______ inputs are

2-input AND 3-input AND

An OR gate outputs a 1 (true) if ______ input is

A NOT gate outputs a 1 (true) if the input is 0

Shahin Nazarian/EE477L/Fall 2012 14

Shahin Nazarian/EE477L/Fall 2012

Shahin Nazarian/EE477L/Fall 2012

Map input combinations of n-bits to desired

IN0 IN1 IN2 OUT0 OUT1

Shahin Nazarian/EE477L/Fall 2012 17

Shahin Nazarian/EE477L/Fall 2012 18

Example: Full Adder performs one 0 0 0 0 0

column of addition of two numbers

carry-in from the previous column 1 0 0 0 1

and generates a sum bit & carry-out

Find patterns in the input combinations that

Shahin Nazarian/EE477L/Fall 2012 20

Decompose function into smaller sub-_____

Shahin Nazarian/EE477L/Fall 2012 21

Functions with multiple outputs can be

+ B3B2B1B0 = B Cout Cin

Shahin Nazarian/EE477L/Fall 2012 22

We can take our logic gates and build up a

Shahin Nazarian/EE477L/Fall 2012 23

Shahin Nazarian/EE477L/Fall 2012 24

Beyond the functionality, it is important to

Each gate (transistor) has inherent

Delay of a circuit is proportional to the

Shahin Nazarian/EE477L/Fall 2012 26

Change in V, B, or T must propagate

Shahin Nazarian/EE477L/Fall 2012 27

Change P must propagate

Shahin Nazarian/EE477L/Fall 2012 28

At the time just before we enter the new

The second adder updates its carry and sum

The third adder is now correct but the last

Finally, all the adders are correct

Op. 1 Op. 2 Op. 3

in the processor 1 cycle

Shahin Nazarian/EE477L/Fall 2012 36

Fundamental sequential building block

Positive-Edge Triggered D-FF t = 0 ns t = 2 ns t = 6 ns t = 10 ns t = 14 ns

q(t) d(-2) d(2) d(6) d(10) d(14)

Shahin Nazarian/EE477L/Fall 2012 37

Q looks at D only at CLK D Q*