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1s IEEE International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES-2016)

A Seven Level Multilevel Inverter Topology with

Improved Results using PWM Technique

l 2 3
Vanya Goel , Jagdish Kumar and Jaimala Gambhir
123
, , Department of Electrical Engg., PEC University of Technology Chandigarh, India

Abstraet-The new emerging multilevel inverter must be isolated from the semiconductor switches and the
topologies with reduced device count, better control other H-bridges, hence, a separate maximum power point
strategies, improved modulation schemes and capability to tracking (MPPT) charge controller is required to charge
address various operational issues have proved to be highly its storage batteries independently. Hence, a PV system
superior to that of two level inverters and the conventional
that uses the cascaded H-bridge multilevel inverter
multilevel inverter topologies. This paper presents
topology can be quite bulky and costly. Moreover, due to
significantly improved results of an existing 6 switches and 4
the intermittent nature of the renewable energy sources the
DC sources multilevel inverter topology to produce great
performance and efficiency of the muItilevel inverter may
perfection in the seven level output voltage waveform. The
deteriorate. For this, the output voltage quality of the MLI
major impact of the improved results is the reduction in total
harmonie distortion (THD). The control methodology is improved as the number of output voltage level
employed is Level Shifted PWM technique, based on which increase, reaching to that of the perfect sinusoid. Also, the
the topology is simulated for Phase Opposition Disposition, quantity and size of output filters can be reduced because
Alternate Phase Opposition Disposition and Alternate Phase of the reduction in the lower order harmonics content in
Opposition Disposition + Variable Frequency modulation the output voItage waveform. On the other hand, with
techniques. Multilevel Inverters today present a viable lesser number of levels, they need large sized as weil as
solution for high dynamie performance and power quality expensive LC output filters. A multilevel inverter offers
seeking applieations, ultimately focusing to achieve almost various advantages over a conventional two level inverter
perfect sinusoidal output voltage with minimum harmonie by employing a high switching frequency PWM which not
content. Thus, in this paper an effort is made to reduce the
only produces the output voItage with lower harmonic
THD in the output voltage waveform. An analysis is done
distortion, but also reduces dv/dt stresses, thereby
and a comparison is also made between the existing results
reducing electromagnetic compatibility (EMC) problems,
and the new results obtained. These results are verified using
these advantages will be elaborated later in this paper.
MATLAB/SIMULINK and the analysis of harmonie
Since, harmonics play a major role in context of power
spectrum is done through the Fast Fourier transform
window. electronics, their reduction is the primary motive in this
Keywords-Multilevel Inverters; New Topologies; Total paper so that the multilevel inverter topology can be
Harmonie Distortion; Level Shifted Multiearrier PWM applied to various high power quality seeking
Teehniques applications. To be known as a multilevel inverter, each
phase of the inverter should produce at least three different
I. INTRODUCTION voltages and this differentiates the conventional two-Ievel
voltage source inverter (2L-VSI) from the multilevel
The Conventional cascaded seven level multilevel
family. In this paper, the circuit is checked out using level
inverters utilize three DC sources and twelve switches [1]
shifted multicarrier PWM techniques [10]. Then
[6]. Many comparisons have been made by various
identifying the effectiveness by working the simulated
authors between the diode c1amped, tlying capacitor and
circuit with In-Phase Disposition (PD), Phase Opposition
the cascaded H-bridge MLI [7]-[8]. The main
Disposition (POD), Alternate Phase Opposition
disadvantage in these structures is that for higher levels of
the output voltage higher number of power switches is Disposition (APOD) PWM modulation schemes [11]-[12]
using MATLAB/SIMULINK.
required. Hence, improvement is required to lower the no.
of switches of the inverter. This topology utilizes four DC
11. TOPOLOGIES
sources and six switches and it produces the output
voltage waveform with significantly less harmonics as A. Canventianal Tapa/agy
compared to conventional cascaded multilevel inverter [9].
The fundamental concept of an MLI to generate near to Cascaded H-Bridge multilevel inverters are obtained
sinusoidal output voltage waveform is by using power by connecting in series more than two single phase H
electronic switches like IGBTs, MOSFETs, etc. along Bridge inverters each consisting of 4 switches, hence the
with appropriate DC voltage sources to perform the power name [13]-[14]. In general terms when connecting k H
conversion i.e. the DC to AC conversion. Capacitors, Bridges in series, 2k+1 different voltage levels are
batteries, and renewable energy voltage sources can be obtained and maximum output voltage kVdc Thus, for a
used as the multiple input DC sources. Since the batteries seven level inverter it uses 3 H-Bridges in series hence a

978-1-4673-8587-9/16/$31.00 2016 IEEE [1)

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1s IEEE International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES-2016)

total of 12 switches and maximum output voItage of 3Vdc. T ABLE I: SWITCHING STATES OF 6-SWITCH 4 OC SOURCE TOPOLOGY
It is important to note that the two switches connected in Sr. No. S] S2 S3 S4 SS S6 Vo
the same leg must not conduct at the same time in order to 1. 0 0 I 0 I 0 Vdc
prevent a complete short circuit. Fig. 1 represents the 2. 0 I 0 0 I 0 2Vdc
Conventional Cascaded H bridge inverter. 3. I 0 0 0 I 0 3Vdc
4. 0 0 0 0 0 I 0
5. I 0 0 I 0 0 -Vdc
6. 0 I 0 I 0 0 -2Vdc
7. 0 0 I I 0 0 -3Vdc
Vdel Where,O refers to OFF; I refers to ON .

III. METHOOOLOGY USEO

In order to realize the muItilevel inverter topology, a

VdeZ
Vdc3
Fig. I: Cascaded H-bridge Structure for Seven- Ievel Multilevel Inverter
B. 7 Level 6 Switch Tapalagy
This topology uses 4 dc voItage sources and 6
switches as shown in Fig. 2. Switches SI, S2, S3 are
utilized for producing levels while switches S4, S5 are
utilized for reversing the polarity [15]. The switch S6 is
connected across the load for obtaining zero level. Table 1
represents its switching sequence. In this topology the
number of switches and percentage of THD produced is
much lesser as compared to the conventional and other
existing 9 switch, 7 switch topologies. 2 switches conduct
in the positive half cycle and two switches conduct for the
negative half cycle and one switch for generating zero
level. Here, level shifting PWM technique is used.
Fig. 2: Seven Level 6 Switch Multilevel Inverter Topology
particular control strategy needs to be used. There are
many controlling schemes in literature; one of these is the
modulation technique that can be c1assified based on the
switching frequency. These include: fundamental
switching frequency, where, each inverter in one cycle
undergoes one commutation, e.g. Selective Harmonic
Elimination (SHE), Space Vector Control (SVC) and
Nearest VoItage Level Control (NVLC) and high
switching frequency modulation technique where, in one
cycle the inverter undergoes several commutations, e.g.
PWM technique and Space Vector Modulation (SVM).
One of the simplest methods of obtaining voItage
source modulation is through intersecting a modulating
signal which is mostly a sine wave with triangular carrier
waveform. This scheme is explained as in carrier based
PWM technique [16]. MuIticarrier PWM Techniques can
be categorized in two groups i.e.; Level Shifted methods
(LS) and Phase Shifted (PS) PWM methods [17], latter
produces higher amount of total harmonic distortion as
compared to former. Therefore, Level Shifted PWM
technique is considered [18].
Level shifting technique is further categorized into
three techniques which are: In-Phase Disposition (PD),
Phase Opposition Disposition (POD), and Alternate Phase
Opposition Disposition (APOD) [19]-[20]. When using
level shifted PWM technique, an 'N' level inverter uses
'N-l' carrier waves such that the 'N-l' triangular carriers
are vertically displaced and the bands they occupy are
equally spaced. Moreover, along with the vertical
displacement there is also phase reversal between the
triangular carriers. In-Phase Disposition (PD) involves all
the carriers in phase [21], which when compared with the
sinusoidal reference produce the desired pulses.
Appropriate comparisons are made and according to the
desired pulse pattern, the logical circuits are used. The
pulses thus obtained are fed to the power electronic
switch, in this case, MOSFET and the desired seven level
output voItage waveform is obtained.
In this paper, for e.g. in order to obtain "Vdc" voItage
level, switches S3 and S5 should be ON, thus we now
know the desired pulse pattern. To achieve this pattern,
comparisons are made between the sinusoidal reference
and the triangular carriers and if desired additional logical
circuits can be used.

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1s IEEE International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES-2016)

Here, the same topology is simulated for POD, APOD

and APOD+VF modulation technique and the desired
seven level output voItage waveform is obtained.
In the case of Phase Opposition Disposition (POD)
[22] as shown in Fig. 3, all the triangular carriers above
zero reference are in same phase whereas those below zero
reference are 180 degrees out of phase.
1 ID
'0

Ci
E
'"

ID
'0

Ci
E
'"
0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
time(secs)

Fig. 5: APOD+VF PWM Technique

IV. SIMULATION RESULTS

The above discussed 7 level 6 switch topology is

simulated based on the POD, APOD, APOD+VF PWM
0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
technique and the harmonie spectrum is analyzed using
time(secs)
MATLAB/ Simulink.
Fig. 3: POD PWM Technique The amplitude of the dc source is taken as lOV and
load resistance is 10 ohms. MOSFET block parameters are
Each carrier is 180 degrees in phase difference with
as folIows:
its neighboring carrier in Alternate Phase Opposition
FET resistance= O.Olohms
Disposition (APOD) as shown in Fig. 4.
1 ---- Internal Diode Resistance =lOkilo ohms
The resuIts we obtained are shown in Fig. 6, Fig. 7
and Fig. 8.
Selected sig nal: 5 cycles. FFT window (in red): 3 cycles

ID
'0
:
Ci
E
'"
::r\/\l\l\/\J
o 0.02 0.04
Tim", (c;\
0.05 0.08 0.1

- FFT analysis-------
Fundamental (50Hz) = 27.3 THD= 15.77%

100
ro
c 80
CI)

E
rn
"0
c 50
:::0
CL
-0 40
>R-
0

'" 20
Fig. 4: APOD PWM Technique
rn

0 _I. .I. ... J. _0.
In APOD+VF technique each carrier wave is 0 200 400 500 800 1000
Frequency (Hz)
displaced to its adjacent carrier wave by 180 degrees [23]
[24], such that the carrier frequency of the lower most and Fig. 6: FFT Analysis of 7-Level 6-Switch Topology using
the uppermost carrier waves is appropriately increased as POD PWM Technique
shown in Fig. 5.

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1s IEEE International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES-2016)

Selected signal: 5 cycles. FFT window (in red): 3 cycles

Based on the above simulation results, it can be seen

: r\7\7\1\7\J
that the percentage THD obtained in the seven-Ievel
multilevel inverter topology is lesser than that of the
results given in the reference [25].
A detailed comparison is made based on the above
o 0.02 0.04 0.06 0.08 0.1
Tjmp (,.,) THD analysis for POD, APOD and APOD+VF
-FFT analysis ------ modulation technique as shown in Table 2.
Fundamental (50Hz) = 28.46 , THD= 14.61% A comparison of the THD of the obtained results and
100 -r-----,
various other existing multilevel inverter topologies are
C
Q)
80 shown in Table 3.
E
60 TABLE 3: PERCENTAGE THD COMPARISON OF DIFFERENT TOPOLOGIES

LL
40 PWM Technique PD POD APOD APOD+VF
'
Cascaded 7-level 24.26 23. 13 22.46 -
'" 20
'" 7 level 9 switch - 20. 52 - -
:2
J. _ .. _I _.-
7 level 7 switch symmetrical - 18. 15 - -
200 400 600 800 1000
7 level 7 switch asymmetrical - 15.79 - -
Frequency (Hz)
7 level 6 switch 4 dc source - 16.77 14.76 10. 35
Fig. 7: FFT Analysis of 7-LeveI 6-Switch Topology using APOD PWM 7 level 6 switch 3 dc source - 15. 91 - -
Technique
7 level 6 switch asymmetrical - 18.69 - -
Selected signal: 5 cycles. FFT window (in red): 3 cycles
Thus it can be seen from Table 2 that the proposed

J\1\1\7\1\J
results are better than the existing results such that for
Phase Opposition Disposition PWM technique, the
percentage THD in the existing results is 18.25% and that
o 0.02 0.04 0.06 0.08 0.1 in the proposed results is 16.77%, for Alternate Phase
Tjm (r' Opposition Disposition PWM technique, the percentage
-FFT analysis ------
THD in the existing results is 16.48% and that in the
Fundamental (50Hz) = 30.46 , THD= 10.35%
100 -r------
proposed results is 14.61%. Hence, the proposed results
'" are significantly better than the existing results. Moreover,
C 80
E in the reference [25], the topology is not simulated for
60 Alternate Phase Opposition Disposition + Variable

LL
-
Frequency PWM technique, but, in this paper the topology
0 40
is simulated for this PWM technique and the percentage

'" 20 THD thus obtained is 10.35%. Hence, it is worth
mentioning that the percentage THD is minimum for
I". .. _ ..
200 400 600 800 1000
Alternate Phase Opposition Disposition + Variable
Frequency (Hz)
Frequency PWM technique, which in the case of
Fig. 8: FFT Analysis of 7-LeveI 6-Switch Topology using APOD+VF multilevel inverters is a significantly good result.
PWM Technique The multilevel approach for DC to AC conversion
offers many advantages such as:
V. COMPARISON OF RESULTS
The staircase waveform not only exhibits an
TABLE 2: COMPARISON OF THD OF SEVEN LEVEL SIX SWITCH
improved harmonie profile but also the dv/dt
TOPOLOGY BETWEEN EXISTlNG RESULTS AND PROPOSED RESULTS
stresses are greatly reduced. Thus, minimizing
Sr. Topology Existing Proposed
the filter size or even eliminating filter
No. Results% Results%
THD 1251 THD
requirement and at the same time electromagnetic
I. Seven level six switch topology 18.25% 16.77% compatibility problems can be addressed.
with 4 DC source using Phase MLI produces much lesser stress in the bearing
Opposition Disposition PWM
of a motor because the common mode voltage
technique
2. Seven level six switch topology 16.48% 14.61% produced is much smaller when the motor is used
with 4 DC source using Alternate in a multilevel motor drive application
Phase Opposition Disposition Renewable energy sources such as solar PV cells,
PWM technique
3. Seven level six switch topology 10.35% wind energy and fuel cells can be readily
with 4 DC source using Alternate incorporated in the multilevel converter
Phase Opposition Disposition +
technology and the input sources can be
Variable Frequency PWM
technique controlled for equal load sharing.

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1s IEEE International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES-2016)

VI. CONCLUSION [12] L. M. Tolbert, F. z. Peng, and T. G. Habetier, BMultilevel converters

for large electric drives,[ IEEE Trans. Ind. Appl. , vol. 35,
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gaining importance for low, medium and high power [13] Rodriguez, J. ; Franquelo, L. G. ; Kouro, S. ; Leon, J. I. ; Portillo, R.C. ;
applications, a dedicated research is required with Prats, M. AM. ; Perez, M. A;,"Multilevel Converters: An Enabling
Technology for High-Power Applications," Proceedings of the
minimum devices such that cost is minimized and
IEEE, vo1.97, nO. 1I, pp. I786- 1817, Nov. 2009.
performance is improvised. Thus, in this paper an effort is
[14] Rodriguez, J. ; Bernet, S. ; Wu, B. ; Pontt, J. O. ; Kouro, S. ;,
made to improve the performance of the inverter which "Multilevel Voltage-Source-Converter Topologies for Industrial
can be seen from the harmonie analysis done by Medium-Voltage Drives," Industrial Electronics, IEEE
successfully simulating the circuitry using Transactions on, vo1.54, no.6, pp.2930-2945, Dec. 2007.

MATLAB/SIMULINK. Minimum THD is obtained by
using APOD+VF hybrid muIticarrier PWM technique
which is significantly less than that of conventional
topology and other existing topologies. However, with the
continuous technological advancements and
emergence of various industrial applications, it opens new
challenges and opportunities that would motivate further
development in the field of muItilevel inverter technology.
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[5)