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(c)
(a)
(b)
Problem 2. Draw a circuit to realize each of the expressions using AND gates,
OR gates and Invertors.
a.
b.
c.
d.
Problem 3. Make a truth table, and then a Karnaugh map for the expression
indicated. Then develop the minimum sum of products form.
a. Do this for W, the output of problem 2a.
b. Do this for Z, the output of problem 2d.
Problem 4.
Problem 5. In the truth table below, the inputs are A, B, C, and D. Use a
Karnaugh map to come up with a minimum sum of products form when:
a. the output is W
b. the output is X
c. the output is Y
d. the output is Z
Input Output
D C B A W X Y Z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 1 0
0 0 1 0 0 1 0 1
0 0 1 1 0 0 0 0
0 1 0 0 1 1 1 0
0 1 0 1 1 0 1 1
0 1 1 0 1 0 0 0
0 1 1 1 1 1 0 1
1 0 0 0 1 1 0 1
1 0 0 1 1 0 0 0
1 0 1 0 1 0 0 1
1 0 1 1 1 1 0 0
1 1 0 0 0 0 X X
1 1 0 1 0 1 X X
1 1 1 0 0 1 X X
1 1 1 1 0 0 X X
Inputs Output
Digit (7
D C B A Segments)
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
Problem 8.
a. Repeat the previous problem for segment b.
b. Repeat the previous problem for segment c.
c. Repeat the previous problem for segment d.
d. Repeat the previous problem for segment e.
e. Repeat the previous problem for segment f.
f. Repeat the previous problem for segment g.
Problem 9. The flip-flops in the drawing below are positive edge triggered D
flip-flops. Let Q2, Q1, Q0 = 0,0,0 initially.
a. Plot the clock, Q2, Q1 and Q0 until the outputs begin to repeat.
b. Show that the circuit acts as a counter.
Problem 10. The flip-flops in the drawing below are negative edge triggered J-
K flip- flops. Let Q2, Q1, Q0 = 0,0,0 initially.
a. Plot the clock, Q2, Q1 and Q0 until the outputs begin to repeat.
b. Show that the circuit acts as a counter.
c. What advantage does this circuit have over the previous one? (It has
nothing to do with being negative edge triggered rather than positive
edge triggered)
Problem 11. The flip-flops in the drawing below are positive edge triggered D
flip flops. Let Q2, Q1, Q0 = 1,0,0 initially. Plot the clock, Q2, Q1 and Q0 until
the outputs begin to repeat.