VHDL IMPLEMENTATION OF TMDS ENCODER FOR THE

TRANSMISSION OF VIDEO SIGNALS IN SERIAL COMMUNICATION

I. INTRODUCTION

Digital visual interface transmitter and receiver in a multimedia system allow for
transmitting of high definition video and audio data between the source and the
receiver across a serial link at high speeds. This project highlights a detailed
development of digital visual interface (DVI) transmitter and receiver in
multimedia system. These include developing the architecture DVI receiver and
transmitter, high speed serialize, clock and data recovery circuits and deserializer
through the efficient use of FPGA resources. The project makes use of TMDS
(Transition Minimized Differential Signaling) technique, that involves advanced
TMDS encoding and decoding algorithms using DC balanced transmission, and
helps reducing EMI over the transmission lines.
 II. LITERATURE REVIEW
1. Paper Name- Review: Design And Implementation Of Reed Solomon
Encoder And Decoder
Author Name- Harshada l. Borkar1, prof. V.n. Bhonge2

From This Paper I Refer-

The design of encoder and decoder is described in VHDL and will be implemented
on Spartan 6 FPGA device using Xilinx software. The RS Decoder corrects a
symbol, by replacing the incorrect symbol with the correct one, whether the error
was occurred in one bit or all of the bits. Thus, if a symbol is wrong, it might as
well be wrong in all of its bit positions and hence because of this reason RS codes
have tremendous burst noise advantages over binary codes [15]. For reliable
communication in the presence of noisy channel efficient error detection and
correction techniques are shown in this paper. RS codes can be extended or
shortened because they are based on the finite fields. Reed Solomon codes provide
a wide range of code values that can be chosen to optimize the performance. RS
codes have wide application and are used in Wireless Communication such as
mobile phones, microwave links, in Deep Space and Satellite Communications
Networks, mass storage devices such as hard disk drives, DVD, barcodes and
Broadband Modems (ADSL,VDSL, SDSL, HDSL etc).

2. Paper Name- Design of Ultra Low Power TMDS Encoder using QCA
(Quantum Cellular Automata) for Nanoscale Communications
Author Name- Skandha Deepsita S.

From This Paper I Refer-

The design under consideration, i,e TMDS encoder is said to be area effective
when designed with QCA rather than CMOS. As there is an advantage of both low
area and power at the same abstraction level, QCA can be seen as one of the
promising technologies in near future. However there is still research going on in
the inter disciplines of physical implementations and cost effective manufacturing
process.

3. Paper Name- Speed Optimized Design of Serial Front Panel Data Port
(SFPDP) Protocol
Author Name- Sushma Pondugala

From This Paper I Refer-

This paper presents design and realization of Serial Front Panel Data Port (SFPDP)
protocol for high speed data transfer. To communicate with any device must and
should there is a need of protocol either it may be serial communication or parallel
communication. This paper discuss about the serial communication protocol which
is serial front panel data protocol (SFPDP). The design should be modeled using
VHDL language. In the paper the transmitter and the receiver should be designed
using finite state machines. The frame format of the design contains IDLE ,START
OF FRAME, DATA, FIRST END OF FRAME ,SECOND END OF FRAME and
GO STOP states. Based on this frame format fields the FSM should be designed.
Each Frame is recognized by a specified 32 bit hexadecimal pattern. In this paper
the Xilinx ISE EDA\ Tool is used for synthesis and Modelsim is used for
simulation.
 4. Paper Name- VHDL Implementation of optimized ADPLL and TMDS
encoder for serial communication.
Author Name- Supreetha Rao1, Kiran Kumar V.G2

From This Paper I Refer-

ADPLL is a modified PLL (phase locked loop) which is designed using all digital
block for the processing. Its operation is analogous to that of the PLL. It finds
range of applications in the field of real time analog signals which synchronizes the
phase information. In this project, we propose a novel design of ADPLL which
should operate in synchronous with TDMS for data serialization. To obtain better
accuracy the ADPLL building blocks such as loop filter are implemented with the
new method in the digital domain.

5. Paper Name- Communication Protocols Augmentation in VLSI Design

Applications

Author Name- By Kanhu Charan Padhy

From This Paper I Refer-

With the advancement in communication System, the use of various protocols got
a sharp rise in the different applications. Especially in the VLSI design for FPGAs,
ASICS, CPLDs, the application areas got expanded to FPGA based technologies.
Today, it has moved from commercial application to the defence sectors like
missiles & aerospace controls. In this paper the use of FPGAs and its interface with
various application circuits in the communication field for data (textual & visual)
& control transfer is discussed. To be specific, the paper discusses the use of FPGA
in various communication protocols like SPI, I2C, and TMDS in synchronous
mode in Digital System Design using VHDL/Verilog.
 III. METHODOLOGY

Fig No 01 TMDS (Transmitter-Receiver) block diagram

DVI block diagram is as shown in the fig.1 DVI cable and connectors carry four
differential pair that makes up the TMDS data and the clock channels. These
channels are used to carry the audio, video and the control data. The DVI system
consists of a transmitter and receiver, the transmitter encodes and serially transmits
a digital data stream over the twisted pair of wires to a receiver. The audio, video
and auxiliary data are carried by the three data channel of the TMDS. The video
pixel clock is transmitted on the TMDS clock channel and is used by the receiver
as the frequency references for the data recovery on the three TMDS data channels.
Each pixel has three colors, respectively, transmitting through three data channels
at the same time, and each color has 8 bit source word ranging from 0-255. The
encoded process for the active data can be viewed as a two stage procedure. The
procedure converts 8bits per channel into the 10 bit DC balanced, transition
minimized sequence which is then transmitted serially across the pair at a rate of
10bits per pixel clock period. The TMDS Clock channel carries a character ratio
frequency reference. The receiver/decoder produces bit-rate sample clock based
upon this reference, which is adjusted for each of the data streams, enabling proper
decoding. the basis of the 10th bit depending on the encoder the necessary steps are
taken at the decoder in the sink. The table.1 depicts few examples of the data taken
as the input, when the data is long transition less series automatically an transition
is introduced by the encoder. The 10bit data obtained is then transmitted over the
serializer provide to the CML for the transmission of the data through the links.
 IV. SPECIFICATION
1. Video transmission over the TMDS channel is logically divided into an
encoder, serializer and I/O circuit stage, the pixel data is 8 bits wide, while
the control data is 2 bits wide.
2. The encoder must produce 10-bit words from 8-bit words, which occurs
only for the pixel data. For control data, fixed 10 bit data is generated.
3. The serializer converts the parallel data to serial on all three streams and
then send them out onto three channels of differential output pair CML
(current mode logic) since I/O circuit is differential two wires are required
for each channel.
V. ADVANTAGES
1. The project makes use of TMDS (Transition Minimized Differential
Signaling) technique, that involves advanced TMDS encoding and decoding
algorithms using DC balanced transmission, and helps reducing EMI over
the transmission lines.
 VI. DISADVANTAGES
1. The conventional analog video graphics array (VGA) standard has been
replaced by the standard digital visual interface (DVI) with the evolution of
the display technology.
2. Digital multimedia interface made use of LVDS technology, in the LVDS
technology cable length was limited to short distance.
3. The proposed work makes use of TMDS technology with TMDS encoding
and decoding algorithms to overcome the drawbacks of the LVDS
technology

VII. APPLICATIONS

o KVM switches
o A/V receivers

o DVI/HDMI extenders

o Televisions/PC monitors/projectors
 VIII. PHASE WISE PLAN

Schedule Date Project Activity

July 1st Week 01/07/2016 Formation Of Project Group
2nd Week 08/07/2016 Project Topic Selection
3rd Week 15/07/2016 Synopsis Submission
August 1st Week 05/08/2016 Presentation On Project Ideas
2nd Week 12/08/2016 Submission Of Literature Survey
3rd Week 19/08/2016 Feasibility Assessment
September 1st Week 02/09/2016 Mid Sem Presentation
3rd Week 16/09/2016 Design Of Mathematical Model
4th Week 23/09/2016 End Sem Presentation.
October 1st Week 07/10/2016 Report Preparation And Submission
December 3rd Week 19/12/2016 1st module presentation
4th Week 26/12/2016 Discussion and implementation of 2nd
module
January 1st Week 02/01/2017 Preparation for ANEC conference
2nd Week 09/01/2017 Study of Algorithm to implement.
3rd Week 16/01/2017 Discussion about modification to
Improved for algorithm
4th Week 23/01/2017 1st and 2nd module presentation
5th Week 30/01/2017 Discussion on flow of project and
designing new module
February 1st Week 06/02/2017 Modification of modules.
2nd Week 13/02/2017 Designed test cases for our module.
 3rd Week 20/02/2017 Worked on user interface.
March 1st Week 06/03/2017 Integration of all modules.
3rd Week 20/03/2017 Final Report and presentation.

REFRENCES

[1] Digital Visual Interface, Revision 1.0, Digital Display Working Group,
http://www.ddwg.org.

[2] Design and implementation of high definition multimedia interface transmitter

and receiver, International Journal of Advanced Technology & Engineering
Research (IJATER)

[3] Al Widmer, Peter Franaszek, A DC-Balanced, Parti-tioned-Block, 8B/10B

Transmission Code IBM

[4] Journal of research and development, Volume 27, Number 5, Septem-ber 1983.