IP Development at UTS

IP development at UTS
IP core development - FPGA verified RTL
VLSI & Embedded group

Unistring Tech Solutions Pvt Ltd
1
VLSI & Embedded group, UTS www.unistring.com
Agenda
Security IP developed at UTS
Communication IP developed at UTS
Embedded system IP developed at UTS
Efforts by UTS towards parameterized models
RTL design flow case studies
2
FPGA tested Encryption and decryption
Security
algorithms
AES
Area optimized AES
Comm sys
IDEA
SHA
Blowfish
Embedded sys
Scalable encryption algorithm
XTEA
3
Work under progress
Security
Network intrusion detection architecture Comm sys
Hardware based packet filtering platform

with customizable front end.
Embedded sys
4
AES
Security
Comm sys
Embedded sys
5
AES
Security
Round structure
Comm sys
Embedded sys
6
AES
Security
Top level block diagram
Comm sys
Embedded sys
7
AES
Security
Comm sys
Embedded sys
8
AES
Security
Comm sys
Embedded sys
9
IDEA
Security
Comm sys
Embedded sys
10
IDEA
Security
Comm sys
Encryption
Embedded sys
11
IDEA
Security
Comm sys
Decryption
Embedded sys
12
IDEA 64 bit Plain text
Security
General round -1 of IDEA
Sub keys

Sub keys
Comm sys
Sub keys
Direct
implementation Sub keys

Sub keys
Sub keys General round -6 of IDEA
Embedded sys
Sub keys
Sub keys Final Round of IDEA
64 bit cypher text
13
IP development at UTS 64 bit Plain text
Shift reg
IDEA Sub keys

rst
Security
clk Shift reg

rst Shift reg
clk

rst Shift reg
clk
Comm sys

rst Shift reg
clk
Pipelined Sub keys General round - 5 of IDEA

version rst
clk Shift reg
Sub keys General round 6 of IDEA

rst
Embedded sys
clk Shift reg

rst Shift reg
clk
Sub keys General round-8 - of IDEA

rst Shift reg
clk
Sub keys Final Round of IDEA

clk Shift reg
14
VLSI & Embedded group, UTS 64 bit cypher text www.unistring.com
IDEA
Security
Comm sys
Serial
Architecture
Embedded sys
(area/power optimized)
15
IDEA
Security
Simulation results
Comm sys
Embedded sys
16
IDEA
Security
Synthesized to Xilinx FPGA
Comm sys
Embedded sys
17
IDEA
Security
Comm sys
Tested on chip with chipscope

Embedded sys
18
SHA
Security
Comm sys
Embedded sys
19
SHA
Security
Comm sys
Embedded sys
20
SHA
Security
Comm sys
Embedded sys
21
SHA
Security
Comm sys
Embedded sys
22
SHA
Security
Performance on XC3S500E
Max. frequency of operation: 74.845 MHz

Device utilization (area): 42% of XC3S500E
Comm sys
Tested on board with chipscope
Embedded sys
23
Blowfish
Security
FPGA proven core
Contact us for more details
Comm sys
Embedded sys
24
SEA Scalable encryption algorithm
Security
FPGA proven core
Comm sys
Embedded sys
25
XTEA
Security
Extended tiny encryption algorithm
FPGA proven core
Comm sys

Embedded sys
26
Communication system related IP
Security
NCO based digital frequency synthesis (DFS)
CORDIC based DFS
STBC (space time block code)
Comm sys
Noise and fading models
Secured arithmetic coding
CDMA modulator and demodulator block set
Convolution encoder viterbi decoder
Embedded sys
Telemetry link with manchester coding and
BFSK
Programmable modulator built around CORDIC
27
Communication system related IP
Differential QPSK MODEM Security
Golay encoder and decoder

Comm sys
Few blocks of OFDM

FFT
FIR filters
IIR fitlers
Embedded sys
Distributed arithmetic core
28
In progress
Security
Digital down converter
CIC filters
Comm sys
Monobit FFT
FHSS transmitter and receiver
Direction finding systems
Embedded sys
29
DFS-Digital frequency synthesis
Security
Comm sys
Embedded sys
30
Security
Comm sys
Embedded sys
31
ASK
Security
Comm sys
Embedded sys
32
DFS
Security
Comm sys
Embedded sys
33
Results from FPGA with chipscope DFS
Security
Comm sys
Embedded sys
34
Security
Comm sys
Embedded sys
35
CORDIC
RTL design Security
Comm sys
Embedded sys
36
CORDIC
Security
Comm sys
Embedded sys
37
CORDIC
Phase Accumulator Security
Frequency modulating Phase
bits modulating bits
Delta Frequency Phase Phase phase shift

Comm sys
Phase shift keying increment register keying

8 8 8
controller register controller
Modulation
Mod
Command
command
processor CORDIC Amplitude
8
Q
for modulating bits signal
SIN & COS
Embedded sys
amplitue
rst Clock and shift keying
Master control controller
clock generation Synthesized
circuit signal
Universal modulator built around CORDIC
38
CORDIC
Security
Comm sys
Embedded sys
Simulation results
39
CORDIC
Security
Comm sys
Embedded sys
Tested in Spartan 3E FPGA with chipscope

Simple SIN function generation
40
CORDIC
Security
Comm sys
Embedded sys
Modulating signal (4 bit data)
Tested in Spartan 3E FPGA with chipscope

16 level QAM modulation
41
STBC Space time block codes
Security
Comm sys
Embedded sys
42
STBC
Security
Comm sys
Embedded sys
43
STBC
Security
Comm sys
Embedded sys
44
STBC
Security
Comm sys
Embedded sys
Decision
matrices
45
CDMA block set
Security
Code division multiple access (CDMA) block set
PN sequence generators
Gold code generators
Comm sys
ML sequence generators
Spreader for DSSS
BPSK modulator
BPSK demodulator
Embedded sys
Matched filter
accumulate and sample unit
GPS frame generator
CORDIC/LUT based signal generators
46
PN sequence gen
Security
Comm sys
Embedded sys
47
PN sequence gen
Security
Comm sys
Embedded sys
48
CDMA
Security
Comm sys
Embedded sys
49
CDMA
Security
Comm sys
Embedded sys
50
CDMA
Security
Comm sys
Embedded sys
51
CDMA
Security
Comm sys
Embedded sys
52
CDMA
Security
Comm sys
Embedded sys
53
DQPSK
Security
010
011 001
000
100
Comm sys
101
111
110
Embedded sys
54
DQPSK
Security
Comm sys
Embedded sys
55
DQPSK
Security
x = (wk * wk_1) + (zk * zk_1);
y = (zk * wk_1) - (wk * zk_1);

Comm sys
Embedded sys
Differential detection non coherent
56
DQPSK
Security
MATLAB
Comm sys
Embedded sys
57
Running in hardware DQPSK
Security
Comm sys
Embedded sys
58
Noise and fading Simulator in FPGA
distance
In Counter
signa reg reg reg reg reg reg reg reg

l
LUT LUT LUT LUT LUT LUT LUT

Gaussian Gaussian Gaussian Gaussian Gaussian Gaussian Gaussian
Co-efff Co-efff Co-efff Co-efff Co-efff Co-efff Co-efff
Attenuation
Value
0 Rayleigh/Rician selector
Gaussian
noise
generator
Signal effected with

fading and noise 59
Tx Rx
V
effect due to fading with single reflector

IP development at UTS Resultant
Input signal Reflected signals noise
signal
61
Embedded Sys related IP
Multichannel UART Security
CAN bus interface

I2C bus interface
Comm sys
SPI bus interface

Interrupt controller
Scaled ARM7
Train communication network
Embedded sys
62
Embedded Sys related IP
Security
VGA
Debug data compressor
Logic signal analyzer
Comm sys
FPGA based Virtual computer for industrial automation
Embedded sys
63
Embedded systems on going work
HIL simulation core

High speed software defined radio front
end (DDC and CIC in FPGA)
64
Scaled ARM7 softcore
Reg File
Controller
MUL
Barrel Shifter
ROM
ALU
65
Scaled ARM7 softcore
66
Design approach for IP development
Algorithm simulation in C/MATLAB/OCTAVE

Evolving high level design for RTL
Re-simulating the C/MATLAB/OCTAVE code (if
required)
Designing micro-architecture for each block
VHDL/Verilog coding for each block.
Testing the blocks with suitable testbenches
67
Design approach for IP development
Integration of modules and testing with top level test

benches.
Using MATLAB or C codes to generate suitable test data
Performing timing simulation and checking the design for
the targeted specs.
Re-coding few blocks to improve performance (if required)
Modifying the top level test bench for on-chip testing
Testing on FPGA with chipscope for the targeted high
frequency of operation
Documenting the IP with design details and results
68
Thank you
69

IP Development at UTS

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IP development at UTS

IP core development - FPGA verified RTL

VLSI & Embedded group

FPGA tested Encryption and decryption

Hardware based packet filtering platform

General round -2 of IDEA

General round -5 of IDEA

Sub keys General round -6 of IDEA

Sub keys General round -8 of IDEA

Sub keys Final Round of IDEA

64 bit cypher text

IP development at UTS 64 bit Plain text

IDEA Sub keys

Sub keys General round -2 of IDEA

Sub keys General round -3 of IDEA

Sub keys General round -4 of IDEA

Pipelined Sub keys General round - 5 of IDEA

Sub keys General round 6 of IDEA

clk Shift reg

Sub keys General round -7 of IDEA

Sub keys General round-8 - of IDEA

Sub keys Final Round of IDEA

Tested on chip with chipscope

Max. frequency of operation: 74.845 MHz

Contact us for more details

Differential QPSK MODEM Security

Golay encoder and decoder

Few blocks of OFDM

Distributed arithmetic core

Delta Frequency Phase Phase phase shift

Phase shift keying increment register keying

Universal modulator built around CORDIC

Tested in Spartan 3E FPGA with chipscope

Tested in Spartan 3E FPGA with chipscope

x = (wk * wk_1) + (zk * zk_1);

y = (zk * wk_1) - (wk * zk_1);

Differential detection non coherent

signa reg reg reg reg reg reg reg reg

LUT LUT LUT LUT LUT LUT LUT

Signal effected with

effect due to fading with single reflector

VLSI & Embedded group, UTS www.unistring.com

CAN bus interface

SPI bus interface

HIL simulation core

Algorithm simulation in C/MATLAB/OCTAVE

Integration of modules and testing with top level test

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