JYOTHISHMATHI INSTITUTE OF TECHNOLOGY & SCIENCE

Nustulapur, Karimnagar

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

IV - B.Tech I Semester ECE & IT

VLSI DESIGN
OBJECTIVE QUESTION BANK
ACADEMIC YEAR -2014-2015

Prepared By:
Mr. M. RAMAKRISHNA, Assoc. Professor, ECE
Mr. D.RAVIKRAN BABU, Assoc. Professor, ECE

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 JYOTHISHMATHI INSTITUTE OF TECHNOLOGY & SCIENCE
Nustulapur, Karimnagar
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
IV B.Tech I-Sem ECE & IT

VLSI DESIGN
OBJECTIVE QUESTION BANK

UNIT I: INTRODUCTION

1. The approximate number of transistors per VLSI chip in commercial products

a. 100-1000 b.1000-20,000 c.20,000 -1,000,000 d. 1,000,000-10,000,000

2. To achieve low threshold voltage in the p-well CMOS fabrication

a. Deep well diffusion or low well resistivity
b. Deep well diffusion or high well resistivity
c. Lower substrate bias and higher parasitic capacitances
d. Higher substrate bias and higher parasitic capacitances

3. The common measure of effectiveness of VLSI chip is

a. Propagation delay b. Speed power product
c. Gain bandwidth product d. Power dissipation

4. The advantages of Bipolar technology compared to MOS technology is

a. Low static power dissipation b. High input impedance
c. Low drive current d. Higher gain
5. In NMOS fabrication, the UV radiation is used for
a. Etching b. Polymerization c. Chemical Vapor Deposition d. self aligning

6. The buried n+ sub collector is added to the n-well CMOS transistor to provide
a. Emitter region b. Reduce the output drive current
c. Reduce the n-well collector resistance d. Base region
7. To provide a interconnection pattern which of the following layers is used
a. Thin layer of SiO2 b. Poly silicon layer c. Phtoresist layer d. Aluminum layer

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8. The advantages of CMOS technology compared to Bipolar technology
a. Low delay sensitivity to load b. High output drive current
c. High packing density d. High gain

9. The speed power product of any MOS technology is measured in

a. KJ b. MW-sec c. PJ d. Joules

10. For depletion mode MOSFET, threshold voltage

a. 0.2VDD b. -0.2VDD c. 0.8VDD d. -0.8VDD

11. The technology which is characterized by high speed

a. CMOS b. BICMOS c. GaAs d. ECL

12. Latch-up in CMOS device can be avoided by

a) Increasing temp b) doping control
c) Increasing the substrate resistance d) decreasing substrate doping level

13. Material used for metallization is

a) Aluminum b) copper c) silver d)tungsten

14. Material used for gate oxide in most technology.

a) Si b) Ge c) SiO2 d) AlO2

15. Poly silicon is a material

a) Crystalline b) Amorphous c) Poly crystalline d) None

16. Silicide is combination of

a) Metal poly b) Metal-Silicon c) Metal-Ge d) Metal-SiO2
17. In modern CMOS fabrication, the pattern on each layer is created by
a) Ion implantation b) Oxidation c) Photolithography d) Encapsulation

18. The advantage of twin- tub process

a) Low complexity b) Low cost depletion c) Latch up immunity d) high mask count

19. ------------ is used as gate material

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 a) Poly silicon b) Si c) Cu d) Al

20. Which MOS transistor passes strong logic 1

`a) PMOS b) NMOS c) (a) & (b) d) None

21. Pinch-off occurs in ---------------------- region

a) Non saturation b) Saturation c) cut-off d) linear

22. The drain current flow in ideally independent of drain-source voltage when channel is
a) Strongly depleted b) Weakly depleted c) strongly inverted d) Weakly inverted

23. -------------- Process is used to transfer the layout pattern from masks to wafer.
a) Diffusion b) Isolation c) Photolithographic d) Metallization

24. According to Moores law, the number of transistors that could be manufactured on a chip

a) Linearly decreases b) Grows exponentially

c) Grows linearly d) Decreases exponentially

25. The transistor threshold voltage, VT is ----------------------- for P type transistor.

a) Positive b) Negative c) Zero d) Infinity

26. The present feature size of a transistor is -----------------

a) 0.5 m b) 0.13 m c) 0.75 m d) 1 m

27. Pick out the advantage of IC

a) Smaller physical size b) Low power consumption
c) Reduced cost d) All
28. All of the following are advantages for CMOS Technology compared to Bipolar Technology, except

a) High input impedance b) High noise margin

c) High noise margin d) high output drive current
29. The guard rings are used to reduce
a ) VT b ) latch up c ) width of channel d ) CGS
30. The Fermi potential value for typical p-type silicon substrate is
a) 0.6V b) 0.35V c) -0.35V d)-0.6V
31. Accumulation mode of MOS transistor is -
a) Vgs=Vt b) Vgs>Vt c)Vgs<Vt d) none
32. The effective gate voltage is Vg=Vgs-Vt(Vgs<Vt)
a) high current flows b) no current flows c) low current flows d) none
33. In enhancement mode devices Vt, Vdd values are respectively
a) 5V, 1V b) -5V, -1V c) 1V, 5V d) -1V, 5V

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 34. In NMOS fabrication, on the hole chip metal (aluminum) has deposited over its surface to a
thickness is
a) 2um b) 1m c) 0.5um d) 5um
35. In well process, to achieve low threshold voltages(0.6V and 0.1V)
a) high doping b) low doping c) deep well diffusion d) none
36. The process technology presently used in chip design is
a) NMOS b) PMOS c) BiCMOS d) CMOS
37. In present CMOS technology the type of gate used is
a) Poly Silicon b) Aluminum c) copper d) Gold
38. Common dielectric is used for isolation of devices is
a) Silica b) silicon dioxide c) wood d) graphite
39. The second most abundant element available on the earth is
a) Silicon b) Aluminum c) graphite d) ferrous

40. The plasma orientation of the wafer which produces electrically cleaner oxide interface is
a) <100> b) <110> c) <111> d) <000>

41. Noise margin of MOS technology is ___compared with bipolar technology

a) low b) high c) same d) none

42. _____ Law describes the epitaxial growth of integrated circuit complexity
a) Lenzs law b) nyquists c) faradays d) Moores

43. VLSI is meant by the term as a Device has containing between_______________ transistors.
a) 103 and 105 b) 105 and 107 c) 107 and 109 d) 109 and 1011

44. Thermal oxidation process is carried out at ____ 0C temperature range.

a) 100-200 b) 400-600 c) 900-1200 d) 1300-1600

45. _____ is the best method for controlling the selective dopants in to the silicon crystal wafer.
a) epitaxial b) diffusion c) ion implantation d) all

46. ICs made by sputting materials on ceramic substrate are called

a) Thin film IC b) Hybrid IC c) Monolithic IC d) Thick Film IC
47. MOS ICs
a) consume more power b) occupy less space than BJT
c) low input capacitance d) having high speed
48. Epitaxial layer growth in IC
a) May be on n-type b) may be on p-type
c) Involves growth from gas phase d) involves growth from liquid phase
49. The most important reason for use of ICs is
a) High reliability b) low power consumption
c) simple circuit design d) low cost
50. According to Moores law, the number of components doubles in every _____ months
a) 10 b) 20 c) 22 d) 18

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51. Expansion of CVD is ________________
52. _________________ lithography is preferred in submicron device dimension
53. The kinetics of thermal oxidation is modeled by __________model.
54. The static power dissipation in CMOS technology is
55. In normal mode of operation in CMOS, substrate terminal of MOS is connected to__________and
substrate terminal of PMOS is connected to____________
56. CMOS technology is high delay than___________Technology
57. The deficiency of MOS technology is _________
58. Under DEPLETION mode NMOS is _________state.
59. NMOSFETs are_______than PMOSFETs
60. Power dissipation in NMOS technology is ______ compared to CMOS technology.
61. The thickness of thin-ox (SiO2)layer is ________________
62. The threshold voltage for enhancement mode transistor is ______________
63. _________________ type of gate voltage is applied to establish channel between source and drain
of enhancement mode MOS transistor
64. The gate/channel capacitance Cg and gate capacitance/unit area Co are related as______
65. The voltage applied between the gate and source of a MOS device, below which the drainto-source
current effectively drops to zero, is ________________.
66. The thickness of thick-ox (SiO2) layer is typically ______ thick.
67. If a gate is connected to a suitable positive voltage then a ___________is formed between the
source and drain.
68. Bi-CMOS technology is most popularly used for I/O and driver circuits (T / F)
69. Charge induced in channel due to gate voltage is due to the voltage difference between the drain and
source (T / F )
70. In the CMOS fabrication p-well process requires lower temperature for diffusion process than n-
well process (T / F )
71. Threshold voltage needed to invert charge under gate and establish channel (T / F )
72. PMOS transistor are inherently faster than the NMOS transistors (T/ F )

73. In Bi-CMOS, the logical approach is to use MOS switches to perform the logic function
(T / F )
74. In BiCMOS technology, the n-well resistance is reduced by using _________
75. Through-hole mounting is used in ________________ package
76. Metallization is done for fabricating
77. Dry etching is also known as____________
78. the mask is often known as________
79. Bipolar device has__________
80. Working of MOSFET depends on___________
81. Dual inline package is sometimes called as _________ package.
82. Photolithography is done in________________.
83. The type of silicon required to fabricate IC is____________
84. Etching is done to remove ________areas to the semiconductor surface
85. Photo resist is used in lithographic process to transfer patterns from _____to the________
86. Advantages on silicon on insulator _______ process is absence of latch up problem
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87. The width of the channel depends____
88. In BiCMOS logic____ are used near output to drive currents
89. If packaging density area and performance are the constraints, power dissipation is not constraints
the technology preferred______
90. For depletion mode device Vtd is ______
91. Thin film resistors have_____ temperature coefficient
92. ___&_________ elements are first diffusions in silicon
93. Czochralski is a _____________ technique in wafer fabrication.
94. The ____________ of the VLSI chip ranges from pre-assembly wafer preparation to fabrication
technologies for the packages that provide electrical connections and mechanical and environmental
protection.
95. The implantation dose Q0 is given by the expression______________.
96. In MOS resistors to increase the resistance value the aspect ratio of MOSFET should be___.

REFERENCES:

1. Essentials of VLSI circuits and systems Kamran Eshraghian, EshraghianDougles and A. Pucknell,
PHI, 2005 Edition-CHAPTER 1 (pp:1-23).
2. Introduction to VLSI Circuits and Systems - John .P. Uyemura, JohnWiley, 2003-CHAPTER 4 (
pp: 115-132).

ANSWERS-UNIT-I

1. c 19. a
2. b 20. a
3. b 21. b
4. d 22. c
5. b 23. c
6. c 24. c
7. d 25. a
8. c 26. b
9. c 27. d
10. b 28. d
11. d 29. d
12. b 30. b
13. a 31. c
14. c 32. b
15. c 33. c
16. a 34. b
17. c 35. c
18. c 36. d
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 37. a 75. single inline
38. b 76. wires, contacts etc
39. a 77. plasma etching
40. a 78. Reticle
41. b 79. High power dissipation
42. d 80. Vds
43. c 81. DIL
44. c 82. clean rooms
45. c 83. electronic grade silicon
46. a 84. unwanted
47. b 85. mask, substrate
48. c 86. CMOS
49. a 87. Vgs
50. d 88. BJTs
51. Chemical Vapour Deposition 89. nMOS
52. Electron 90. 0.8Vdd
53. Deal and groover model 91. low
54. Zero 92. Group 1&VIII
55. Vss , Vdd 93. Crystal growth
56. Bipolar 94. Packaging
57. Limited load driving capacity 95. Jt/q
58. ON 96. Reduced
59. Faster
60. High
61. 0.1m
62. 0.2Vdd
63. Positive
64. Cg = C0 WL
65. Threshold voltage
66. 1m
67. Channel
68. True
69. True
70. False
71. True
72. False
73. False
74. Doping

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 UNIT -II:BASIC ELECTRICAL PROPERTIES

1. MOSFET operated in saturation when

a) Vds=vgs-vt b) vds<vgs-vt c) Vds>vgs-vt d) Vds<vt

2. For faster NMOS circuits, one would choose the following type of substrate
a) 110 Oriented n - type substrate b) 100 oriented p - type substrate
c) 111Oriented p - type substrate d)111 oriented n- type substrate

3. Pull-up to pull-down ratio for NMOS inverter driven by another NMOS inverter is
a) 4:4 b) 4:1 c)1:4 d) 8:1

4. The following device is less likely to suffer latch-up

a) NMOS b) CMOS c) Bi-CMOS d) PMOS

5. In CMOS inverter if n=p &if Vtn=Vtp, then the logic levels are disposed about at a
point where
a)VIN=Vout=0.1VIN b)VIN=0.5 VDD
c) VIN=Vout=0.5VDD d) VIN=Vout=VDD

6. The figure of merit of MOS transistor can be expressed as

a) gmCg b) Cg/gm c) gm /Cg d) gm + Cg

7. Typical mobility of holes(Bulk) is

a) 650cm2/V.sec b) 240 cm2/V.sec c) 1250 cm2/V.sec d) 480
cm2/V.sec

8. Pick up the true statement with respect to Bi-CMOS Inverter

a) Low input impedance b) High output impedance
c) High noise margin d) Low driving capability

9. To achieve best performance NMOS inverter transfer characteristics, Zpu/Zpd ratio

should be
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 a) Zero b) One c) As low as possible d) As high as
possible

10. Number of transistors to implement three-input AND gate using pass transistor logic is
a) 6 b) 3 c) 5 d) 9

11. In the MOSFET, as width of channel increases Id

a) Increases b) decreases c) Constant d) none

12. Latch up is caused by

a) Parasitic R b) Parasitic BJTs c) (a) & (b) d) Parasitic C

13. Pick up latch-up resistant CMOS process

a) n well b) p well c) silicon on Insulator
d) all

14. In which process (CMOS) PFETs are embedded in n well

a) P well b) n well c) SOI d) all

15. In the Pseudo-NMOS logic ----------- transistor is used as pull-up resistor

a)PMOS b) NMOS c) Bipolar d) UJT

16. Latch structure is used in ------------ Logic

a)Pseudo-nMOS b) DCVS c) Domino d) all

17. For n-type transistor threshold voltage is ______________

a) Positive b) negative c) zero 4) none

18. In the twin tub process ____________ wafer is used

a) p-doped b) n-doped c) undoped d) none

19. The expression for drain to source current in non-saturated region for enhancement
MOS device is

20. The charge per unit area in the depletion layer beneath the oxide QB is

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 21. . The transit time of electrons will flow from source to drain is

22. The input and output impedances for Bi-CMOS inverter is

a) Both are high b) Both are low c) High and low d) Low and
high

23. The gate/channel capacitance for parallel plates is

24. In NMOS inverter, alternative pull-ups are_________ used as loads

a) load resistor b) depletion mode c) CMOS d) all

25. The problem with n-mos pass transistor to provide logic ___ levels
a) 0 b) 1 c) 0,1 d) none

26. Accumulation mode of MOS transistor is

a) Vgs<Vt b) Vgs>Vt c)Vgs=Vt d) Vgs*Vt

27. For depletion mode devices the channel is established because of the implant even
when a) Vgs=0 b) Vgs=Vdd c) Vgs=Vdd/2 d) Vgs=Vt

28. An inverter driven through one or more pass transistors should have a Zp.d/Zp.u ratio
a a) 2:1 b) 4:1 c) 8:1 d) 16:1

29. An inverter driven directly from the output of another should have a Zp.u/Zp.d
a) 2:1 b) 4:1 c) 8:1 d) 16:1

30. In place of resistors ___are used

a) buffers b) inverters c) pass transistor d) NAND gate

31. The inverter has _____input impedance and ________ output impedance
a) High, Low b) Low, High c) Low, Low d) High, High

32. The ____ of electron mobility with electric field gives velocity
a) addition b) product c) subtraction d) division
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 33. _____ is the input voltage of a CMOS inverter in which both PMOS and NMOS in
saturated region
a) Vdd b) Vdd/2 c) Vdd/3 d) 2Vdd
34. In BiCMOS logic____ are used near output to drive currents
a) PMOS b) NMOS c) BJT d) Resistor
35. Sub threshold operation of MOSFET is very much useful in _____
a) biomedical applications b) memory
c) charge coupled devices d) none
36. The main advantages of short channel devices is_____
a) its low power consumption b) it has good output characteristics
c) it has good speed d) it is easy to fabricate
37. The phenomenon in MOSFET like early effect in BJT is
a) body effect b) hot carrier effect
c) channel length modulation d) subthreshold conduction
38. Sub threshold operation occurs in_________
a) strong inversion region b) weak inversion region
c) saturation region d) cut-off region
39. The ON resistance of a MOSFET_______
a) linearly increases with Vgs b) linearly decreases with Vgs
c) exponentially increases with Vgs d) non-linearly decreases with Vgs
40. The threshold value of an enhancement NMOS transistor is
a) >0 b) <0 c) =0 d) none

41. Main advantage of depletion load NMOS inverter circuit over enhancement type
NMOS load is
a) fabrication process is easier b) sharp VTC transitions and better noise margins
c) less power dissipation d) none of these

42. Which one is not second order effect?

a) body effect b) ) channel length modulation
c) sub threshold conduction d) hot carrier effect

43. CMOS uses

a) Positive logicVDD is logic 1 and VSS is logic 0
b) negative logic--- VSS is logic 1 and VDD is logic 0
c) none of the above
d) both a and b

44. An inverter driven through one or more pass transistor should have Zpu/Zpd ratio
of___
45. The threshold voltage is increased due to _____
46. More lightly doped substrate___________ will be the body effect
47. The drain- source current (IDS) for NMO under saturation can be expressed as

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 48. Trans conductance of MOS transistor (gm) is expressed as

49. For devices of similar dimension n-channel is ___________than the pchannel

50. A simple BICMOS inverter _______ input impedance and _____output
impedance.
51. The power dissipation is _______in CMOS technology.
52. Bi-CMOS inverter has high driving capability than____________ technology.
53. For high performance CMOS inverter n/p should below_

54. The threshold voltage for depletion mode transistor is ______________

55. A reduction in the channel length in MOS transistor results in an increase
in________
56. The BiCMOS inverter has a high current drive capability but occupies--------------
area
57. The---------------needed to invert the charge under the gate and establish the
channel
58. The-------------- are Switching Logic Arrays
59. To increase the gm of a MOS device by ----------------------its width
60. The establishment of low resistance conducting paths between VDD and VSS due
to the parasitic capacitance is called _____________.
61. Charge induced in channel due to _________
62. The threshold voltage for the NMOS enhancement mode device is_________.
63. Zp.u./Zp.d.for an inverter directly driven by an inverter is____________.
64. Bulk mobility of n-transistor is -------------
65. The Maximum voltage across the enhancement mode device corresponds
to_____voltage across the depletion mode transistor
66. Mobility of n-transistor at room temperature is _________
67. The gate/channel capacitance Cg and gate capacitance/unit area Co are related
as_____.
68. The gain of MOS device decreases as output resistance___________
69. The ratio of charge induced in channel to electron transit time is_________
70. In saturated region_________ remains constant when Vds is changed
71. In non-saturated region the average value of the voltage of channel gives____
72. The width to length ratio of the p-devices___ of the n-devices
73. The effective gate voltage Vg is the difference b/w ____ and______
74. In MOS transistor surface mobility is also dependent on ____
75. The NMOS inverter for depletion mode transistor the gate is connected to
_________so it is always on
76. In saturated region, by increasing channel width it is possible to increase the ___ of
MOS device
77. The switching speed depends on ________ above threshold and on carrier mobility.

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 78. The charge induced is ________ on the gate to source voltage Vgs, then Ids is ___
on the both Vgs and Vds
79. In non-saturated region electric field Eds _________
80. The threshold voltage for the NMOS depletion mode device is________
81. The effective gate to channel voltage at the drain ,the current is fairly_______ -
82. In the aspects of MOS, increasing __________ cause the channel depleted of
charge carriers and thus_______ raised
83. The source of NMOS and PMOS in CMOS inverter always connected to____
84. A MOS transistor which has no conducting channel region at zero gate bias is
called__
85. Saturated load in the ___ inverter makes high output logic less by 1Vt
86. In the NMOS inverter configuration, the depletion mode device is called_____
87. In the NMOS depletion mode transistor dissipation is___________ when
Vin=logical 1
88. In pull-up (CMOS)_________________flows either for logical 0 or for logical 1
inputs.
89. In CMOS inverter(region 3) is the region in which the inverter exhibits gain and
both the transistors are in______
90. Advantages on silicon on insulator _______ process is absence of latch up problem
91. In linear region channel is formed and drain current_____ linearly when potential
is _______ between source and drain
92. The speed of CMOS is less when compared to other technologies due to
93. The state of NMOS and PMOS transistor in region 4 of Vin Vs Vout characteristics is
94. In CMOS _____&_____ are used
95. The transconductance ratio is ______
96. If n=p then the value of Wp is ______
97. Figure of Merit of MOS transistor is__________
98. CMOS has__________ dissipation than compared to bipolar and mos devices
99. ______load in the NMOS inverter makes HIGH OUTPUT logic less by 1Vt.
100. If packaging density area and performance are the constraints, power
dissipation is not a constraint, the technology preferred is_____________.
101. The parameter which affects the propagation delay is ______.
102. Advantages of Silicon on Insulator CMOS process is____________
103. Working of MOSFET depends on_______.
104. The width of the channel dependent on_____________.
105. The ratio of gm/Cg gives __________

REFERENCES:

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 1. Essentials of VLSI circuits and systems Kamran Eshraghian, EshraghianDougles and
A. Pucknell, PHI, 2005 Edition-CHAPTER 2 (pp: 24-54).
2. Introduction to VLSI Circuits and Systems - John .P. Uyemura, JohnWiley, 2003-
CHAPTER 6 (pp: 191-229).

ANSWERS-UNIT-II

1. c 25. b
2. b 26. a
3. b 27. a 48. (Vgs Vt)
4. c 28. c 49. faster
5. c 29. b 50. high, low
6. c 30. b 51. low
7. d 31. a 52. CMOS
8. c 32. b 53. Low
9. c 33. b 54. -0.6v negative
10. b 34. c 55. Drain current
11. b 35. a 56. Large
12. b 36. c 57. Threshold
13. a 37. c
voltage
14. b 38. b
58. Pass transistor
15. a 39. d
59. Increase
16. b 40. a
60. Latch up
17. a 41. b
61. Gate voltage
18. c 42. a
62. 0.2v positive
19. 4 43. a
63. 4:1
20. 3 44. 8:1
64. 1250
21. 3 45. Body effect
22. c 46. Less cm2/V.sec
23. 4 47. 65. Minimum
24. d 650cm2/V.sec
66.

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 67. Cg = C0 WL 81. constant 92. High input
68. Decreases 82. Vsb,Vt
capacitance
69. Drain current 83. GND,Vdd
93. Linear,
70. Drain current 84. enhancement
71. Vds/2 Saturation
mode
72. 2 to 3 times 94. NMOS&PMO
85. BICMOS
73. Vgs, Vt
86. Pull up S
74. Gate voltage
87. high 95. Ids/Vgs
75. source
88. no current 96. 2.5 Wn/Ln
76. gm
97. gm/ Cg
77. gate voltage flows
98. low static
78. dependent 89. saturation
,dependent 90. CMOS power
79. Eds=Vds/L 91. Increases, 99. saturation
negative 100. NMOS
80.
Increases

101. load capacitance, doping densities, channel length

102. no latchup problem
103. Vds
104. Vgs
105. Figure of merit

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 UNIT III:VLSI CIRCUIT DESIGN PROCESSES

1. The color encoding for poly silicon is

(a)Red (b) Green (c) Blue (d)
Orange

2. The color encoding of VIA in double metal CMOS p-well process

(a)Red (b) black (c) Blue (d)
Orange

3. Metal 1to Metal 1 spacing in layout design is

(a)4 (b) 2 (c)3 (d) 1

4. The buried contact is made between

(a) Poly to metal (b) poly to diff
(c) poly to diffusing metal (d) Metal to metal

5. In NMOS layout design style, the color of contact cut

a) Black b) Green c) Blue d) Red

6. What is color of metal 1(CMOS encoding)

a) Black b) Blue c) Red
d) Yellow

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 7. The p-type transistors are placed above the
a) Poly silicon b) diffusion c) Demarcation
line d) metal

8. The minimum gap between diffusion and diffusion is

a) 2 b) 5 c) 7 d) 10

9. The size of a transistor is usually designed in terms of

a) Drain b) source c) metal
d) channel length

10. According to 2m CMOS technology, the minimum separation between

contact cuts
a) 2m b) 4 m c) 6m d) 5 m
11. The smallest feature size of a transistor is
a) 4 x 4 b) 2 x 2 c) 8 x 8 d) 1 x
1

12. Metal-2 to metal-1 contact is called ---------------

a) Buried contact b) Butting contact c) Via d)
contact out

13. The minimum separation between two metal-2 contacts in based design rules
is
a. 1 b. 2 c.3 d. 4

14. The gate delay is scaled by

a. 1/ b. /2 c. 1/ d.

15. The Butting contact is used to

a. Connect poly silicon to diffusion using metal b. Metal1 to

metal 2
c. Connect VDD d. Connect
ground

16. The gate capacitance per unit area is scaled by

a. 1/ b. c.1/ d.
17/62
VLSI DESIGN: Prepared by M.Ramakrishna @Dept. of ECE, JITS
 17. VDD and VSS should be distributed on
a. Diffusion layer b. Metal layer c. Poly silicon layer d.
Silicide layer

18. The minimum feature size on chip, if can be allocated a value of 1m is

a. 0.5m b.1m c. 2m d. 4m

19. The minimum separation between two poly silicon layers in based design
rules is
a. 1 b. 2 c.3 d. 4

20. Design rules are geometrical constraints on

a) stick diagram b) Layout c) circuit d)

program
21. If pull-up network consist of series connected NFETs, the gate is
a) NAND b) NOR c) NOT d) None

22. If pull-up network consist of parallel connected NFETs, the gate is

a) NAND b) NOR c) NOT d) None

23. In constant voltage scaling, the doping density

a) Remain unchanged b) increased by a factor s
2
c) Increased by a factor s d) increased by a factor s3
24. In full scaling, the power dissipation is
a) decreased by a factor s b) decreased by a factor s2
c) remain unchanged d) increased by a factor s
25. In constant voltage scaling, the power dissipation is
a) remain unchanged b) increased by a factor s
2
c) decreased by a factor s d) decreased by a factor s3
26. The smallest feature size ( ) used to measure an IC is_____
a) half the length of the smallest transistor
b) two-third the length of the smallest transistor
c) ) one fourth the length of the smallest transistor
d) none of the above
23. For a 0.5 um process technology
a) =0.25 um b) =0.5 um c) =1um d) = 0.25um

27. The color code for thin oxide region in stick diagram using NMOS design is
a) Green b) Yellow c) Blue d) Red

28. What gate is used to convey layer information through the use of a color code?

18/62
VLSI DESIGN: Prepared by M.Ramakrishna @Dept. of ECE, JITS
 a) NOT Gate b) Transmission gate c) NAND
d) NOR

29. The metal 2 to metal2 spacing in CMOS lambda based design rules is
a) 2 b) 3 c) 4 d)

30. Power speed product is scaled by

a) 1/2 b) 1/2 c) /2 d)

31. All of the following are used for making contacts b/w poly silicon and diffusion
in NMOS circuit, except
a) Buried contact b) butting contact
c) Polysilicon to metal then metal to diffusion d) none of these

32. The switching energy per gate is Eg______

a) 1/2 b) 1/2 c) /2 d)

33. The saturation current Idss is scaled by______

a) 1/ b) 1/2 c) /2 d)

34. Gate capacitances per unit area Cox is scaled by______

a) 1/ b) /2 c) d) 1/

35. The gate area Ag is scaled by __________

a) 1/ b) 1 /2 c) d)1/

36. For nMOS design yellow is used for______

a) diffusion b) poly silicon c) implant d) metal-1
37. In scaling factors channel resistance is scaled by ______
a) 1/ b) 1 c) d) 1/

38. In CMOS design style, the n-transistor are then placed____ the demarcation
line and thus close to____
a) below, Vdd b) Above, Vss c) Above, Vdd d)
below, Vss

39. The minimum feature size on chip is 2um, then the value of is
a) 4 b) 2 c) 3 d) 1

40. The layer preferred for global distribution of power buses is

41. ______________is used to convey layer information.
42. For CMOS circuits stick encodings for demarcation line is ________in
color.
43. The power and ground lines often called
44. The minimum width of metal 1 layer is

19/62
VLSI DESIGN: Prepared by M.Ramakrishna @Dept. of ECE, JITS
 45. A_____________ is formed wherever poly silicon crosses Diffusion
46. Metal 1 for __________and metal 2for ________of power lines in stick
notation
47. The minimum poly silicon width is___________
48. As fabrication technology improves, the heat sink size_
49. In CMOS design style, Demarcation line is shown by
50. The Scaling factor for gate oxide thickness is _______________
51. The feature size will scale down without changing design rules True /
False
52. Layers cannot join together where contacts are formed True / False
53. To provide an interconnection pattern _____________ layer is used

Match the following:

54. P+ mask [ ] a. Black

55. p- well [ ] b. Blue
56. p- diffusion [ ] c. Yellow
57. Metal 2 [ ] d. Brown
58. VDD contact [ ] e. Green
59. Carrier density in channel Qon is scaled by_____
60. The max operating frequency is scaled by ______
61. The parasitic capacitance is scaled by ______
62. In CMOs design style, diffusion paths must ____ the demarcation line
63. In CMOS design style, the Vss and Vdd contact crosses,one on the Vss line
for every_____n-transistor
64. In CMOS design style, the p-transistor are placed____ the demarcation line
and ___ Vdd
65. For nMOs design green is used for _____
66. The color of polysilicon ate is _______
67. For nMOS design, black is used for ______
68. In double metal MOS process rules, connected to the other layers using
matal1 and metal2 contacts called
69. In CMOS design for CMOS layouts that the thinox mask includes all _____
features(n-devices) and all______features in stick diagram
70. In CMOS design style, p-transistors are placed_____ the line and below
Vdd
71. In CMOS design style, n-transistor are then placed _________ demarcation
line and thus close to Vss
72. Second level metal is used for global distribution of______- and ______
73. Blue of metal1 may cross_____ without a connection
20/62
VLSI DESIGN: Prepared by M.Ramakrishna @Dept. of ECE, JITS
 74. In scaling parameters for consist voltage scaling is ____

REFERENCES:

1. Essentials of VLSI circuits and systems Kamran Eshraghian,

EshraghianDougles and A. Pucknell, PHI, 2005 Edition- CHAPTER 3 (pp: 55-
77).
2. CMOS VLSI Design- A circuits and systems perspective, Neil H.E Weste,
David Harris, Ayan Banerjee, pearson, 2009- CHAPTER 3 (pp: 83-90).

ANSWERS -UNIT-III
1. a 23. c
2. b 24. b
3. c 25. a
4. b 26. a
5. a 27. a
6. b 28. a
7. c 29. b
8. a 30. c
9. d 31. b
10. a 32. c
11. b 33. b
12. c 34. a
13. d 35. c
14. b 36. b
15. a 37. c
16. b 38. b
17. b 39. b
18. c 40. d
19. b 41. Metal
20. b 42. Stick diagram
21. b 43. Brown
22. a 44. Power range
21/62
VLSI DESIGN: Prepared by M.Ramakrishna @Dept. of ECE, JITS
 45. 3
46. MOS transistor
47. Local distribution, global
distribution
48. 2
49. Reduces
50. Dotted line
51. 1 /
52. True
53. False
54. Metal
55. c
56. d
57. e
58. b
59. a
60. 1
61. 2/
62. 1/
63. Not cross
64. Four
65. Above, Below
66. n-diffusion
67. Red
68. contact areas
69. Vias
70. Green, Yellow
71. Above
72. Below
73. Vdd and GND
74. Green or red
75. =1

22/62
VLSI DESIGN: Prepared by M.Ramakrishna @Dept. of ECE, JITS
 UNIT-IV: GATE LEVEL DESIGN

1. Power dissipation per unit area is scaled by

a) 1/2 b) c) d) 2/2
2. Typical value of Diffusion capacitor(Carea) in5mtechnology

a) 1.0x10 4pF/m2 b) 1.0X10 2pF/m2= c) 0.1x10 4pF/m2 d) 0.1x10

2pF/m2

3. The rise time of CMOS inverters is

a) = (b) = (c) = d) =

4. The typical value of load capacitance is

(a) CL < 10 4 Cg (b) CL 10 4 Cg (c) CL = 10 14 Cg (d) CL 10 14 Cg

5. The characteristics of a metal layer are

a) Low R; low C b) low R; moderate C c)Low R; moderate C d) moderate R; highC

6. The typical sheet resistance of poly silicon for 5m is

a) 0-10 b) 10-14 c) 120 to140 d) 15 to100

7. The overall delay Td for n sections is given by

a) Td=nrc ( ) b) Td= n2rc( ) c) Td=n2r2c() d) Td=nr2c()

8. Deposition of the metal/silicon alloy prior to sintering may be done with

a) Sputtering b) diffusion c) Implantation d) Metallization

9. What is the formula for Rise-Time Estimation?

10. The formula for fall-time estimation in CMOS inverter is

11. The number of gates that can be connected at the input is

a) DC Fan-in b) AC Fan-in c) Fan-in d) Fan-out
12. For 2 m technology =
a) 0.064 ns b) 0.1 ns c) 0.128 ns d) 0.064s

13. The sheet resistance of silicides layer compared to poly silicon layer is
a. Twice b. High c. Low d. Same

14. The layer used to speed up the rise time of propagated signal edges is
a. Diffusion layer b. Metal layer c. Poly-silicon layer d. Silicide layer

15. The channel resistance of a simple n-type pass transistor has a channel length 2 and width 2
is
a. 104 ohm b. 4 ohm c.1 ohm d.4 ohm

16. One of the following is used to drive large capacitive loads

a. N cascaded inverters b. Small size inverter
c. High Zp.d and Zp.u d. Small L:W

17. For a given area, the metal to poly-silicon capacitance is compared to metal to substrate
a. Lower b. Higher c. Same d. Half

18. One of the following is used to drive large capacitive loads

a. super buffers b. Buffers c. Inverters d. Super inverters

19. The sheet resistance of diffusion layer compared to poly silicon layer is
a. Twice b. High c. Low d. Same

20. Standard value of Cg =

a) 0.0032nf b) 0.01 pf c) 0.128 pf d) 0.0023 nf

21. The propagation delay of n sections is given by___________

22. The layer in which metal is deposited on poly silicon is called_____________
23. The sheet resistance of pdiff is________ times that of n-diffusion.
24. The values for N-diffusion region are ______times the P-diffusion regions.
25. Bi-CMOS technology is reasonably good for _______.
26. Power consumption in CMOS circuits depends on______at which they operate.
27. _____________ layer is suitable for routing Vdd or Vss
28. The_______________ load cant be driven by a single inverter.
29. In Bi-Polar transistor collector current depends _________on Vbe.
30. The Delay for Bi-CMOS inverter is _____by a factor of hfe compared with a CMOS Inverter.
31. In CMOS the rise time delay time is _____________times then a fall time delay for equal n
and p transistor geometries
32. In_________ logic pMOS net is in dual topology with nMOS net.
33. Pass transistor logic uses transistors as______to carry logic signals from one node to
another.
34. The two phases in dynamic CMOS are _______and__________
35. The unit of sheet resistance is___________________

36. The resistance of MOS layers depend on the_____________________________and

_o f the layer.
37. The delay unit T =_______________
38. The rise time and fall time are dependent on______________

39. For equal n and p geometries the rise time is equal to_____ times that of the fall
time
40. R s is independent of the area of the square [true / false]
41. _____________is the time taken for a waveform to rise from 10% to 90% of its steady-state
value.
42. ___________is the time taken for a waveform to fall from 90% to 10% of its steady-state
value.
43. __________is the time difference between input transition (50%) and the 50% output level.
44. _________is the advantage of Domino logic
45. __________is disadvantages of Domino logic
46. Correct operation of a design must not be dependent on__________________
47. ______________ is used to reduce the number of transistors required to implement a given
logic information.
48. The problem of driving comparatively large capacitive loads arises when signals must be
propagated from the ------
49. The inverter pair delay for inverter having 4:1 ratio is ____________
50. For __________ the value of fringing field capacitance can be of the same order as that of
the area capacitance
51. The inverter pair delay for CMOS is_______________.
52. The optimum value of width factor to drive large load in N-cascaded inverters is____.

REFERENCES:

1.Essentials of VLSI circuits and systems Kamran Eshraghian, EshraghianDougles and A.

Pucknell, PHI, 2005 Edition- CHAPTER 4 (pp: 85-110).
 ANSWERS -UNIT-IV

1. d 15. a
2. a 16. a
3. c 17. b
4. b 18. a
5. a 19. c
6. d 20. b
7. b 21. n2rc( )
8. a 22. silicide
9. a 23. 2.5
10. c 24. 0.4
11. c 25. High output driving capability
12. a 26. Frequency
13. c 27. Metal 1
14. b
28. Large capacitance 42. Fall time
29. Exponentially 43. Transmission delay
30. Reduced 44. smaller parasitic capacitances
31. 2.5 hence higher speed
32. CMOS 45. charge sharing
33. Switch 46. temperature, parasitic
34. Precharge, evaluate elements
35. Ohm/square 47. NMOS, Pseudo NMOS
36. Length and Width 48. On chip to off chip
37. Nano sec 49. 5 NMOS, 7 CMOS
38. , width 50. Fine line metallization
39. 2.5 51. 7T
40. True 52. e=2.7713
41. Rise time
 UNIT-V: DATAPATH SUB SYSTEM DESIGN
1. For the 4X4 bit barrel shifter, the regularity factor is given by
a.
8
b.
4
c.
2
d.
16
2. The level of any particular design can be measured by
a.
SNR
b.
Ratio of amplitudes
c.
regularity
d.
quality
3. In tackling the design of system the more significant property is
a.
logical operations
b.
test ability
c.
topological properties
d.
nature of architecture
4. Any bit shifted out at one end of data word will be shifted in at the other end of the word
is called
a.
end-around
b.
end-off
c.
end-less
d.
end-on
5. In the VLSI design the data and control signals of a shift register flow in
a.
horizontally and vertically
b.
vertically and horizontally
c.
both horizontally
d.
both vertically
6. The subsystem design is classified as
 a.
first level
b.
top level
c.
bottom level
d.
leaf-cell level
7. The larger system design must be partition into a sub systems design such that
a.
minimum interdependence and inter connection
b.
complexity of interconnection
c.
maximum interdependence
d.
arbitarily chosen
8. To simplify the subsystem design, we generally used the
a.
interdependence
b.
complex interconnections
c.
regular structures
d.
standard cells
9. System design is generally in the manner of
a.
down-top
b.
top-down
c.
bottom level only
d.
top level only
10. Structured design begins with the concept of
a.
hierarchy
b.
down-top design
c.
bottom level design
d.
complex function design
11. Any general purpose n-bit shifter should be able to shift incoming data by up to number
of places are
a.
n
b.
2n
c.
n-1
 d.
2n-1
12. For a four bit word, a one-bit shift right is equivalent to a
a.
two bit shift left
b.
three-bit shift left
c.
one bit shift left
d.
four-bit shift left
13. The type of switch used in shifters is
a.
line switch
b.
transistor type switch
c.
crossbar switch
d.
gate switch
14. The carry chain in adder is consist with
a.
cross-bar swith
b.
transmission gate
c.
bus interconncection
d.
pass transistors
15. VLSI design of adder element basically requires
a.
EX-OR gate, Not and OR gates
b.
multiplexers, inverter circuit and communication paths
c.
multiplexers, EX-OR and NAND gates
d.
inverter circuits and communication paths
16. The number of basic cells required for an n-bit X n-bit multiplier is
a.
(3n+1)
b.
(3n+1)2n
c.
n2
d.
n(n-1)
17. The heart of the ALU is
a.
Register
 b.
adder
c.
control bus
d.
I/O port
18. Carry line in adder must be buffered after or before each adder element because
a.
slow response of series pass transistors
b.
slow response of parallel line
c.
fast response of parallel pass transistors
d.
fast response of series line
19. The ALU logical functions can be obtained by a suitable switching of the
a.
carry line between adder elements
b.
sum line between adder elements
c.
carry line between shifter & buffer
d.
sum line between shifter & buffer
20. To fast an arithmetic operations, the multipliers and dividers is to use architecture of
a.
parallel
b.
serial
c.
pipelined
d.
switched
21. The number of bits increases in comparator then the
a.
height increases
b.
width grows linearly
c.
width reduces linearly
d.
height reduces
22. The standard cell for an n-bit parity generator is
a.
n-1 bit cell
b.
one bit cell
c.
two bit cell
d.
n+1 bit cell
23. The parity information is passed from one cell to the next and is modified or not by a cell
depending on the state of the
a.
previous information
b.
output line
c.
input lines
d.
next information
24. The parity information (pi) passed from one cell to the next is modified when the input
line (Ai) is at the state of
a.
zero
b.
overline{A}i
c.
one
d.
independent of input line state
25. When cells of parity generator are butted together (indicate false statement)
a.
design rule errors are not present
b.
wastage of area is avoided
c.
inlet and outlet points of cells must be match up
d.
layer and position match is not necessary
26. The two output signals of comparator remain at zero as long as the two bits being
compared are
a.
same
b.
zero
c.
one
d.
different
27. In the comparator the two inputs if A>B then the outputs are
a.
Ci=0 & Di=1
b.
Ci=1 & Di=0
c.
Ci=1 & Di=1
d.
Ci=0 & Di=0
28. In the comparator the two inputs if A<B then the outputs are
 a.
Ci=0 & Di=0
b.
Ci=1 & Di=1
c.
Ci=0 & Di=1
d.
Ci=1 & Di=0
29. The width of n-bit comparator is_____ where w is the width of leaf cell
a.
nw b. w c. (n-1) w d. n
30. The main drawback of asynchronous counter with respect to VLSI is
a.
The output change with respect to clock edge
b.
counter stages are cascaded
c.
the last counter stage to settle can be quite large
d.
clocking of each stage is carried out by the previous stage
31. ONE/ZERO detection circuits for word width of less than 32 bits is the
a.
pseduo-nMOS OR gate
b.
pseduo-nMOS NOT gate
c.
pseduo-nMOS NOR gate
d.
nMOS OR gate
32. The delay from the last changing output to the ripple zero/one detector is a
a.
constant one gate delay
b.
variable delay
c.
greater than two gate delays
d.
constantly increasing delay
33. The speed that synchronous up/down counter can operate is determined by the
a.
ripple-carry time from the LSB to MSB
b.
substantially the clock time
c.
delay of registers
d.
settling time of counter
34. Detecting all ones or all zeros on wide words require
a.
large fan-out AND or OR gates
 b.
large fan-in AND or OR gates
c.
large fan in EX-NOR or EX-OR gates
d.
large fan-out NOR or NAND gates
35. In zero/one detector, the delay to the output is porportional to
(N is bit width of the word)
a.
N
b.
N2
c.
-log N
d.
log N
36. Self-loading of large word widths in ONE/ZERO detectors is avoided by
a.
split into 8 or 16 bit chunks
b.
use large fan in gates
c.
use large word width pseudo-nMOS NOR gates
d.
use large fan-out gates
37. Binary counters are used to cycle through a sequence of
a.
Decimal numbers
b.
binary numbers
c.
hexa decimal numbers
d.
octal numbers
38. An asynchronous counter has outputs that change at
a.
varying times with respect to the clock edge
b.
substantially the same clock time
c.
twice that of the clock edge time
d.
half time of the clock
39. The clocking of each stage of ripple counter is carried out by the
a.
common clock
b.
previous counter stage
c.
connected positive and negative cycles alternately
d.
master-slave flip-flop
 40. the worst case delay of n x n multiplier is
a.
(n+1)T b. (2n+1)T c. (2n-1)T d. (n-1)T
41. The limitation of serial/parallel multiplier is that___ frequency is limited by the
propagation through the array of adders
a.
Maximum b. minimum c. same d. no

42. A multiplier(n x n) requires

2
a. (n-2) full adders, n half adders and n NAND gates
2
b. n (n-2) full adders, n half adders and n NAND gates
2
c. n (n-2) full adders, n half adders and n AND gates
2
d. (n-2) full adders, n half adders and n AND gates

43. Parity generator detects whether the no. of ones in an word is

a.
Odd b. even c. both d. zero
44. ____is a logic circuit used to compare the magnitudes of two binary numbers.

45. A universal shift register can be realized using

46. ___________ circuit can be used as ALU

47. ___________ is a wrap-around shifter which is a very useful switch array.

48. The bottom level in the subsystem design commonly referred to as

( a ) standard cells ( b ) leaf-cells ( c ) block-cells ( d ) system cells

49. Different types of multipliers are ____

a.
Serial b. parallel c. Both d. None

50. Multipliers are employed in different DSP operations like

A) Convolution B) correlations C) filtering D) all

51. ALU involve both ________ and __________ operations.

REFERENCES:

1. Essentials of VLSI circuits and systems Kamran Eshraghian, EshraghianDougles and A.

Pucknell, PHI, 2005 Edition. CHAPTER 6 (pp: 151-162).
2. Principles of CMOS VLSI Design-N.H.Weste & Eshraghian, Pearsoneducation- CHAPTER 8
(pp: 303-356).
3. Introduction to VLSI Circuits and Systems - John .P. Uyemura, JohnWiley, 2003- CHAPTER
12 (pp: 443-471).

ANSWERS-UNIT-V

25. d
1. d 26. a
2. c 27. b
3. c 28. c
4. a 29. a
5. a 30. c
6. d 31. c
7. a 32. a
8. d 33. a
9. b 34. b
10. a 35. d
11. c 36. a
12. b 37. b
13. c 38. a
14. d 39. b
15. b 40. b
16. d 41. a
17. b 42. c
18. a 43. c
19. a 44. Xor gate
20. c 45. Barrel shifter
21. b 46. Adder
22. b 47. Barrel shifter
23. c 48. a
24. c 49. c
50. d
51. Arithmetic, logic
 UNIT-VI: ARRAY SUB SYSTEMS
1. proper placement of memory elements makes maximum use of the
a. available clock period
b. cost of area
c. power dissipation
d. parasitics

2. A design that requires high density memory is usually

a. a single ship
b. on chip
c. partitioned into several chips
d. DRAMS

2. Random access memory at the chip level is classed as memory that has
a. an access time dependent of the physical location of the data
b. an access time independent of the physical loction of the data
c. reading or writing of a particular datum with address
d. examines a data word and compares this data with internally stored data

3. The following memory examines data word and compares this data with internally stored
data
a. serial access memory
b. random access memory
c. content addressable memory
d. shift registers memory

4. The main characteristics of on chip memory is

a. small and slow
b. large and slow
c. small and faster
d. large and faster

5. DRAM has a
a. smaller layout and uses large power
b. smaller layout and uses less power
c. more power and slower
d. more power and faster

6. SRAM has a
a. faster, more power and larger
b. slower, more power and larger
c. faster, less power and smaller
d. faster less power and larger

7. On chip memory is comes under the category of

 a. high density memory
b. medium density memory
c. low density memory
d. large density memory

8. On chip memory usually in the order of

a. 10k bytes
b. 50k bytes
c. 1k bytes
d. 100 k bytes

9. The simplest and safest way to use memory in a system is to treat it as a

a. sequential component
b. combinational component
c. decoders
d. NOR gates

10. Serial access memory at the chip level is classed as memory that has
a. shift registers
b. counters
c. accesstime is independent of location of data
d. internally stored data is used

11. which of the following is a non-volatile memory

a. DRAM
b. SRAM
c. Flash
d. None

12. Dynamic RAM is a type of RAM that only holds its data if it is continuously accessed by
special logic called a
a. Switch circuit
b. refresh circuit
c. capacitor circuit
d. schematic circuit

13. The simplest memory element is MOS technology is

a. Inverter
b. NAND gate
c. dynamic latch
d. single MOS transistor

14. Which of the following is fastest memory

a. SRAM
b. DRAM
c. ROM
 d. EPROM
15. on chip memory is comes under the category of
a. high density memory
b. medium density memory
c. low density memory
d. none
17. The process of entering information in EPROM is commonly known as
a. writing
b. programming
c. storing
d. none of the above.
18. Fusible link is associated with
a. EAROM
b. ROM
c. PROM
d. EPROM

19. Following is volatile memory

a.SRAM
b. ROM
c. DRAM
d. None

20. Which of the following can be reprogrammed

a. SRAM FPGA
b. Anti fuse FPGA
c. both
d. none
21. A ROM which can be programmed is called
a. MROM
b. PROM
c. EPROM
d. EEPROM
22. A 32 x 10 ROM contains a decoder of size
(a) 5 x 32 (b) 32 x 32 (c) 32 x 10 (d) 10x32
23. A 16 x 5 ROM stores
(a) 4 words of 16 bits each (b) 16 words of 5 bits each
(c) 16 words of 4 bits each (d) 5 words of 16 bits each

24. When the power supply of a ROM is switched off, its contents

(a) Become all zeros (b) become all ones (c) remain intact (d) are unpredictable
25. A ROM of size M x N bits can store

(a) N words of M bits each (b)M words of N bits each (c) M bits (d) N bits
26. The address bus with a ROM of size 1024 x 8 bits is

(a) 8 bits (b) 10 bits (c) 12 bits (d) 16 bits

27. A ROM has a 16-bit address bus. The number of locations in this memory is

(a) 16 (b) 32 (c) 1024 (d) 65536

28. It is desired to have a 64 x 8 ROM. The ROMs available are of 16 x 4 size. The number of
ROMs required will be

(a) 8 (b) 6 (c) 4 (d) 2

29. Four ROM chips of 16 x 4 size have their address buses connected together. This system will
be of size

(a) 64x4 (b) 16x16 (c) 32 x 8 (d) 256x 1

30. In a read-only memory information can be stored

(a) at the time of fabrication (b) by the user only once during its life time
(c) by the user a number of times (d) in any of the above ways

31. SRAM is ________ type of memory.

32. To have a ROM of size of 16KB,the number of 1024*4 ROMs required is ______

33. ROM structures belong to the class of the ______memories

34. A low power SRAM cell may be designed by using _______ inverter
35. In SRAM and Anti-fuse types of FPGA, switched connections are made between ______
lines.
36. Expand DRAM _________________________________.
31. _____memory examines data word and compares this data with internally stored data.
32. The contents of an______________________ can be erased electrically.
33. The contents of an F.PROM can be erased by exposing it to ________
34. A ROM of 128 KB can be used to design a combinational circuit of a maximum of
____variables.
35. The various types of ROMs arc ___________,____________and___________
36. A 16 x 5 ROM contains____________________________ a decoder.
37. ROM is a ________________________in which permanent information is stored.
38. Selective erasing is not possible in ____________but possible in______________
39. A ROM which can be programmed is called a_____________________________

REFERENCES:
1.Essentials of VLSI circuits and systems Kamran Eshraghian, EshraghianDougles and A.
Pucknell, PHI, 2005 Edition- CHAPTER 9 (pp: 236-255).
2. Introduction to VLSI Circuits and Systems - John .P. Uyemura, JohnWiley, 2003- CHAPTER
13 (pp: 483-513).

ANSWERS-UNIT-VI

1. a 13. c
2. c 14. d
3. b 15. c
4. c 16. a
5. c 17. b
6. b 18. c
7. a 19. c
8. b 20. a
9. c 21. b
10. a 22. a
11. a 23. b
12. b 24. a
25. b
26. b
27. d
28. c
29. a
30. b
31. Non-Volatile
32. 32
33. Non volatile
34. Cmos
35. Address lines and word
lines
36. Dynamic Random Access
Memory
37. CAM
38. EPROM
39. UV Rays
40. 7
41. PROM, EPROM,
E2PROM
42. 4x16
43. Non Volatile memory
44. EPROM, E2PROM
45. PROM
 UNIT-VII: SEMI CONDUCTOR INTEGRATED CIRCUITS
1. The PLA provides a systematic and regular way of implementing multiple output
functions of n variables in
a.
POS form
b.
SOP form
c.
complex form
d.
simple form
2. V(input variables) X P(product terms) PLA is to maintain generality within the
constraints of its dimensions then for
a.
AND gate have n inputs and output OR gate must have P inputs
b.
AND gate have P inputs and output OR gate must have n inputs
c.
Both AND gate and OR gate have n inputs
d.
both AND and or gates have P inputs
3. A MOS PLA is realized by using the gate of
a.
AND
b.
OR
c.
AND-OR
d.
NOR
4. A CMOS PLA is realized by
a.
pseudo nmos NOR gate
b.
CMOS NOR gate
c.
pseudo nmos NAND gate
d.
CMOS NAND gate
5. The mapping of irregular combinational logic functions into regular structures is
provided by the
a.
FPGA
b.
CPCD
c.
standard cells
d.
PLA
6. The general arrangement of PLA is
a.
AND/OR structure
b.
OR/AND structure
c.
NAND/NOR structure
d.
EX-OR/OR structure
7. V X P X Z PLA represents as
a.
V-no.of input variables ,P-no.of output functions ,Z-no.of gates
b.
V-no.of gates,P-no.of OR gates ,Z- no.of AND gates
c.
V-no.of input variables ,P-no.of product terms ,Z-no.of output functions
d.
V-no.of gates ,P-no.of AND gates ,Z-no.of output functions
8. To realize any finite state machine requirements, the PLA along with
a.
NOR gate is used
b.
feedback links is used
c.
NAND gate is used
d.
NOT gate is used
9. To reduce the PLA dimensions, the simplification must be done on a
a.
individual output basis
b.
multi-output basis
c.
individual product term
d.
individual input basis
10. The regularity of the PLA sturcture shows that both the AND and OR planes are
constructed from
a.
different standard cells
b.
standard cells are not used
c.
same standard cells
d.
feed back control links
11. The behavior AND/OR structure of a system may be capured in
a.
hardware description language
b.
software language
c.
tabulation method
d.
state design model
12. VHDL differs from other software languages by including
a.
behaviour of system
b.
compilers, debuggers and simulatois
c.
syntax
d.
machine understanding language
13. The advantage of fuse-based FPGAS compared to other FPGAs is
a.
allows large number of interconnections
b.
complex fabrication process
 c.
larger in size
d.
modified without changing hardware
14. Where the design is of moderate complexity and time to silicon is of paramount
importance then the probably suitable approach is
a.
FPGA
b.
PLA
c.
standard cell
d.
PAL
15. A single time programmable FPGA is the type of
a.
fuse-based FPGA
b.
SRAM-FPGA
c.
EPROM-FPGA
d.
Flash based FPGA
16. The SRAM-FPGA's consists of a large array of programmable logic cells known as
a.
Erasable programmable logic devices-EPLD
b.
configurable logic blocks-CLB
c.
micro cells
d.
AND/OR array
17. The fabrication process of EPROM-FPGA is
a.
easy and high integration density
b.
easy and low integration density
c.
complex and high integration density
d.
complex and low integration density
18. The following is a chip whose final logic sturcture is directly configured by the end user
a.
gate array design
b.
field programmable logic
c.
standard cell design
d.
full custom design
19. FPGA can be programmed as per the
a.
positive logic
b.
negative logic
c.
users logic
d.
fixed logic
20. The logic cells in FPGA contains
a.
only combinational circuits
b.
only sequential circuits
c.
both combinational & sequential circuits
d.
only Flip-Flop circuits
21. The individual cells of FPGA are interconnected by
a.
AND gates and switches
b.
matrix of wires and programmable switches
c.
OR gates and non programmable switches
d.
AND & OR gates
22. The programming in fuse-based FPGAS is done by
a.
configurable logic blocks
b.
memory cell
c.
multiplexer
d.
closing antifuse switches

23. A slew rate control is used in the I/O block of CPLD because of
a.
matching with other parts
b.
suppressing the occurrence of the noise
c.
grounding the I/O pin
d.
global tree state control
24. Which part of the CPLD is programmed to pass the latched or unlatched, true or
complement output to the external output
a.
AND gates of array
b.
OR gates of array
c.
I/O cell
d.
standard cell
25. A slew rate control in the I/O block of CPLD is used to make the rising and falling of the
output pulse
a.
zero
b.
one
c.
faster
d.
slow
26. A macro cell in CPLD is composed of
a.
J-K flip-Flop
 b.
R-S Flip-Flop
c.
T-Flip-Flop
d.
D-Flip-Flop
27. CPLD devices are used for design modification because these are
a.
reprogrammable
b.
non programmable
c.
always a fixed program
d.
design modificaions are not possible
28. CPLD is a devices of numeorus integrated SPLDs and interconnections between them is
a.
non programmable
b.
programmable
c.
used single SPLD
d.
permanent connections are used
29. To compose a circuit in case of CPLD, it has wiring among
a.
the pins
b.
the logic
c.
connection on printed board
d.
the function
30. CPLD is possible to rewrite it many times because
a.
it is records the contents of the circuit to the flash memory
b.
a standard cell is used
c.
it is a plastic loaded chip
d.
it is AND/OR array
31. The CPLD can be rewritable in about
a.
< 10times
b.
< 100 times
c.
< 1000times
d.
> 1000times
32. During programming of CPLD, the I/O pin is at the state of
a.
logic O
b.
logic 1
c.
high impedance
d.
open
33. The function block of CPLD consists of
a.
AND array, OR array and macro cell
b.
OR array, product term allocator and macrocell
c.
AND array, product term allocator and marcocell
d.
AND array, product term and OR array
34. In the standard cell, all the cells should have
a.
identical heights and widths
b.
identical heights and the widths of the cells may vary
c.
identical widths and the variable heights
d.
variable heights and widths
35. Cells in different rows of standard cells can be connected by using
a.
internal wires
b.
feed through cells
c.
intra wires
d.
route around a complete row
36. When a design is implemented in the standard cell design style
a.
only signal routing has to be done
b.
replacement of library cells
c.
change of the design fucntion
d.
change of placement of blocks
37. Standard cell designs are less area efficient than a full custom design due to
a.
feed through cells
b.
multiple cell rows
c.
fixed size of the cells
d.
lower clock rates
38. Where the design is of a reduced cost and include size memories the preferable approach
is
a.
FPGA
b.
gate array logic
c.
standard cell
d.
full custom
39. Logic gates are placed in rows of standard cells of
a.
equal height
b.
equal width
 c.
variable height
d.
constant width
40. Logic gate are placed in rows of standard cells are interconnected using
a.
internal wires
b.
intra wire
c.
routing channel
d.
switch box
41. Semicustom design using standard cells enable the designes to use
a.
a functional modules (available in library)
b.
a layout automatically generated
c.
an interconnections between cells
d.
only basic logic functions
42. In the standard cell design methodology
a.
each transistor is manually designed
b.
predefined logic and function blocks are available
c.
final logic structure is directly configured
d.
an array of unconnected logic gates
43. Standard cell designs are operate at
a.
higher clock rates and less area efficient
b.
lower clock rates and less area efficient
c.
lower clock rates and high area efficient
d.
higher clock rates and high area efficient

44. PAL16R8, here R denotes the

a.
number of inputs
b.
number of outputs
c.
active high
d.
presence of flip-flop
45. PAL10L8, here L denotes the
a.
active high
b.
active low
c.
number of inputs
d.
number of outputs
46. If one function depend on other functions in PAL then
a.
OR gate is used
b.
feed back is used
c.
ex-OR gate is used
d.
realization is not possible
47. One approach that is becoming more popular and feasible is to model chips as collections
of
a.
standard cells
b.
no.of gates
c.
reprogrammable gate arrays
d.
semicustom design sub systems
48. Programmable array logic provide a convinient way of realizing
a.
combinational networks only
b.
sequential networks only
c.
both combinational and sequential network
d.
not used for realization
49. Programmable array logic is made up of
a.
programmable AND and OR array
b.
programmable AND and fixed OR array
c.
Fixed AND and programmable OR array
d.
Fixed AND and OR array
50. The number of product terms in PAL depends on
a.
number of AND gates
b.
number of OR gates
c.
number of addition of both AND and OR gate
d.
independent of number of gates
51. To realise the sequential networks in PAL, the type of flip-flop used is
a.
D flip-flop
b.
T flip-flop
c.
J-K flip-flop
d.
R-S flip-flop
52. The combination PAL devices with active-low outputs mean
a.
AND-OR logic
b.
AND-NOR logic
 c.
AND-NAND logic
d.
NAND-OR logic

53. In order to realize a Boolean function with a combinational PAL device, the function
must be expressed in
a.
POS form
b.
SOP form
c.
Standard form
d.
complex form
54. When the PAL sequential device has a tristate buffer at the output stage then the type of
circuit implemented is
a.
sequential circuit
b.
product terms
c.
pos form
d.
combinational circuit
55. Different versions of PLDs are
a. PLA b.PAL c.PROM d.All

56. Which of the following can be reprogrammed

a. SRAM FPGA b. Antifuse FPGA c. Both d.None

57. The full form of ASIC is _____________

58. ASICs can be divided in to two basic categories as _____________ and _____________.

59.As compared to ASIC , the performance of PLD is ________

60. Which of the following are process technologies in CPLD

a.EPROM,EEPROM,AND FLASH b. SRAM,ANTIFUSE, & EPROM
b. FLASH, SRAM, & ANTIFUSE d. FLASH, DRAM & ANTIFUSE
61. In commercial FPGA chips, Look Up tables usually either 4 or 5 inputs which require
______ storage cells.
a. 16 and 24 b. 16 and 32 c. 8 and 16 d. 12 and 24
61. The following methods all are used to programm PLAs except
( a ) fusible links (b) UV-erasable EPROM ( c ) EEPROM ( d ) wafer lots

62. What is the most commonly used logic block in FPGA?

( a ) Look up table ( b ) diode- array ( c ) GAL array ( d ) CLBs

63. The programmable interconnect points are used to

 ( a ) connect the power to all blocks

( b ) connect the ground to all blocks

( c ) interconnect all the devices inside the CLBs

( d ) interconnect the global routing to CLBs

64. A type of package used to house CPLD chip is called ___________

65. The FPGAs are configured by ______________ method
66. FPGA based design has turn-around time ______ than ASIC based design
a. Less b. more c. equal d. more or less
67. Logic gate that used to measure the gate equalent/count in an IC is______
a. NOT gate b. 2-input NAND Gate
c. 2-input NOR gate d. 2-input XOR gate
69. PLA has
a. fixed OR plane followed by a programmable AND plane
b. programmable AND plane followed by fixed OR plane
c. fixed AND plane followed by programmable OR plane
d. programmable AND plane followed by Programmable OR plane
70. PAL has
a. fixed OR plane followed by a programmable AND plane
b. programmable AND plane followed by fixed OR plane
c. fixed AND plane followed by programmable OR plane
d. programmable AND plane followed by Programmable OR plane
71. In FPGA-based design, designers
a. design the layout and fabricate the IC
b. download the bit stream to program the device
c. both (a) and (b)
d. None
72. Different FPGA programming technologies are
a. antifuse b. SRAM c. EPROM d.all
73. LUT is used in
a.CPLD b. FPGA c. ASIC d. SPLD

74. Which of the following is not part of FPGA

a. RTL b. I/O c. PI d. CLB
75. SPLD is a macrocell which contains
a. And-OR array followed by flip-flop
b. a flip-flop
c. AND-OR array
d. AND array
76. SPLD contains sequential elements like Flip-Flops [true / false]

77. CPLD is more complex than FPGA in terms of architecture [true/false]

78. FPGA can be programmed only one time [true/false]

79. What does the term ASIC stand for?
(a) Application standard integrated chip

(b) Applied system integrated circuit

(c) Application specic integrated circuit

REFERENCES:

1.CMOS VLSI Design- A circuits and systems perspective, Neil H.E Weste, David Harris, Ayan
Banerjee, pearson, 2009- CHAPTER 10(pp: 407-443).
2. Introduction to VLSI Circuits and Systems - John .P. Uyemura, JohnWiley, 2003- CHAPTER
14 (pp: 558-564).

ANSWERS-UNIT-VII
1. b 6. a 11. a
2. a 7. c 12. b
3. d 8. b 13. d
4. a 9. b 14. a
5. d 10. c 15. a
16. b 58. Full custom,
17. d Semi
18. b Custom
19. c 59. Less
20. c 60. a
21. b 61. b
22. d 62. d
23. b 63. d
24. c 64. d
25. d 65. PGA
26. d 66. Programmin
27. a
g
28. b
67. a
29. b
68. b
30. a
69. d
31. d
70. b
32. b
71. b
33. c
72. d
34. b
73. b
35. b
74. a
36. a
75. a
37. c
76. True
38. c
77. True
39. a
78. False
40. c
79. C
41. a
42. b
43. b
44. b
45. b
46. b
47. c
48. c
49. b
50. a
51. a
52. b
53. b
54. d
55. d
56. a
57. Application
Specific
Integrated
Circuit
 UNIT VIII CMOS TESTING
1. For MOS circuits the dominant faults are due to
a. short circuits in diffusion layers
b. open circuits in diffusion layer
c. short circuits in interconnections
d. open circuits in interconnections
2. Very effective aid to testing and testability of a design is
a. a reset facility
b. facility to probe the circuit nodes
c. provide circuit modification
d. sealed in over glass
3. Correct operation of a design must not be dependent on
a. Rise times or fall times
b. short circuits in diffusion layer
c. Layout
d. short and open circuits in metal layer
4. Generally functional tests are impractical due to
a. fast simulation times and short verification sequences
b. fast simulation times and long verification sequences
c. slow simulation times and very long verification sequences
d. slow simulation times and short verification sequences
5. During testing of VLSI system (Indicate the false statement)
a. The chip is sealed by an over glass layer
b. circuits nodes cannot be probed for monitoring
c. circuits can be modified
d. circuits cannot be modified
6. The advantage of a reset facility in the design is
 a. testing always from fixed position
b. testing proceed from known conditions
c. testing proceed from unknown conditions
d. It is not related to testing

7. A 20 bit counter is split into four five bit section, them the required steps for testing are
a. 25
b. four sets of 25
c. five sets of 24
d. five sets of 25

8. Manufacturing tests are used to verify that

a. function of a chip as a whole
b. every gate operates as expected
c. function in the field
d. the clock response of the chip
9. VHDL, verilog hardware description languages are used for testing of
a. manufacturing tests
b. functionality test
c. Design testing
d. chip testing
10. Functionality tests seek to verify the
a. function of a chip as a whole
b. every gate operates as expected
c. function in the field
d. the clock response of the chip

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 11. Adhoc testability means
a. testability arrangements configured with the architecture changes
b. testability with structure changes
c. testability arrangements configured without changing the architecture
d. testability without structure changes
12. A measure of goodness of a test program is
a. the amount of fault coverage
b. time
c. cost
d. degree of performance
13. At the prototype state it is possible to provide special test points by
a. providing extra pads for probing
b. It is not possible to test
c. modifying the circuit
d. link connections
14. A finite state machine with 'n' possible inputs to the combinational logic and 'm' memory
elements then the required test vectors are
a. m+n
b. 2m
c. 2n
d. 2m+n
15. Generally the system is partitioned for testing because
a. reducing the chip area
b. reducing the no. of pads
c. reducing the number of test vectors
d. reduce the required power

16. The two key concepts underlying all considerations for testability are

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 a. set and reset
b. controllability and observability
c. initial and final conditions
d. pads and links
17. Controllability in testing means
a. being able to set known internal states
b. being able to generate all states
c. being able to generate all combinations of circuit states
d. read out the result of the state changes
18. Being able to generate all states to fully excise all combinations of circuit states is called
a. controllability
b. observability
c. combinationatorial testability
d. reset facility
19. Being able to read out the result of the state changes as they occur is called
a. controllability
b. reset facility
c. combinational testability
d. observability
20. The faults occur due to thin-oxide shorts or metal-to metal shorts are called
a. stuck at zero faults
b. short-circuit faults
c. open-circuit faults
d. bridge faults
21. Radom logic is probably best tested via
a. self testing
b. full serial scan or parallel scan
c. boundary scan

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 d. LFSR method
22. Self-test circuitry approach is based on
a. linear feedback shift registers only
b. linear feedback shift registers, exclusive-OR and clock system or gate
c. clock system only
d. inclusive OR gates only
23. The combination of LSSD scan path and linear feedback shift register is called
a. self test circuitry
b. signature analysis technique
c. structured testability
d. built-in logic block observation
24. In the following which one is correct with respect to BILBO testing for control inputs C 0=1,
C1=1
a. linear shift mode
b. signature analysis mode
c. data latch
d. reset mode
25. The control inputs in BILBO testing the corresponding mode is
a. linear shift mode
b. signature analysis mode
c. data latch
d. reset mode
26. In the BILBO arrangements, when C0=0, C1=1 then the corresponding mode is
a. linear shift mode
b. signature analysis mode
c. data latch
d. reset mode
27. The following the mode when C0=1, and C1=0 in the BILBO arrangement
a. linear shift mode
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 b. signature analysis mode
c. data latch
d. reset mode
28. On chip testing is obtained by using
a. self - test circuitry
b. adhoc testability
c. structured testability
d. LSSD approach
29. Signature analysis techniques are
a. on chip testing
b. structured testing
c. LSSD testing
d. adhoc testability
30. The manufacturing cost is low by detecting the malfunctioning of chip at a level of
a. wafer level
b. packaged-chip
c. system level
d. field
31. The tests that are usually carried after chip is manufactured are called
a. functionality test
b. design verification
c. manufacturing test
d. technology test
32. Generally memories are tested by
a. self-test
b. full serial scan
c. parallel scan
d. LFSR method

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 33. In order to reconfigure flip - flops appropriately, it is necessary to be able to include a double
throw switch in the
a. simple scan path
b. address path
c. control signal path
d. data path
34. The test access port or TAP controller in a boundary - scan system level testing is a
a. 16 - state FSM
b. 8 - state register
c. 8 - state interface pins
d. 16 - state NAND gates
35. The following path is used to reduce testing time in the LSSD
a. simple scan path
b. parallel path
c. single path
d. complex path
36. The test access port or TAP controller in a boundary - scan system - level testing has
connections of
a. one single bit
b. one multiple bits www.studentmoments.com
c. four or five single bit
d. one or two multiple bits
37. The instruction register (IR) in boundary-scan system level testing has to be at least
a. one bit long
b. two bit long www.studentmoments.com
c. there bit long
d. four bit long
38. Subsystems can be checked out individually by providing the appropriate
a. additional inlet/outlet pads

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 b. additional circuit nodes
c. additional links
d. It is not possible to check
39. The essence of the LSSD approach is to design all circuitry in a
a. transistor to transistor
b. transistor to register
c. register to register
d. register to transistor
40. In the structured testing technique, LSSD means
a. level scan sensitive default www.studentmoments.com
b. level simple scan design
c. level scan simple default
d. level sensitive scan design
41. In the LSSD approach the resisters behaves like a
a. shift register in operation mode and latch in test mode
b. shift register in test mode and latch in operation mode
c. shift registers in both test and operation mode
d. latch in both test and operation mode
42. The IEEE 1149 boundary scan is used for
a. chip level testing
b. design test
c. system level testing
d. circuit level testing
43. To increase the immunity to open - circuit faults usually involve incorporating
a. misaligned
b. connection redundancy
c. nature of defects
d. frequency of defects

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 44. To find the bridging faults, the following popular testing method is used
a. scan testing
b. I L A
c. I D D Q
d. self testing
45. The layout is tested by using
a. Design rule checker www.studentmoments.com
b. simulator
c. PROBE
d. BILBO
46. The layout modifications improves the performance
a. typically 10 % - 20 %
b. greater than 50 %
c. typically 100 %
d. typically 30 % to 50 %
47. NET is used to
a. verify its compliance with the design rules
b. extract the circuit from the mask layout
c. test for the number of contacts
d. simulate the leaf cell
48. PROBE is used to
a. verify the design rules
b. extract the circuit from the mask layout
c. layout testing
d. simulate the cell
49. To reduce parasitics, the changes are made in
a. circuit
b. transistor size

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 c. layout
d. logic
50. The steady state response to any allowed input state change is independent of the circuit and
wire delays within the system then this logic system is called
a. level-sensitive
b. finite state machine
c. stable - state
d. combinational logic circuit
51. Long counters are tested by
a. scan - based approaches
b. self test
c. built - in testing
d. ad-hoc testing
52. The following type of a fault should not disturb the functionality of the circuit
a. Delay fault
b. bridge fault
c. open circuit
d. stuck at faults

REFERENCES:
1.Essentials of VLSI circuits and systems Kamran Eshraghian, EshraghianDougles and A.
Pucknell, PHI, 2005 Edition- CHAPTER 10 (pp: 306-330).
2.CMOS VLSI Design- A circuits and systems perspective, Neil H.E Weste, David Harris, Ayan
Banerjee, pearson, 2009- CHAPTER 12 (pp: 539-551).

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 ANSWERS-UNIT-VIII

1. a 41. b
2. a 42. c
3. a 43. b
4. a 44. c
5. c 45. a
6. b 46. a
7. b 47. b
8. b 48. d
9. a 49. c
10. a 50. a
11. c 51. d
12. a 52. c
13. a
14. d
15. c
16. b
17. a
18. c
19. d
20. a
21. b
22. b
23. d
24. c
25. a
26. d
27. b
28. a
29. a
30. a
31. c
32. a
33. d
34. a
35. b
36. c
37. b
38. a
39. c
40. d

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