CIRCUITS AND

6.002 ELECTRONICS

Energy, CMOS

Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT
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6.002 Fall 2000 Lecture 23

 Review
VS
RL
2
VS
vO P=
vI RL + RON
RON

T1: closed open

T2: open R closed
1

S1 S2
VS +
C R2

1
T = T1 + T2 =
f
2
P = CVS f

Reading: Section 11.5 of A & L.

Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT
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6.002 Fall 2000 Lecture 23

 Review VS

Inverter RL
vO
vI RON C

1
Square wave input T= RL >> RON
2 f
V 2
P = S + CVS f T
>>" RC"
2 RL 2
Demo time constant
P STATIC P DYNAMIC
independent of f. related to switching
MOSFET ON half capacitor.
the time.
In standby mode,
In standby mode, half f0,
the gates in a chip can so dynamic power is 0
be assumed to be on.
So P STATIC per gate is
still VS2 .
2RL
Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT
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6.002 Fall 2000 Lecture 23

 Review
2
VS 2
P= + CVS f
2 RL
Chip with 106 gates clocking at 100 MHz
C = 1 f F, RL = 10 K , f = 100 10 6 , VS = 5 V
5 2
15 6
P = 10
6
+ 10 5 100 10
2

gates 2 10 10
3

= 10 6 [1.25 milliwatts + 2.5 watts ]
1.25KWatts + 2.5Watts
problem ! not bad

independent of f f
also standby power VS2
(assume MOSFETs reduce VS
ON if f 0) 5V1V
must get rid of this! 2.5V150mW

Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT
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6.002 Fall 2000 Lecture 23

 How to get rid of static power
Intuition:

VS VS
RL
RL
i vO high
vI high vO low vI low
MOSFET
RON off

idea !

VS

vI high vO low

Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT
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6.002 Fall 2000 Lecture 23

 New Device PFET

N-channel MOSFET (NFET)

D
on when vGS VTN
G off when vGS < VTN
e.g. VTN = 1V
S

P-channel MOSFET (PFET)

S
on when vGS VTP
G off when vGS > VTP
e.g. VTP = -1V
D 5V
ON when
less than 4V
Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT
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6.002 Fall 2000 Lecture 23

 Consider this circuit:
VS

S
PU = pull up
G D
vI vO
+ D
G PD = pull down
S

works like an inverter!

IN OUT

Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT
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6.002 Fall 2000 Lecture 23

 Consider this circuit:
works like an inverter!
IN OUT

vI = 5V (input high) vI = 0V (input low)

VS = 5V VS = 5V

RON p

vO vO
+ +
vI = 5V = 0V vI = 0V = 5V
RON n

Complementary
Called CMOS logic
MOS
(our previous logic was called NMOS)
Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT
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6.002 Fall 2000 Lecture 23

 Key: no path from VS to GND!
no static power!
Lets compute P DYNAMIC
VS
vI
T

vI vO
t
C 1
f =
T

closed for closed for

vI low vI high
RON p

VS +
C RON n

From
2
P = CVS f

Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT
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6.002 Fall 2000 Lecture 23

 For our previous example
C = 1 f F, VS = 5 V , f = 100 MHz , 1
2
P = CV S f
15
= 10 5 2 100 10 6
= 2 . 5 watts per gate
P = 2 . 5 watts for 10 6 gate chip

Gates f P keep
100 ~2.5 all
106 MHz watts Pentium? else
same
300 ~15
2x106 MHz watts PII?
600 ~30
2x106 MHz watts PII?
~240
s p !
8x106 1.2 GHz watts
~1875
PIII?
ga
25x106 3 GHz watts PIV?

Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT
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6.002 Fall 2000 Lecture 23

 How to reduce power

A VS 5V 3V 1.8V 1.5V
~PIV 170 watts better, but high

and use big heatsink

B Turn off clock when not in use.

C Change VS depending on need.
next time:
power supply
Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT
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6.002 Fall 2000 Lecture 23

 CMOS Logic
NAND:
VS
A B Z
0 0 1
A B 0 1 1
1 0 1
1 1 0
Z
A

5V 5V

0V S
on 5V S
off
G D G D

Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT
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6.002 Fall 2000 Lecture 23

 In general, if we want to implement F

VS e.g. F = A B = A + B
short short when
when F A = 0 or B = 0,
is true,
else open open otherwise
A
Z
B short
when F short when
is true, A B is true,
else open else open

m b er
reme gans law
eM o r
D

Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].

6.002 Fall 2000 Lecture 23