Documente Academic
Documente Profesional
Documente Cultură
Course Objectives
Nc
A
BTS PSTN
Mc
BSC
BTS
Inter-PLMN
Gb Nb
Iur-g
MGW GMGW
IuCs
NodeB
RNC IuPs
NodeB
SGSN GGSN
What does "i" stand for?
iBSC
intelligent integration
intelligent identification of wireless integrates multi-interfaces
access intelligent error E1/STM-1/IP integrates multi
self-correction transmission supported
immensity intensify
large capability intensified design
supports 3072 TRX and 15000 Erl supports FR/EFR/HR/AMR/WB-AMR,
with only two racks innovative NetSpeed wireless
enhanced technology
IP
All-IP platform
supports IP bearer
ZXG10 iBSC Product Features
Based on V3 universal hardware platform
All IP hardware architecture
Large capacity and strong processing
capabilities
Modular design with good scalar
Separation of control streams from media
streams
Supporting Flex A and Flex Gb
Coding scheme: FR/HR/EFR/FR-ARM/HR-
AMR
Transmission interface: E1/T1/FE/STM-1
Easy and smooth upgrade
Flexible networking modes
High integration and low power consumption
Universal All IP Hardware Platform
Universal
Hardware Platform
Totally 16 boards
Smooth
All IP Upgrade
CDMA 2000 NGN Modularity
Modular Design
Boards
z Different software can be used to define
different functions for the same board.
z AIU, BIU, PCU and TCU are logical units; All
interface units are in the resource shelf.
Easy Scalability
z The system can be
expanded via adding
RCBUs.
z 3 RCBUs/2 racks.
Multiple Access Modes and Smooth Evolution
iBSC supports multiple access modes
z E1/T1
z STM-1
z FE/GE
Evolution
Advantages
Advantages
••Saves
Saves20%
20%space
spacewhen
when2G 2Gand
and3G
3G
iBSC iBSC iBSC modules
modulesare
areintegrated
integratedinto
intothe
thesame
same
site.
site.
RNC RNC&BSC ••Shares
Sharescabinets,
cabinets,spare
spareparts,
parts,
BSC RNC RNC&BSC transmission and OMM.
transmission and OMM.
BSC BSC RNC&BSC ••Saves
Savespower
powerconsumption
consumption
BSC BSC RNC&BSC
••Saves
Saves engineeringand
engineering andnetwork
network
upgrade cost
upgrade cost
ZXG10 iBSC Interfaces
Logical
No. Link Object Interface Type
Interface
1. A MSC STM-1, E1, FE/GE
Number
Abis Number of Interface Number of
Interface
Cabinet of Interface Capacity Interface Capacity
Carriers Capacity Carriers
Carriers
A Single Abis:208 E1(T1) Abis:208 E1(T1) Abis:208 E1(T1)
1024 1024 1024
Cabinet A:188E1(T1) A:4 pairs of STM-1 A:1 pair of GE
E1(T1) Abis
Abis:624 E1(T1) Abis:624 E1(T1) Abis:624 E1(T1)
Dual Cabinets 3072 3072 3072
A:700E1(T1) A:11 pairs of STM-1 A:2 pairs of GE
Abis:3 pairs of
A Single Abis:3 pairs of STM-1 Abis:3 pairs of STM-1
1024 STM-1 1024 1024
Cabinet
A:188E1(T1) A:4 pairs of STM-1 A:1 pair of GE
STM_1 Abis
Abis:9 pairs of
Abis:9 pairs of STM-1 Abis:9 pairs of STM-1
Dual Cabinets 3072 STM-1 1024 3072
A:700E1(T1) A:11 pairs of STM-1 A:2 pairs of GE
Major Interfaces
z Abis – IP over E1, E1, IP
z A – TDM (E1, STM-1), IP
z Gb – TDM (E1), IP
z (Ater)
Boards
ZXG10 iBSC Shelves
Control Shelf (BCTC)
System control and management
Rear Board
system clock, manages the
control plane, and responsible
for the switch between the
control plane and the Ethernet
Front Board
Each iBSC must be configured
with one control shelf, which is
located in Shelf 2 in Rack 1
No. Board Name Number Slot No. Backup
1 OMP 2 11–12 1+1
2 CMP 2~4 1~4 1+1
3 CHUB 2 15~16 1+1
4 ICM 2 13~14 1+1
5 UIMC 2 9~10 1+1
6 SBCX 2 5,7 1+1
BCTC Working Principles
BPSN BGSN
The clock generation board
(ICM) distributes clock signals to UIMC GUIM
the switch shelf and resource
shelves through cables. 8K/16M
OMP and SBCX boards are UIMC ICM
CHUB
connected to the iOMCR
through the hub to sever intranet
Ethernet
segments from Internet
segments.
CMP OMP SBCX
The CHUB acts as the control BCTC
stream convergence center for
the control streams from the
switch shelf, the resource shelf
HUB HUB
and the control shelf.
Outside
network
Introduction to BGSN
Gigabit Resource Shelf
Provides system external 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
interfaces.
Rear Board
R R R R R
R R
S D S G G
D S
Processes universal services. P
B
T
B
P
B
U
M
U
M
T P
B B
1 2
Acts as the Level 2 switch
BGSN
center.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
The BGSN is configured in
Front Board
G S S G G G D E G S
D P U U
U P U I U P
Shelf 1 and Shelf 3 of the P B
T
B
B P I I
T
B P P B
2 2 2 2 M M I 2 2
main rack. When a single
shelf constitutes an office, it is
configured in Shelf 2.
No. Board Name Number Slot No. Backup
1 GUIM 2 9~10 1+1
2 GIPI - 1-8,11-17 1+1
3 GUP2 - 2-8,11-16 -
4 DTB 0-8 1-8,11-14,17 -
5 SDTB2 - 1-8,11-16 1+1
6 SPB2 - 1-8,11-17 -
7 EIPI - 1-8,11-17 -
BGSN Working Principles
The GUIM board is the
convergence and switch center for BPSN BCTC
various data in the resource shelf. It
completes the information exchange GLI CHUB ICM
between modules.
The GUIM board interconnects with
the GLI board in the packet switch BGSN
shelf to carry out level 1 switch GUP2 GUP2 GUIM
between different resource shelves.
DTBs and SPBs provide E1
interfaces, and SDTBs provide
STM-1 access.
GIPI boards provide FE and GE SDTB 2 DTB SPB2 GIPI
access.
Processes universal services STM-1 E1 E1 FE GE
(conversion from TC and TDM to IP
packets, processing of user plane
protocols).
Introduction to BPSN
Interconnects BGSNs and Packet Switching Shelf
user plane.
Rear Board
R R
U U
I I
Each iBSC should have one M M
2 3
BPSN, which is configured in
BPSN
Shelf 4.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
If the iBSC has two BGSNs,
Front Board
U U
then the BPSN is not G
L
G
L
G
L
G G
L L
G
L
P
S
P
S
C C
M M
C C
M M I I
I M M
I I I I I N N P P P P
mandatory. However, this can C C
PWRD PWRD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
FAN FAN
G G R R R R
S G D D D G D D S S S G S R R R R R R G G R R R
P U U U U D P P P U P S D D D D D U U D S S S S
T T T T T
B P P I I T B B B P B P T T T T T M M T P P P P
B B B B B M M B
2 2 2 2 2 2 2 2 B B B B B B 1 2 B B B B B
R R
D G G D D G D D G G D G D D G G D R R R R R G G R R R R
U U U U U U U U D D D D D U U D D D D
T P
P T T P T T I I T P T T P P T T T T T T M M T T T T
B 2
2 B B 2 B B M M B 2 B B 2 2 B B B B B B 1 2 B B B B
FAN FAN
R R
S G D D D G D D G G D S S G S R R R R R R R R R R
P U U U U P U P D D D D G G D
T P S D S S S
B P T T T P T T I I B B P B P T T T T T U U T P P P
B M M
2 2 B B B 2 B B M M 2 2 2 2 B B B B B B B B B B
1 2
R R
D G G D D G D D G G G D D G G D R R R R R G G R R R R
D
U U U U U U U U D D D D D D D D D
T P U U
P T T P T T I I T P T T P P T T T T T T M M
T T T T
B 2
2 B B 2 B B M M B 2 B B 2 2 B B B B B B 1 2
B B B B
FAN FAN
Cabinet Configuration (2)
Abis Interface IP
A-Interface IP
Cabinet Configuration (3)
A-Interface IP
Contents
CP FE
What
What are
are the
the CPU Core
Ethernet
OMC2
functions
functions of
of the
the
RPU?
RPU? Logic Unit
Power
Management
RS485,RS232 GPS485
PD 485
RS232
RS232
CPU Core RS485 DEBUG1- 232
1. Enables intranet addresses within the
BSC to communicate with each other. HD Disk
OMC1
Ethernet
2. Provides routes for the operation and CP FE
DEBUG 232
Logic Unit Clock Unit CPU DEBUG FE
Inner Bus
CP FE, CP GE CLKIN
Ethernet
Switch Unit
CHUB
The CHUB works together with the UIMC/GUIM to be
responsible for control plane data stream exchange and
convergence in the system.
The control plane data from each shelf is sent to the
Ethernet switching unit of CHUB board through the
Ethernet cables on the control plane.
The data is then sent to UIMC board of the BCTC
through GE for level-2 switch, and then distributed to
each CMP board for processing.
CHUB
The RCHB1 board has three FE buses, on which FE interfaces are grouped as
FE1–8, FE9–16 and FE17–24.
The RCHB2 board has three FE buses, on which FE interfaces are grouped as
FE25–32, FE33–40 and FE41–46.
DEBUG FE/232
Logic Unit CPU
Inner Bus
CP GE
Ethernet Ethernet
Switch Switch
Ethernet
Switch Unit
RS232
CPU
RS485
Inner Bus
SBCX
The SBCX board is the server board. It mounts the server
on the rack.
It provides the keyboard, the mouse and the VGA
interface.
Uses Sossaman dual-path dual-core CPU with a
frequency of 2G Hz.
Supports multiple operating systems, including Windows
XP/2000/2003, Linux and Solaris.
Provides three FE interfaces, two GE interfaces and one
RS232 serial port.
Provides four universal USB interfaces.
Supports boot from hard disk and boot from USB drive.
SBCX
OMC1(eth3) is set to an external network address to communicate with
NetNumen M31 server.
OMP1(eth6) is set to an intranet address to communicate with the
OMP.
DTB
Provides 32 E1/T1 links for external connections.
Supports extraction of 8K synchronization clock from the
lines, which is transferred to the CLKG/ICM board through
the cable as clock reference.
Supports 120/75 Ω impedance selection for E1 cables,
and supports coaxial cables and twisted-pair cables.
Supports 100 Ω twisted-pair T1 cables.
DTB
8KOUT/DEBUG-232
CP FE ,RS232,RS 485
CPU
Clock
Clock Unit
Logic Unit
E1/T1 1~32
Circuit Switch HW
Interface Unit
Unit
DTP DIP Switches
DTP DIP Switches
DIP Switch Configuration Default Location
Purpose
Switch Mode 1 2 3 4 1 2 3 4
Used to set the
resistances that 75 Ω ON ON ON ON
S1~S6
match the
S9 ON ON ON ON
impedances of
S12 120 Ω OFF OFF OFF OFF
different E1 paths to
75 Ω or 120 Ω.
Used for indicating
the receiving 75 Ω ON ON ON ON
S7 matching
ON ON ON ON
S8 impedance of
corresponding E1 120 Ω OFF OFF OFF OFF
chip to the CPU.
SHORT
Used for reporting ON ON ON ON
HAUL
S10 the long/short wire
ON ON ON ON
S11 status of each E1 LONG
chip to the CPU. OFF OFF OFF OFF
HAUL
RDTP Jumpers
On the RDTB, the E1 cable
works in the 75 Ω unbalanced
coaxial transmission mode by
default.
If the E1 line uses 120 Ω
balanced transmission mode,
the short-circuit block at X9–
X16 on the RDTB needs to be
removed.
The sending end is grounded
through the jumper. The
receiving end is connected to
a capacitor and then grounded
through the jumper. Jumpers
X9–X16 are used to complete
such settings.
RDTP Jumpers
X9-X16 Pin Connection Definitions
8KOUT/DEBUG-232
CP FE ,RS232,RS 485
CPU
Clock
Clock Unit
Back Board
Logic Unit
STM-1
Circuit Switch HW
Interface Unit
STM-1 Unit
SPB2
According to its functions, the SPB2 board can be classified into the
LAPD processing board (LAPD2), the signaling processing board
(SPB2) and the Gb interface processing board (GIPB2).
The LAPD2 board processes LAPD signaling. LAPD signaling data
from the BTS are received by the DTB/SPB/SPB2 board, and then
switched to the LAPD2 board through the circuit switching net on the
UIM board in the local resource shelf or the GUIM board in the local
Gigabit resource shelf. The LAPD2 completes the processing of
LAPD signaling data.
The SPB2 board processes MTP2 and X.25 protocols. It supports
extraction of 8 K synchronization clock from the lines, which is
transferred to the CLKG board through the cable as clock reference.
The GIPB2 board processes the FR, NS and partial BSSGP protocols
for the GPRS, and provides Gb interfaces.
SPB2
Back Board
SPB2
Interface unit, which connects with the switching unit and
provides E1 interfaces.
Circuit switch unit, which implements the switching
between interface unit circuits and backplane circuits.
CPU, which implements signaling processing, board
management and internal connection control.
Ethernet Switch Unit, which implements control plane and
user plane data switch and provides FE interfaces.
Clock Unit, which extracts line clock signals and sends
them to the ICM board.
Each SPB2 board contains four CPUs.
Each SPBs board provides 16 E1/T1 interfaces.
GIPI
The GIPI board provides IP interfaces between iBSC and
the BTS, the SGSN and the MSC/MGW.
Implements Layer 3 protocol interface processing,
separates control plane data from user plane data, and
sends the data respectively to the Ethernet interfaces on
the internal control plane and user plane.
According to functions, GIPI can be classified into four
functional boards:
Abis interface Gigabit IP interface board(IPBB)
A interface Gigabit IP interface board IPAB(Signaling)
A interface Gigabit IP interface board IPI (signaling and service)
Gb interface Gigabit IP interface board(IPGB)
GIPI
The Interface Unit receives data and sends it to the service processing unit,
which separates user plane data from control plane data. User plane data is
then sent to the GUP2 through the user plane switch network, and control
plane data is sent to the CMP through the control plane switch network.
The GIPI board can choose RGER (providing one GE interface) or RMINIC
(providing four FE interfaces) as its rear board.
Back Board
EIPI
The EIPI board provides E1 or T1 based IP connection and
works together with the DTB. It has no external interface
and no rear board. One EIPI works together with two DTBs
to provide up to 64 E1 or T1 ports.
EIPI
The interface unit receives HW data and sends it to the HPS daughter
card. The data is then processed according to the HDLC protocol and
then sent to the service processing unit. It sends user plane data
through the user plane switch network to the GUP2 for processing, and
sends control plane data through the control plane switch network to
the CMP for processing.
GUIM
The GUIM performs Ethernet Level 2 switching between the control
plane and the user plane in the Gigabit resource shelf, the CS field
timeslot multiplexing slot switching and Gigabit resource shelf
management. It also provides external interfaces for the Gigabit
resource shelf.
It has the capability of 16 K circuit switching, and provides an internal
circuit switching network for the GE resource shelf.
It provides the clock drive in the resource shelf. It inputsPP2S, 8K
and 16M signals, which are sent to different slots in the resource
shelf after phase lockup to provide 16M, 8 K and PP2S clocks for
resource modules in this shelf.
The UGIM board performs Gigabit resource shelf management and
provides RS485 management interfaces in the Gigabit resource shelf;
It also provides board resetting and in-slot signal collection functions.
GUIM
Circuit
Switch Unit
HW
Inner Bus
DEBUG 232
Logic Unit Clock Unit CPU
Inner Bus
CLKIN
CP FE 1~6
User Plane Control Plane
Switch Switch
GUP2
According to functions, GUP2 boards are classified into five functional
boards: Abis interface processing board BIPB2, A interface
processing board AIPB, user plane processing board UPPB2, dual
rate transfer board DRTB2 and Ater interface processing board TIPB2.
z Over the STM-1 or E1 Abis interface, CS and PS services from the BTS
are switched to the BIPB2 board through the UIM board in the local
resource shelf or the GUIM board in the local Gigabit resource shelf. The
BIPB2 board searches 20ms TRU frames or PCU frames and form them
into IP packets, which are sent to the TCU or the UPU for processing.
Over the IP Abis interface, the BIPB2 board is also used to process RTP.
z The DRTB2 implements code conversion, finishes TRAU frame conversion
and rate adaptation, and provides FR/EFR/HR/AMR/TFO function.
z The AIPB board processes RTP and forms data into IP packets over the A
interface.
z The UPPB2 processes user plane protocols such as BSSGP, PDCP and
GTP_U under the A/Gb mode.
GUP2
Each GUP2 board has 15 DSPs.
Back Board
…
GUP2
CPU: responsible for board management, and provides
control plane FE interfaces for external connection.
DSP: processes universal services, including functions of
BIPB2, AIPB, DRTB2, UPPB2 and TIPB2.
Circuit Switch Unit: connects the serial ports of multiple-
chip DSP with the circuit switching network.
Ethernet Switch Unit: implements the Ethernet
connections for multiple-chip DSP and provides the user
plane FE interface for external devices.
Clock Unit: provides necessary clock signals for the units
on the board.
GLI
The GB Line Interface (GLI) board is located at level 1
switching subsystem of iBSC. It finishes physical layer
adaptation, IP package query, segmentation, forwarding,
and flow management functions, processes bi-directional
2.5Gbps forwarding, and implements the interfaces to
different resource shelves and external interface
functions.
GLI
Interface Unit: provides GE optical interface and supports physical
backup. SD1–SD2, SD3–SD4, SD5–SD6 and SD7–SD8 are backup
groups.
Processing Unit: implements bi-directional IP packet table look-up,
fragmenting, forwarding and traffic management.
Queue Management Unit: implements bi-directional queue
management.
The GE optical interface receives user plane data from the GUIM and
sends it through the backplane to the PSN board for user plane data
exchange.
SD1~SD8 (GE Optical)
Optical&Ethernet Queue Management
Back Board
Processing Unit
Interface Unit Unit
CP FE
Logic Unit CPU
PSN
Provides bi-directional Inner bus
user plane data switch CP FE
CPU
with a capacity of 40
Gbps on each direction
The data from each GLI
board is sent to the Matrix
Switching Unit through
the high-speed serial
links on the backplane. It
is switched and then sent Logic Unit
to the destination GLI
board.
Matrix Switch Unit
Peripheral Monitor Unit (PMU)
BGSN BGSN
GUIM GUIM
UIMU( UIM_2) UIMU( UIM_2)
User Control User Control
Circuit Circuit
plane plane plane plane
DTB
GUP2 SPB2 GUP2 GIPI
SDTB2
E1 STM-1 IP
CMPU
UPU
Access Switch
TC Unit
BTS Unit Unit
O& M Unit
MSC PMU
SGSN
iBSC External Physical Interfaces
A Gb
iBSC
Abis Ater
E1 Abis
z E1 borne TDM link
IP Abis
z FE/GE borne IP link
IPoE Abis
z E1 borne IP link
BIU - E1 Abis
9The interface board can be the DTB or SDTB2 board. The access
capacity of SDTB2 is four times that of the DTB.
GUP2
GUIM
DTB
SPB2
GUP2 GUP2
GUP2
BIU - IP Abis
GIPI
GUP2 GUP2
GUP2
BIU - IPoE Abis
EIPI
DTB
Access Unit- A Interface Unit (AIU)
E1 A
z E1 borne TDM link
IP A
z FE/GE borne IP link
AIU - E1 A
E 1A
AIU
1
TCU 2
DTB
32
GUP2
GUIM
1
SPB2
2
16
Control Plane Switching Network MTP2
Internal
E1/ T1 Ethernet HW STM -1
AIU - IP A
IP A
AIU
IPI AIPB
RTP RTP
UDP UDP
BIPB2
to CMP
External Internal
Ethernet Ethernet HW
Access Unit–Gb Interface Unit (GIU)
E1 Gb
z E1 borne TDM link
IP Gb
z FE/GE borne IP link
GIU - E1 Gb
E 1 Gb
UPPB2 GIU
1
2
User Plane 16
Switching
UDP
Network 1
2
16
Control Plane Switching Network
to CMP
Internal
E1/ T1 Ethernet
GIU - IP Gb
IP Gb
GIU
IPGB UPPB 2
UDP UDP
BIPB 2
to CMP
Control Plane Switching Network
External Internal
Ethernet Ethernet HW
O&M Unit
OMP Board
z System operation and maintenance;
z Connects to the iOMCR;
z System management and monitoring
OMPP
HH
OMP UU LMT -R
OMP
BB
SBCX
SVB
100 M Ethernet
Operation and Maintenance Networking
The networking mode of SBCX is as follows: iBSC and
SBCX(OMP1) form a subnetwork, and
SBCX(OMC1)+NetNumen for a subnetwork. The local
OMM usually consists of the SBCX and the SBCX client
(LMT).Usually, LMT and the OMM client are installed on
the same PC. The PC is then put in a different equipment
room. The network interfaces of SBCX are connected to
the switches of each iBSC, and then connected to the
router. Then the cables are connected to the remote
NetNument using WAN connection.
When the iBSC needs to manage SDR BTSs, the OMCB
server manages all SDR configurations (physical,
transmission and radio configurations), links, alarms and
versions. The OMCB program is installed on the SBCX
and a pair of GIPI boards must be configured.
Operation and Maintenance Networking
Processing Units & Monitoring Units
CMP OMP
Control Plane Signal Flow in the CS Domain
Abis interface signal flow Abis interface unit (BIU) sends signaling in the
LAPD channel to the CMP board as control plane data. The CMP
processes such data and sends some of it directly back to the BIU (flow
direction: 1→1). Some signaling data will be sent to the AIU in the form of
A-interface signaling flow (flow direction: 1→2).
A-interface signal flow: The AIU processes the MTP2 part of A-interface
signaling, and then sends it to the CMP to complete the processing of
MTP3 and layers above. Some global processes need the participation
of the OMP. The data flow direction is 2→3→3→2 or 2→2.
Control Plane Signal Flow in the PS Domain
For some control plane signaling in the PS field, the system requests
resources from the CMP board, and then sends the signaling to the
UPPB2 for processing.
When the MS is processing PS services, control plane signaling should
be separated from UPPB2 and then sent to the CMP for processing.
UPU TCU
CMP OMP
Control Plane Signal Flow in the PS Domain
Abis interface signaling flow
z The Abis interface unit (BIU) sends control plane data in
the LAPD channel to the CMP board. The CMP
processes such data and sends some of it directly back
to the BIU (flow direction: 1→1). Some data, such as
packet assignment messages, is sent to the UPU,
which processes the data and then sends it to the BIU
through the user plane switch network (flow direction:
1→3→2).
z Data from the Abis interface unit is sent to the UPU
through the user plane switch network. The UPU
processes the data and separates control signaling
packets, which are sent to the control plane processing
board (CMP).The data flow direction is: 2→3→3→2.
Control Plane Signal Flow in the PS Domain
Gb interface signaling flow
z The GIU sends BVC channel data as control plane data to the
active CMP. The CMP processes the data and sends some of it
(such as PTP BVC restart) to other CMPs and some (such as
signaling BVC restart) to the OMP. The CMP or the OMP
processes the data and some signaling generates the Abis
signaling traffic, such as paging messages in the PS or CS field,
whose data flow is 5→1 or 5→3→2; other signaling, such as PTP
BVC restart acknowledgement and signaling BVC restart
acknowledgement, is sent to the Gb interface through the GUI, with
the data flow as 5→5 or 6→6.
z The GUI routes data from other BVC channels to the user plane
processing unit, which separates control plane data and sends it to
the CMP. The CMP processes the data and some signaling, such
as PTP paging messages, is sent to the Gb interface through the
GIU with the data flow as 4→3→5; some signaling generates the
Abis signaling flow, such as location messages, with the data flow
as 4→3→1.
User Plane Board Signal Flow in the CS Domain
E1 Abis, E1 A
E1 Abis E1 A
A iOMCR Client
Control Plane Board Signal Flow in the CS Domain
E1 Abis, E1 A
E1 Abis E1 A
iOMCR Client
User Plane Board Signal Flow in the CS Domain
IP Abis, IP A
BPSN BCTC
¾ The BIU severs CPU SBCX
frames from all frames PSN UIMC UIMC OMP HUB
and sends them to the
UPU(UPPB) through the
user plane switching GLI GLI CHUB CMP
UIMC OMP
485 Signal
GLI UIMC CHUB CLKG
PWRD
in Each
User
Control Rack
Plane GUIM
Ethernet Plane CLKG
Ethernet
BGSN1
User Plane Ethernet UIMC
GUIM
Circuit Switch
BGSN2 Shelf
System Clock Capture and Distribution
Principles
The CLK board is responsible for
supplying clock signals and BITS interface,Line 8K reference GPS reference
external synchronization
functions. BCTC
each shelf.
Control Plane and Ethernet Interconnection
Cables
The FE interfaces of the
CHUB rear boards connect
to the FE interfaces of the
UIM boards in each shelf.
Internal GE connection is
used inside the BCTC.
User Plane Optical Cable Connection
The optical interface on the
GUIM front panel in the Power distribution subrack
BGSN connects to the Fan subrack
optical interface on the PLI G
U
front panel. BGSN I
M
Supports physical backup.
U C
O I
I H
BCTC M C
M U
P M
C B
G
U
BGSN I
M
U
G
I
BPSN L
M
I
C
Monitoring Cables
The cables between fans to PWRD Sensor
boards are usually 120 ohm
twisted-pair cables that are Cabinet-top fan
connected to the FANBOX
Power distribution subrack
interfaces to monitor fan running
status. Fan subrack
G
The environment monitoring sensor BGSN
U
I
is connected to the SENSORS M
U C
interface on the PWRD board to I
O
M
I
C
H
BCTC M U
collect environment alarms. C
P M
B
Fan subrack
The door access sensor is
G
connected to the DOOR interface U
BGSN I
on the PWRD board to monitor door M
access status. G
U
I
BPSN L
M
The PWRD board reports I
C