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Basic Analog Layout Techniques

Presentation August 2015

DOI: 10.13140/RG.2.1.4599.5285

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Analog Layout Techniques

MEAD course on "Advanced Analog CMOS IC Design"

EPF-Lausanne, August 24-28, 2015

BASIC ANALOG LAYOUT TECHNIQUES

Eric A.Vittoz
evittoz@ieee.org

MOS transistors.
CMOS compatible bipolars.
Resistors and capacitors.
Control of absolute values.
Matching.
Parasitic effects.
Long-range coupling.

E. Vittoz, 2015
Analog Layout Techniques
LA-1
INTRODUCTION

Why is analog layout so different from digital layout?

signals electrical
represented by: processing with:
numbers
DIGITAL (codes) regeneration

ANALOG physical no regeneration

values
Related layout topics (V, I, Q, f) distortion noise

Variety of sizes and shapes

Absolute values (as few as possible)
Matching (designs based on ratios)
Parasitics
Long-range coupling

E. Vittoz, 2015
 Analog Layout Techniques
LA-2
TRANSISTOR LAYOUT
G L = Lm + L
minimum size poly Si metal
Wm W = Wm + W
given by layout rules S D
mask drawing
contact window Lm n+ diffusion electrical

L and W include process effects

wide L includes -2Llat.diff. thus <0

D D

G Wm Wm Lm
Lm G
min. diffusion min. S and D resistance
S areas S
G
long S D
Wm
Lm
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 Analog Layout Techniques
LA-3
VERY WIDE TRANSISTORS

W L, use source and drain "fingers"

minimum size minimum S and D series resistance:

minimum junction area Lm
S
S

W
Lm

D
G
G D
contacts to metal all along the fingers
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Analog Layout Techniques
LA-4
VERY WIDE TRANSISTORS FOR RF OR LOW-NOISE

Minimum S, D and G series resistance

no metal possible above gate
Lfinger limited, specially with short Lm
( increased polysilicon sheet resistivity due to grain size).
D Lm

Lfinger

S
G can be reduced if many
metal layers
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 Analog Layout Techniques
LA-5
CLOSED TRANSISTOR STRUCTURES
Maximum /Drain-junction area
No side of channel (lower leakage and/or noise)

Minimum size Multiple structure:

drain inside waffle-shaped transistor
D
G W
D
S
Lm

S
G D
G
S
Large W/L per area
Low S,G,D series resistance
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Analog Layout Techniques
LA-6

VERY LONG TRANSISTOR

Serpentine structure
L W

Wm
S G

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 Analog Layout Techniques

CMOS COMPATIBLE BIPOLAR TRANSISTORS LA-7

(n-well process pnp transistors)

Substrate current must be recaptured locally
B n-well
Simple vertical bipolar (grounded collector):
safer to surround the base by the collector contact. E V-
C
MOS transistor operated as a lateral bipolar:
for max. value of and : - closed with E centered
- min. bottom area of E
Minimum-size device: Optimum lateral bipolar:
B p+diffusion
G n+diffusion
n+ diff. G
n-well
V- E
p+ diff. n-well C
substrate C E
B
contact
V-
large Rbb' min. Rbb'
small substrate contact surrounded by substrate contacts to V-
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Analog Layout Techniques
LA-8
RESISTORS

Long, narrow bar in a resistive layer (polysilicon, diffusion,...)

small L/W Wm large L/W

Lm

Wm resistive
layer L

end uncertainty
contact resistance may be folding uncertainty
non-negligible

E. Vittoz, 2015
 Analog Layout Techniques

LA-9
CAPACITORS
Inter-layer capacitors (vertical field):
layer 1
compensation layer 2
tab Wm
area depends on alignement
Lm
clearance larger than
maximum mask misalign
Intra-layer capacitors (lateral field):
applicable when the electrode thickness is larger than the feature size.
d1
electrode 1 d1, d2: minimum
same layer
electrode 2 d2

Combination of vertical and lateral fields: cross section: electrodes

1 2 1 2
increased capacitance per unit area layer 2
reduced bottom plate capacitance
layer 1
may be extended to more layers 2 1 2 1
may be further increased by vias. substrate
E. Vittoz, 2015
Analog Layout Techniques
LA-10
BETTER CONTROL OF ABSOLUTE VALUES
a) Good control of geometries: avoid uncertainties
Example: folding- and end-effects in a resistor:
resistor n-well resistor
(or non-salicided poly)
(high resistivity)
n+ diffusion (or salicided poly)
(low resistivity)
b) Non minimum dimensions:
Any value X (X=, C, R,...) is proportional to a specific value Xs
(Xs=Cox,C/unit area, Rs...) by: X = Xs W1L1
L W
Now: L = Lm + L and W = Wm + W with and 1
L W
Xmax-Xmin Xsmax-Xsmin Wmax-Wmin Lmax-Lmin
Thus: = + +
X Xs W L
indep. of W,L should be made negligible
very large (5 to 50%)
Good designs minimize the dependency on absolute values.
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 Analog Layout Techniques

LA-11
MATCHING OF DEVICES

Allows circuit design based on ratios of values

Rules for optimum matching:
Devices to be matched should have:
1. Same structure
2. Same temperature
3. Same shape and same size
4. Minimum distance
5. Common centroid geometries
6. Same orientation on the chip
7. Same surroundings (same neighbourhood)
8. Non-minimum size.

The relevancy and the quantitative importance of each rule depend

on the particular process and the particular device under consideration.
E. Vittoz, 2015
Analog Layout Techniques

LA-12
MATCHING: SAME TEMPERATURE

Negligible dissipation on chip:

no problem for constant ambient temperature T
possible small T at fast transients of ambient T.
Heat generation on chip:
place devices to be matched
- close to each other
- as far as possible from the source of heat
- on the same isotherm
- exploit the symmetry axis of the chip

matched symmetry axis

devices of the chip
source of heat
isotherm
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 Analog Layout Techniques

LA-13
MATCHING: SAME SHAPE, SAME SIZE

Examples:
Resistors Transistors Capacitors
(4 squares) (W/L=2) (area A)

A Reference

A Good

A Bad

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 Analog Layout Techniques

LA-14
MATCHING: MINIMUM DISTANCE

To take advantage of spatial correlation of fluctuating parameters

Example:

Multiple current mirror

A B C D

A B C D

BAD GOOD ...but requires more wiring

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Analog Layout Techniques
LA-15
MATCHING: COMMON-CENTROID GEOMETRIES
For compensation of constant gradients
Best solution: "quad" of similar devices grouped in two pairs
Principle Example for a pair of transistors
D1
G2
1/2 1/2
device 2 device 1

1/2 1/2
device 1 device 2 S

G1
D2
Simpler solution
D1 D2
1/2 1/2 1/2 1/2
dev.2 dev.1 dev.1 dev.2

S G1 G2
Does not respect rule 7 (same surroundings)
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 Analog Layout Techniques
LA-16
MATCHING: SAME ORIENTATION

To eliminate possible differences due to:

unisotropic substrate
unisotropic process steps
stress before and/or after packaging.

Example: implementation of a differential pair.

D2 D1 D2
D1 D1 D2 D1 D2

S
S S S

obviously very bad bad better for this rule good

E. Vittoz, 2015
Analog Layout Techniques
LA-17
MATCHING: SAME SURROUNDINGS

Various possible reasons, not always clear

May be ensured by implementing dummy structures.

Example: multiple current source:
I1 I2 = I3 I4

dummy devices added (not used in circuit)

This "end effect" is also found in 2-D arrays
(first and last rows and columns different from rest of array)

If the reason is known, surroundings can be simulated by an

adequate structure (see later: implementation of ratio of capacitors)
E. Vittoz, 2015
 Analog Layout Techniques
LA-18
MATCHING: NON-MINIMUM SIZE

a. Effect of uncorrelated spatial fluctuations of specific parameter xs

(for example tox)

Definition: Xs = spatial average of xs(y,z)

Xs1 = Xs - Xs/2 xs constant Xs2 = Xs + Xs/2

z
L L L
W y W W
device 1 ideal device: Xs xs device 2

It can be shown that:

(Xs) 1/ WL (statistical averaging of xs over area WL)

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 Analog Layout Techniques
LA-19
MATCHING: NON-MINIMUM SIZE

b. Effect of uncorrelated periphery fluctuations:

W- W/2 device 1 ideal W device 2 W+ W/2

L- L/2 L L+ L/2

Now: (W)1/ L width W is averaged along length L

(L)1/ W length L is averaged along width W

+: area WL
and relative mismatch: (WL1)/(WL1) = W/W L/L
: ratio W/L

(WL1) 1 1 1 1 1
Thus: 1
2 + 2 = +
WL W L L W WL L W
Minimum for a square shape
E. Vittoz, 2015
 Analog Layout Techniques
LA-20
MATCHING FOR NON UNITY RATIOS
Rational ratios n/m with m and n integers
use m+n identical devices
matching rules can be respected
example: ratio of capacitors C1/C2 = 3.5 =7/2
almost common centroid C2
compensation tabs:- non aligned
- aligned to connect
C1
dummy structure for homogeneous etching

Any ratio: violation of matching rules; effect must be minimized

examples: resistors: capacitor:
- approximation by n/m - same area/perimeter ratio A/P
A=WL
P=2L
L1 R1 R2 L2 L2
W A/P=W/2
W
L1
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 Analog Layout Techniques
LA-21
PARASITIC EFFECTS

Various types of parasitic effects: Result in various possible effects:

capacitance to ground speed/bandwidth reduction
capacitance from node to node degradation of precision
series resistance of layers distortion of characteristics
parallel conductances degradation of CMRR and PSRR
leakage currents noise / feedthrough / interactions
re-collection of minority carriers losses
long-range coupling .....

Ways to solve the problem:

Identify the critical nodes and loops, then:
eliminate the parasitic
minimize it
or compensate it (by matched structures)

E. Vittoz, 2015
 Analog Layout Techniques
LA-22

LONG-RANGE COUPLING

Cohabitation on same chip of:

DIGITAL or 120 dB of
HIGH-LEVEL ANALOG LOW-LEVEL ANALOG
attenuation
(volts) (microvolts)
may be required
Coupling mechanisms (decreasing importance):
power lines: use - separate V+,V- and ground
- wide conductors
resistive (through substrate)
capacitive (in air)
thermal (via substrate)
by minority carriers.

E. Vittoz, 2015
 Analog Layout Techniques
LA-23
RESISTIVE COUPLING THROUGH SUBSTRATE
direct connection capacitive bipolar
V V I=IC
I CV
I=
p+ n+ p+
p p p
n
coupling to substrate

I injection zone critical sensitive zone

V- d1 V distance D d V-
1 V2 2
p+ p-substrate p+

r1 Rr1,r2 r2
coupling from substrate:
r1 r2
Solutions: V2
direct connection
I
minimize d1 and d2 R
substrate modulation.
maximize D capacitive (drain, pad, bottom
p layer on grounded p+substrate plate of capa)
put critical zones in (or on) special wells
e.g.: capacitors on special grounded well.
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 Analog Layout Techniques
LA-24
CAPACITIVE COUPLING THROUGH AIR

distance D
noisy area A1 sensitive area A2
C12C2 C12
V1 V2 V1
C2
silicon substrate (ground) C2
A1 and/or A2:
diffusion (drains) 0A1A2
2
If D A1 and A2, then: C12 =
interconnections 3
2D
pads
Numerical examples (for 120dB attenuation):
A1 [m2] A2 [m2] C2 [fF] C12max [F] Dmin [m]
10 10 5 5.10-21 30
10000 10 5 5.10-21 300
10000 10000 100 100.10-21 1120

Possible improvements:
reduce A1 and/or A2
increase distance D
shield A1 and/or A2.
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 Analog Layout Techniques
LA-25
COUPLING BY MINORITY CARRIERS

Carriers released at blocking of the channel of

any digital transistor
analog switches.
May be collected by a sensitive junction.

In the substrate: In a well:

sensitive sensitive
blocked channel junction blocked channel junction
n+ n+ n+ p+ p+ p+
n-well n p
electrons guard p holes

avoid close proximity provide separate wells

collect by a guard well

E. Vittoz, 2015
 Analog Layout Techniques

REFERENCES
1. J . L. McCreary, "Matching properties, and voltage and temperature dependence of MOS capacitors", IEEE Journal of
Solid-State Circuits, vol. SC-16, pp.608-616, Dec. 1981.
2. J. B. Shyu et al., "Random errors in MOS capacitors", IEEE Journal of Solid-State Circuits, vol. SC-17, pp.1070-1076,
Dec.1982
3. J. B. Shyu et al, "Random errors effects in matched MOS capacitors and current sources"", IEEE Journal of Solid-State
Circuits, vol.-19, pp.948-955, Dec.1984.
4. E. A. Vittoz, "The design of high-performance analog circuits on digital CMOS chips", IEEE Journal of Solid-State
Circuits, vol. SC-20, June 1985
5. K. R. Lakshmikumar et al., "Characterization and modeling of mismach in MOS transistors for precision analog design",
IEEE Journal of Solid-State Circuits, vol. SC-21, pp.1057-1066, Dec.1986.
6. M. Pelgrom et al.,"Matching properties of MOS transistors", IEEE Journal of Solid-State Circuits, vol. 24, pp.1433-1440,
Oct.1989.
7. B. R. Stanisic et al.,"Addressing substrate coupling in mixed-mode IC's: simulation and power distribution synthesis",
March 1994.
8. M. J. McNutt et al.,"Systematic capacitance matching errors and corrective layout procedures", IEEE Journal of Solid-
State Circuits, vol. 29, pp.611-616, May 1994.
9. J. D. Bruce et al.,"Analog layout using ALAS", IEEE Journal of Solid-State Circuits, vol. 31, pp.271-274, Febr. 1996.
10. H. Samavati et al.,"Fractal capacitors", IEEE Journal of Solid-State Circuits, vol. 33, Dec. 1998.
11. K. Okada et al.,Layout dependent matching analysis in CMOS circuits", Analog Integrated Circuits and Signal Processing,
vol.25, pp.309-318, Dec. 2000.

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