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Contents
1. Introduction .......................................................................................................................................... 3
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Xilinx ISE Simulation Tutorial
1. Introduction
Xilinx is a powerful software tool that is used to design, synthesize, simulate, test and verify
digital circuit designs. The designer (you in this case) can describe the digital design by
either using the schematic entry tool or a hardware description language. In this tutorial, we
will create VHDL design input files the hardware description of the logic circuit, compile
VHDL source files, create a test bench and simulate the design to make sure of the correct
operation of the design (functional simulation). The purpose of this tutorial is to give new
users an exposure to the basic and necessary steps to implement and examine your own
designs using ISE environment. In this tutorial, we will design one simple module (OR gate);
however, in the future, you will be designing such modules and completing the overall circuit
design from these existing files.
Entity Declarations: module name and interface specifications (I/O) list of input
and output ports; their mode, which is direction of data flow; and data type.
Architecture: defines a components logic operation.
As you will learn (or have learned) in this course, there are different styles for the
architecture body:
A combination of these could be used, but in this tutorial we will use Dataflow. In
its simplest form, the architectural body will take the following format, regardless
of the style:
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After creating an account, install Xilinx software: ISE 14.7 from the website at
http://www.xilinx.com/support/download/index.htm
For a step by step process of downloading and installing Xilinx ISE WebPack (student
version), go to the appendix at the end of tutorial.
For extra help with the installation, go to:
http://www.xilinx.com/support/documentation/dt_ise.htm
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1 2 3 4
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2. In the Name field enter a short name for your project that correctly describes what
you are designing (For now we will use ORgate). Also, make sure that your project
name:
o Starts with a letter
o Contains only alphanumeric characters and underscores
o Cannot contain two consecutive underscores.
3. Click the Browse icon (pointed by the arrow in the Figure above) in order to select
the desired location to which you would like to save your project.
4. In the Top-level source type field, make sure that HDL is selected this is selected
if the top level design to be used is in VHDL or Verilog, which can include lower
level modules such as HDL files, schematics or different types.
5. Click Next
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6. In the Project Settings page shown below, ensure that the following options are set
because they effect the types and processes that will be available for your design:
o Product Category All
o Family Spartan3E
o Device XC3S500E
o Package FT256
o Speed -5
o Top-Level Source Type HDL (automatically selected)
o Synthesis Tool XST (VHDL/Verilog), which is a technology to
synthesize VHDL, Verilog, or mixed language designs to create Xilinx-
specific netlist files.
o Simulator ISim (VHDL/Verilog), allows for running integrated
simulation process as part of your ISE design flow.
o Preferred Language VHDL
In order to open an existing project in Xilinx, select File Open Project to show the
lists of projects available in a certain directory, choose the project you want and check
OK
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9. Click Finish and you will exit the New Project Wizard and be taken back to the
original ISE Project Navigator window, but a new project hierarchy is generated
with the ORgate design file displayed in the Hierarchy Pane as shown in Figure
6.
The Create New Source Wizard will enable you to create a VHDL source input file
(.vhd) for a combinational logic design that will contain information about the design of
the 2-input or gate. (Any other text editor can be used to do so)
1. Click on the New Source icon , which is to the left of the Hierarchy Pane.
This can also be done by right clicking on ORgate source file in the Hierarchy
Pane and clicking New Source, as shown in Figure 7. This will take us to the
New Source Wizard as shown Figure 8.
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Create New
Source
Add Source
Add Copy of
Source
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2. Select VHDL Module as a source file type to be added to the project since our files
will contain VHDL design code, so our files will have .vhd extension.
3. In the File name field, enter a name of the entity for which you are creating input
and output ports for. Remember to follow the conventions mentioned earlier (in
Section 4, step 2) for naming the project. In this case, enter ORgate.
4. For the Location field, click the browse icon to navigate to the appropriate folder,
which should be the same one used for creating the project.
5. Make sure that the Add to project checkbox is selected to automatically add this
source to your project so that you dont need to add it to the project again manually.
6. Click Next, the wizard will take you to the Define Module page as shown below,
where I/O of the module (OR gate) will get defined. As you can see, the entity name
is there, but can be changed if you want and the architecture name is Behavioral by
default.
7. Direction field is used to describe the mode, which is how data is transferred
through the port. We are concerned with 3 modes: in data flowing into the port; out
data flowing out of the port; inout data flowing into and out of the port (bi-
directional). Since we have 2 inputs and 1 output, in the first 3 fields under port name,
we type a, b and c and set the Direction fields as in for the first two fields
and out for the third field (c).
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8. Click Next to view and verify the summary of the information about the new
source created. If any changes are to be made, just click cancel.
9. After making sure that the description of the module is correct, click Finish. The
source file will be now displayed in ISE Project Navigator as shown below; the
workspace window will be used as a text editor to make necessary changes to the
source file. All the input and output ports that we specified will be displayed.
Figure 11: VHDL source code editor window in the Project Navigator
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In the statement part, we will write one statement that describes how our or gate works, in
the following manner:
After writing the statement, we click save icon to save our work or do it through File Save
Note: VHDL programs can be edited using any text editor (not recommended) and then
add them to the project directory using Add Copy of Source icon .
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1. Make sure that Implementation checkbox is checked from the View Pane in the
Design Panel.
2. From the Process Pane in the Design Panel, double click on the Synthesize
XST function as shown in Figure 13, which will check the syntax of your code and give
you warning and error messages if any are present in the Transcript Window, where
you can click Errors or Warnings tab. Errors are indicated by next to the
message and warnings are indicated by . You can right click the message and select
Search for Answer Record to open the Xilinx website and show any related answer.
Otherwise, you can just right click the message and select Go to Source to go directly
to the error. These errors must be corrected, saved, and fresh synthesis (compilation)
needs to be done again before you move to the next step; otherwise, you wont be able to
simulate your design. After correcting the errors (if any), the synthesis process runs
After a successful Synthesis, you will get a message as shown in Figure 13.
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8. Simulation of Design
In order to do functional and timing simulation, we will create a test bench for our VHDL
code which will help in debugging our design. This allows us to verify that our design
functions as expected (given inputs in our truth table, we get desired outputs). In order to test
the gate completely, we shall provide all the different input combinations.
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2. From the Select Source Type options select VHDL Test Bench
3. In the File name field choose a name that signifies the test bench and adheres to the
naming conventions mentioned earlier. Type testorgate
4. For the Location field, click the browse icon to navigate to the appropriate folder,
which should be the same one used for creating the project.
5. Click Next
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6. The following window allows you to select which design you want to create a test
bench for, in our case ORgate since it is the only module we have; however, for
your future designs, you can make test benches for individual components of your
designs as well as the top-level design which ties it all together.
7. Click Next
8. A summary window like the one shown below will appear, click Finish
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9. Now you will view the test bench file (testorgate.vhd), shown below, that Xilinx has
generated in the workspace window.
Now going to our test bench file, we can see that it consists of the same two main parts of
a normal VHDL design, which is the entity and architecture. The entity is left blank
because we are simply supplying inputs and observing outputs to the design in test. The
architecture part will consist of the design we are testing as a component, input and
output signals, a port map of the component for the UUT (Unit Under Test), a process to
run the clock and a stimulus process, which will be responsible for running the tests that
are written to test the design.
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10. Lets modify the default code by removing the highlighted code shown below, which
is the clock process that is generated by default, which divides the clock period by
two. We also want to remove the stimulus process.
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11. Replace the deleted code with the following code segment, which will perform a
very simple initial test of the design for simulation by giving different values of
inputs:
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In our modified code, we have chosen to wait for 100 ns, which means the time delay for
which the input has to maintain the current value; i.e., after 100 ns have elapsed the next
set of values can be assigned to the inputs.
12. The testbench file does not appear in the Hierarchy Pane of the Design Panel.
This is because there is a separate view for implementation and test files. In order to
view test files, select the box of Simulation in the View Pane of the Design
panel. In the Process Pane, double click on the Behavioral Check Syntax to
make sure that you didnt make any syntax errors while making changes.
13. Save your work.
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14. Double click on Simulate Behavioral Model in the Process Pane, which will
open the ISim software with your test bench loaded.
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15. ISim simulator window will open with your simulation executed, as shown in Figure
22, where you are able to simulate your designs and check for errors. You can step
through your VHDL designs and check the states of signals and set the simulation to
run for specific period of time. Make sure to check the results of the simulation output
against your truth table results to verify the correctness of the design. The resolution
of the simulation is set to 1 picosecond to ensure correct processing of your design.
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16. To get a better view of the simulation waveforms, from the tool bar, click on View
Zoom Full View or use F6 or click on the shortcut Zoom to Full View icon
. This will give you a better view of what your simulation is doing.
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17. In the text box located near the run button, you may specify amount of time for the
simulation to run; the button to the left of the box will execute the simulation for the
time you have specified. After setting the new simulation time, click on Re-Start to
clear the previous simulation result and then click on Run to start simulating with
new time setting. Below is an example of 2us of simulation time:
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18. You can change the default simulation run time. This will help to avoid setting the
run time again every time you launch the simulation. This can be done by setting the
properties of your project in Xilinx. Right click on Simulate Behavioral Model, and
then click on Process Properties An ISim property window will appear. You can
modify the simulation run time from value textbox as in Figure
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19. In some cases, you want to change the display format of a specific signal from binary
format into other format. This can be done by doing a right click on that signal, then
click on Radix and choose your desired display format. Below is an example of
changing display format from binary number to hexadecimal number:
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20. When your design is big, it is not easy to just look at into your HDL code to find the
mistake. In this case, you may want to see the internal signals of a specific component
to see if it is working properly or not. To do this, you will need to open both panels
Instances and Processes and Objects
Click on utt in Instances and Processes panel, then all of the instantiated
components will be listed. Then, click on a specific instantiated component. All of
the signals belongs to this component will appear in the Objects panel. Now, you
can drag and drop these signals into the waveform panel then restart and run your
simulation again to see the values of these signals. The figure 29 is an example of
displaying signals of program counter component in a CPU.
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9. Simulation Printouts
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2. ISim Print Setup window like the one shown in Figure 25 will appear, from Time
Range select the checkbox for Full Simulation.
Good Luck!
Youre all set to start using the Xilinx ISE Simulator to write VHDL code for digital circuits,
synthesize and simulate your designs. Save often, watch out for syntax errors, correct your errors
before proceeding to simulating your design, and remember to include enough input cases in
your test bench to verify the correctness of your design. Dont worry if the different styles of
architectural body seem a little confusing now, you will get into more depth in class and a good
bit of practice is necessary to use them effectively.
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Appendix Downloading and Installing Xilinx ISE Webpack (Student Version 14.4)
1. Navigate to http://www.xilinx.com/support/download/index.htm
2. Click on the appropriate file download for your system, mostly Full Installer for
Windows
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3. You will be redirected to a Sign in page. If you already have an account, sign in using
your username and password; otherwise create an account.
4. You will be directed to a Download Manager page and prompted in the top bar of
your window whether you give permission to run it, so click run and download will start.
5. The downloaded tar file might not be recognized by your computer so I recommend
downloading WinRAR free trial from http://www.rarlab.com/download.htm or any
program of your own choice.
6. Unzip the file all files will be extracted to a folder as shown below.
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7. Double click the folder shown in the figure above, and then double click on xsetup.exe
to start installation.
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11. Choose directory of file, click Next on the following two windows, and then click
Install.
12. When the installation is done, Xilinx License Configuration Manager will pop up so
you can obtain a free license. Click Get Free ISE WebPack License in the Acquire
a License tab.
13. Click Next where you will be directed to Xilinx webpage.
14. Log in using your username and password.
15. At the following window ensure that Vivado and ISE Suit: WebPack License is
checked and click on Generate Node-Locked License.
16. Click Next on the Generate License window that pops up.
17. Click Next on the Review License Request window.
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18. Click the download button from the manage licenses tab.
19. You will be presented with a Congratulations window for successfully generating a
license and a .lic file will be downloaded in your Downloads folder.
20. In the Xilinx License Manager window, click on Copy and the license will be
copied to Xilinx directory.
You are now able to use the ISE Design Suite 14.4.
References
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