1) In logic synthesis, ________ is an EDIF that gives the description of logic cells

& their interconnections.

a. Netlist
b. Checklist
c. Shitlist
d. Dualist

2) Which among the following functions are performed by MSI category of IC

technology?

a. Gates, Op-amps
b. Microprocessor/A/D
c. Filters
d. Memory/DSP

3) Which among the following EDA tool is available for design simulation?

a. OrCAD
b. ALDEC
c. Simucad
d. VIVElogic

4) Which among the following operation/s is/are executed in physical design or

layout synthesis stage?

a. Placement of logic functions in optimized circuit in target chip

b. Interconnection of components in the chip
c. Both a and b
d. None of the above

5) Which among the following is/are taken into account for post-layout
simulation?

a. Interconnect delays
b. Propagation delays
c. Logic cells
d. All of the above

6) Which level of system implementation includes the specific function oriented

registers, counters & multiplexers?

a. Module level
b. Logical level
c. Physical level
d. All of the above

7) In VLSI design, which process deals with the determination of resistance &
capacitance of interconnections?

a. Floorplanning
b. Placement & Routing
c. Testing
d. Extraction

8) _________ is the fundamental architecture block or element of a target PLD.

a. System Partitioning
b. Pre-layout Simulation
c. Logic cell
d. Post-layout Simulation

9) Which among the following is a process of transforming design entry

information of the circuit into a set of logic equations?

a. Simulation
b. Optimization
c. Synthesis
d. Verification
10) The utilization of CAD tools for drawing timing waveform diagram and
transforming it into a network of logic gates is known as ________.

a. Waveform Editor
b. Waveform Estimator
c. Waveform Simulator
d. Waveform Evaluator

11) Which type of simulation mode is used to check the timing performance of a
design?

a. Behavioural
b. Switch-level
c. Transistor-level
d. Gate-level

14) Which among the following is an output generated by synthesis process?

a. Attributes & Library

b. RTL VHDL description
c. Circuit constraints
d. Gate-level net list

15) Register transfer level description specifies all of the registers in a design &
______ logic between them.

a. Sequential
b. Combinational
c. Both a and b
d. None of the above

16) In synthesis process, the load attribute specifies the existing amount of
_________load on a particular output signal.

a. Inductive
b. Resistive
c. Capacitive
d. All of the above
17) Which attribute in synthesis process specifies the resistance by controlling
the quantity of current it can source?

a. Load attribute
b. Drive attribute
c. Arrival time attribute
d. All of the above

18) Which type of digital systems exhibit the necessity for the existence of at
least one feedback path from output to input?

a. Combinational System
b. Sequential system
c. Both a and b
d. None of the above

19) The output of sequential circuit is regarded as a function of time sequence of

__________.
A. Inputs
B. Outputs
C. Internal States
D. External States

a. A & D
b. A & C
c. B & D
d. B & C

20) The time required for an input data to settle _____ the triggering edge of clock
is known as 'Setup Time'.

a. before
b. During
c. After
d. All of the above
21) Hold time is defined as the time required for the data to ________ after the
triggering edge of clock.

a. Increase
b. Decrease
c. Remain stable
d. All of the above

22) An Antifuse programming technology is predominantly associated with _____.

a. SPLDs
b. FPGAs
c. CPLDs
d. All of the above

23) Which type of MOSFET exhibits no current at zero gate voltage?

a. Depletion MOSFET
b. Enhancement MOSFET
c. Both a and b
d. None of the above

24) In enhancement MOSFET, the magnitude of output current __________ due to

an increase in the magnitude of gate potentials.

a. Increases
b. Remains constant
c. Decreases
d. None of the above

25) Which among the following can be regarded as an/the application/s of MOS
switch in an IC design?

a. Multiplexing & Modulation

b. Transmission gate in digital circuits
c. Simulation of a resistor
d. All of the above
26) Which among the following is/are regarded as an/the active resistor/s?

a. MOS diode
b. MOS transistor
c. MOS switch
d. All of the above

27) In CMOS circuits, which type of power dissipation occurs due to switching of
transient current and charging & discharging of load capacitance?

a. Static dissipation
b. Dynamic dissipation
c. Both a and b
d. None of the above

28) According to the principle of current mirror, if gate-source potentials of two

identical MOS transistors are equal, then the channel currents should be _______

a. Equal
b. Different
c. Both a and b
d. None of the above

29) PSSR can be defined as the product of the ratio of change in supply voltage to
change in output voltage of op-amp caused by the change in power supply &
_______ of op-amp.

a. Open-loop gain
b. Closed-loop gain
c. Both a and b
d. None of the above
30) Which among the following serves as an input stage to most of the op-amps
due to its compatibility with IC technology?

a. Differential amplifier
b. Cascode amplifier
c. Operational trans conductance amplifiers (OTAs)
d. Voltage operational amplifier

31) Timing analysis is more efficient with synchronous systems whose maximum
operating frequency is evaluated by the _________path delay between
consecutive flip-flops.

a. shortest
b. average
c. longest
d. unpredictable

32) An ant fuse element initial provides ______ between two conductors in
absence of the application of sufficient programming voltage.

a. Conduction
b. Insulation
c. Both a and b
d. None of the above

33) Maze routing is also known as ________

a. Viterbi's algorithm
b. Lee/Moore algorithm
c. Prim's algorithm
d. Quine-McCuskey algorithm

34) Maze routing is used to determine the _______path for a single wire between a
set of points, if any path exists.

a. Shortest
b. Average
c. Longest
d. None of the above

35) In a chip, which type/s of pad design/s is/are adopted to solve the problem of
pin count?
a. Input pad design
b. Output pad design
c. Three state pad design
d. All of the above

36) The power consumption of static CMOS gates varies with the _____ of power
supply voltage.

a. square
b. cube
c. fourth power
d. 1/8 th power

37) Which factor plays a crucial role in determining the speed of CMOS logic gate?

a. Load capacitance
b. Supply voltage
c. Gain factor of MOS
d. All of the above

38) In high noise margin (NMH), the difference in magnitude between the maximum
HIGH output voltage of driving gate and the maximum HIGH voltage is recognized
by the _________gate.

a. Driven
b. Receiving
c. Both a and b
d. None of the above

39) In two-stage op-amp, what is the purpose of compensation circuitry?

a. To provide high gain

b. To lower output resistance & maintain large signal swing
c. To establish proper operating point for each transistor in its quiescent state
d. To achieve stable closed-loop performance

40) According to the principle of current mirror, if gate-source potentials of two

identical MOS transistors are equal, then the channel currents should be _______

a. Equal
b. Different
c. Both a and b
d. None of the above
41) In logic synthesis, ________ is an EDIF that gives the description of logic cells
& their interconnections.

a. Netlist
b. Checklist
c. Shitlist
d. Dualist

42) Which level of system implementation includes the specific function oriented
registers, counters & multiplexers?

a. Module level
b. Logical level
c. Physical level
d. All of the above

43) Which among the following operations are executed in physical design or
layout synthesis stage?

a. Placement of logic functions in optimized circuit in target chip

b. Interconnection of components in the chip
c. Both a and b
d. None of the above

44) After an initialization phase, the simulator enters the ______phase.

a. Compilation
b. Elaboration
c. Execution
d. None of the above

45) Which concept proves to be beneficial in acquiring concurrency and order

independence?

a. Alpha delay
b. Beta delay
c. Gamma delay
d. Delta delay
46) An event is nothing but ______ target signal, which is to be updated.

a. Fixed
b. Change on
c. Both a and b
d. None of the above

47) Which functions are performed by static timing analysis in simulation?

a. Computation of delay for each timing path

b. Logic analysis in a static manner
c. Both a and b
d. None of the above

48) Which among the following are regarded as the functions of translation step in
synthesis process?

a. Conversion of RTL description to Boolean unoptimized description

b. Conversion of an unoptimized to optimized Boolean description
c. Conversion of unoptimized Boolean description to PLA format
d. All of the above

49) In synthesis flow, which stage/s is/are responsible for converting an

unoptimized Boolean description to PLA format?

a. Translation
b. Optimization
c. Flattening
d. All of the above

50) In synthesis flow, the flattening process generates a flat signal representation
of _____levels.

A. AND
B. OR
C. NOT
D. EX-OR
a. A & B
b. C & D
c. A & C
d. B & D

51) In floor planning, placement and routing are __________ tools.

a. Front end
b. Back end
c. Both a and b
d. None of the above

52) In floor planning, which phase/s play/s a crucial role in minimizing the ASIC
area and the interconnection density?

a. Placement
b. Global Routing
c. Detailed Routing
d. All of the above

53) In CMOS inverter, the propagation delay of a gate is the/an _________

transition delay time for the signal during propagation from input to output
especially when the signal changes its value.

a. Highest
b. Average
c. Lowest
d. None of the above
54) In pull-up network, PMOS transistors of CMOS are connected in parallel with
the provision of conducting path between output node & Vdd yielding _____
output.

a. 1
b. 0
c. Both a and b
d. None of the above

55) For complex gate design in CMOS, OR function needs to be implemented by

_______ connection/s of MOS.

a. Series
b. Parallel
c. Both series and parallel
d. None of the above

56) In MOS devices, the current at any instant of time is ______of the voltage
across their terminals.

a. constant & dependent

b. constant & independent
c. variable & dependent
d. variable & independent

57) On the basis of an active load, which type of inverting CMOS amplifier
represents low gain with highly predictable small and large signal characteristics?

a. Active PMOS load inverter

b. Current source load inverter
c. Push-pull inverter
d. None of the above

58) An ideal op-amp has ________

a. Infinite input resistance

b. Infinite differential voltage gain
c. Zero output resistance
d. All of the above

59) Chip utilization depends on ___.

a. Only on standard cells

b. Standard cells and macros
c. Only on macros
d. Standard cells macros and IO pads

59) In Soft blockages ____ cells are placed.

a. Only sequential cells

b. No cells
c. Only Buffers and Inverters
d. Any cells

60) Why we have to remove scan chains before placement?

a. Because scan chains are group of flip flop

b. It does not have timing critical path
c. It is series of flip flop connected in FIFO
d. None

61) Delay between shortest path and longest path in the clock is called ____.

a. Useful skew
b. Local skew
c. Global skew
d. Slack

62) Cross talk can be avoided by ___.

a. Decreasing the spacing between the metal layers

b. shielding the nets
c. Using lower metal layers
d. using long nets

63) Pre-routing means routing of _____.

a. Clock nets
b. Signal nets
c. IO nets
d. PG nets

64) Which of the following metal layer has Maximum resistance?

a. Metal1
b. Metal2
c. Metal3
d. Metal4
65) What is the goal of CTS?

a. Minimum IR Drop
b. Minimum EM
c. Minimum Skew
d. Minimum Slack

66) Usually Hold is fixed ___.

a. before Placement
b. After Placement
c. Before CTS
d. After CTS

67) To achieve better timing ____ cells are placed in the critical path.

a. HVT
b. LVT
c. RVT
d. SVT

68) Leakage power is inversely proportional to ___.

a. Frequency
b. Load Capacitance
c. Supply voltage
d. Threshold Voltage

69) Filler cells are added ___.

a. Before Placement of std cells

b. After Placement of std Cells
c. Before Floor planning
d. Before Detail Routing

70) Search and Repair is used for ___.

a. Reducing IR Drop
b. Reducing DRC
c. Reducing EM violations
d. None

71) Maximum current density of a metal is available in ___.

a. .lib
b. .v
c. .tf
d. .sdc

72) More IR drop is due to ___.

a. Increase in metal width

b. Increase in metal length
c. Decrease in metal length
d. Lot of metal layers

73) The minimum height and width a cell can occupy in the design is called as ___.
a. Unit Tile cell
b. Multi heighten cell
c. LVT cell
d. HVT cell

74) CRPR stands for ___.

a. Cell Convergence Pessimism Removal

b. Cell Convergence Preset Removal
c. Clock Convergence Pessimism Removal
d. Clock Convergence Preset Removal

75) In OCV timing check, for setup time, ___.

a. Max delay is used for launch path and Min delay for capture path
b. Min delay is used for launch path and Max delay for capture path
c. Both Max delay is used for launch and Capture path
d. Both Min delay is used for both Capture and Launch paths

76) "Total metal area and (or) perimeter of conducting layer / gate to gate area" is called ___.

a. Utilization
b. Aspect Ratio
c. OCV
d. Antenna Ratio

77) The Solution for Antenna effect is ___.

a. Diode insertion
b. shielding
c. Buffer insertion
d. Double spacing

78) To avoid cross talk, the shielded net is usually connected to ___.

a. VDD
b. VSS
c. Both VDD and VSS
d. Clock

79) If the data is faster than the clock in Reg to Reg path ___ violation may come.

a. Setup
b. Hold
c. Both
d. None

80) Hold violations are preferred to fix ___.

a. before placement
b. After placement
c. Before CTS
d. After CTS

81) Which of the following is not present in SDC ___?

a. Max tran
b. Max cap
c. Max fan-out
d. Max current density

82) Timing sanity check means (with respect to PD) ___.

a. Checking timing of routed design without net delays

b. Checking Timing of placed design with net delays
c. Checking Timing of unplaced design without net delays
d. Checking Timing of routed design with net delays

83) Which of the following is having highest priority at final stage (post routed) of the design ___?

a. Setup violation
b. Hold violation
c. Skew
d. None

84) Which of the following is best suited for CTS?

a. CLKBUF
b. BUF
c. INV
d. CLKINV

85) Max voltage drop will be there at (without macros) ___.

a. Left and Right sides

b. Bottom and Top sides
c. Middle
d. None

86) Which of the following is preferred while placing macros ___?

a. Macros placed centre of the die

b. Macros placed left and right side of die
c. Macros placed bottom and top sides of die
d. Macros placed based on connectivity of the I/O

87) Routing congestion can be avoided by ___.

a. placing cells closer

b. placing cells at corners
c. Distributing cells
d. None

88) Pitch of the wire is ___.

a. Min width
b. Min spacing
c. Min width - min spacing
d. Min width + min spacing

89) In Physical Design following step is not there ___.

a. Floorplaning
b. Placement
c. Design Synthesis
d. CTS

90) In technology file if 7 metals are there then which metals you will use for power?

a. Metal1 and metal2

b. Metal3 and metal4
c. Metal5 and metal6
d. Metal6 and metal7

91) If metal6 and metal7 are used for the power in 7 metal layer process design then which metals you
will use for clock?

a. Metal1 and metal2

b. Metal3 and metal4
c. Metal4 and metal5
d. Metal6 and metal7

92) In a reg to reg timing path Tclocktoq delay is 0.5ns andTCombo delay is 5ns and Tsetup is 0.5ns then
the clock period should be ___.

a. 1ns
b. 3ns
c. 5ns
d. 6ns

93) Difference between Clock buff/inverters and normal buff/inverters is __.

a. Clock buff/inverters are faster than normal buff/inverters

b. Clock buff/inverters are slower than normal buff/inverters
c. Clock buff/inverters are having equal rise and fall times with high drive strengths compare to normal
buff/inverters.
d. Normal buff/inverters are having equal rise and fall times with high drive strengths compare to Clock
buff/inverters.

94) Which configuration is more preferred during floor planning?

a. Double back with flipped rows

b. Double back with non-flipped rows
c. With channel spacing between rows and no double back
d. With channel spacing between rows and double back

95) What is the effect of high drive strength buffer when added in long net?

a. Delay on the net increases

b. Capacitance on the net increases
c. Delay on the net decreases
d. Resistance on the net increases.

96) Delay of a cell depends on which factors?

a. Output transition and input load

b. Input transition and Output load
c. Input transition and Output transition
d. Input load and Output Load.

97) After the final routing the violations in the design ___.
a. There can be no setup, no hold violations
b. There can be only setup violation but no hold
c. There can be only hold violation not Setup violation
d. There can be both violations.

98) Utilisation of the chip after placement optimisation will be ___.

a. Constant
b. Decrease
c. Increase
d. None of the above

99) What is routing congestion in the design?

a. Ratio of required routing tracks to available routing tracks

b. Ratio of available routing tracks to required routing tracks
c. Depends on the routing layers available
d. None of the above

100) what are preroutes in your design?

a. Power routing
b. Signal routing
c. Power and Signal routing
d. None of the above.

101) Clock tree doesn't contain following cell ___.

a. Clock buffer
b. Clock Inverter
c. AOI cell
d. None of the above