Intro To Electronics P5 PDF

Introduction to Electronics
Digital Electronics
Part - V
Mrinal K Mandal
mkmandal@ece.iitkgp.ernet.in
Department of E & ECE
I.I.T. Kharagpur. 721302.
www.ecdept.iitkgp.ernet.in
1
Introduction to Digital Electronics
Signal is represented by discrete bands.
An industrial digital
controller.
Intel core i9.

Internal circuitry of a mobile phone.
2
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Introduction to Digital Electronics
Signal is represented by discrete bands.
Advantages:
Digital signal can be transmitted without degradation due to noise.
More precise representation of a digital signal: use more binary digits, requires
more digital circuits. An analog system requires fundamental improvements in the
linearity and noise characteristics of each step of the signal chain.
Computer-controlled digital systems can be controlled by software, allowing new
functions to be added without changing hardware.
Information storage can be easier in digital systems than in analog (provided total
noise is below a certain level).
Error correction.
Disadvantages:
Usually, use more energy to accomplish the same tasks.
High frequency limitation: cellular telephones still use a low-power analog front-
end. Digital circuits are sometimes more expensive, especially in small quantities.
Quantization error.
In some schemes, a single bit error can damage a large amount of data. 3
Introduction to Binary Logic
AND: x AND y x.y (output is true only if all of the inputs are true).
OR: x OR y x+y (output is true if any of the inputs is true).
NOT: x not or sometimes y (the output is opposite of that of the input).
AND OR NOT
x y x.y x y x.y y y'
0 0 0 0 0 0 0 1
0 1 0 0 1 1 1 0
1 0 0 1 0 1
1 1 1 1 1 1
x x
z = x.y z = x+y y z = y
y y
Symbols for digital logic circuits.
Multiple input gates: z = A.B.C.D

4
Binary Logic
NAND NOR X-OR X-NOR
x y (x.y) x y (x+y) x y x y
0 0 1 0 0 1 0 0 0 0 0 1
0 1 1 0 1 0 0 1 1 0 1 0
1 0 1 1 0 0 1 0 1 1 0 0
1 1 0 1 1 0 1 1 0 1 1 1
x x
z = (x.y) z = (x+y)
y y
NAND. NOR.
y z=y
x x Buffer.
z = xy+xy z = xy+xy
y y
X-NOR.
X-OR.
Symbols for digital logic circuits. 5
Binary Logic Implementation
x
x y
+ Lamp + y Lamp
- -
Realization of two input Realization of two input OR

AND using switches. using switches.
Switches can be realized by diode and transistor DTL logic gates.

by transistors TTL logic gates.
Some important parameters: fan-out, power dissipation, propagation delay,
noise margin.
IC family Voltage supply High level Low level
Range Typical Range Typical
TTL VCC = 5 V 2.4-5 3.5 0-0.4 0.2

CMOS VDD = 3-10 V VDD VDD 0-0.5 0 6
Binary Logic Implementation (NMOS)
VDD
iD
VDD = 5 V D + 4
vDSL Load
G
RD +v S vO (V) 2
iD GSL
- - vO
G D vO D
+
vI G 0
S vI vDSD Driver
+ S 0 1 5
vGSD -
-
VI (V)
NMOS inverter. Inverter with an NMOS as a load. Transfer characteristics.
VDD = 5 V
VDD = 5 V IR
RD
IR
RD VO
v1 M1
VO
v1 M1 v 2 M2
v2 M2
Two input NOR gate. Two input NAND gate.

7
Boolean Algebra
Introduced by George Boole in 1854.
Two elements: 0, 1.
Two binary operators: +, . (no subtraction or division)
A new operator: complement.
Basic theorems and postulates:

x +1 1 = x .1 x
x +0 x = x .0 0
x +x x = x .x x
x +x' 1 =x .x ' 0
( x ') ' x= x .y y .x ( commutative )
x +y =y +x x .( x + y ) = x + x .y ( distributive )
DeMorgans theorem:
1. ( x +=
y ) ' x '.y ' NOR
2. ( x .y ) ' =
x '+ y ' NAND
8
Boolean Algebra
Using truth tables, prove that Solutions: x y (x+y) xy
1. ( x + y ) ' =
x ' y '.
0 0 1 1
2. x ' y + x = x + y .
0 1 0 0
1 0 0 0
1 1 0 0
Venn diagram:
Circles are drawn inside a rectangle. One for each variable.
The value of the variable is 1 inside the corresponding circle, and 0 outside.
AND: intersection, OR: union.
x y x y
x y
xy
z z
xy + x = x x(y + z) xy + xz
9
Boolean Algebra
Realization of a function using logic gates:
1. ( x + y ' ) ( x y + x ' ) x
x y + x 'y ' y
z
x
z = xy+xy
y
Implementation using X-NOR gate. Implementation using AND, OR and NOT gates.
Simplify the following functions: x y + x ' z + yz

Solutions: x y + x ' z + yz
= x y + x ' z + yz ( x + x ' )
= x y + x ' z + xyz + x ' yz
= xy (1 + z ) + x ' z (1 + y )
= xy + x ' z
10
Minterms and Maxterms
Minterms Maxterms
x y z Term Design x y z Term Design
ation ation
0 0 0 xyz m0 0 0 0 x+y+z M0
0 0 1 xyz m1 0 0 1 x+y+z M1
0 1 0 xyz m2 0 1 0 x+y+z M2
0 1 1 xyz m3 0 1 1 x+y+z M3
1 0 0 xyz m4 1 0 0 x'+y+z M4
1 0 1 xyz m5 1 0 1 x'+y+z M5
1 1 0 xyz m6 1 1 0 x'+y+z M6
1 1 1 xyz m7 1 1 1 x'+y+z M7
Take the minterms for which the function Take the maxterms for which the function
is 1. is 0.
An n variable binary number will have 2n minterms/maxterms.

Any Boolean function can be expressed by the OR operation of all the minterms.
Any Boolean function can be expressed by the AND operation of all the
maxterms. 11
Truth table for two functions f1 and f2
x y z f1 f2 Representation in terms of minterms:
0 0 0 0 0
0 0 1 1 0
f 1 = x ' y ' z + x ' yz '+ x ' yz = (1, 2, 3 )
0 1 0 1 0
f 2 = x ' yz + xy ' z + xyz '+ xyz = ( 3, 5, 6, 7 )
0 1 1 1 1
1 0 0 0 0
1 0 1 0 1
1 1 0 0 1
1 1 1 0 1
Representation in terms of maxterms:

f 1 = ( x + y + z )( x '+ y + z )( x '+ y + z ' )( x '+ y '+ z )( x '+ y '+ z ' ) = ( 0, 4, 5, 6, 7 )
f 2 = ( x + y + z )( x + y + z ' )( x + y '+ z )( x '+ y + z ) = ( 0, 1, 2, 4 )
12
Express the Boolean function F = A+BC in a sum of minterms form.
Solutions:
Consider each term individually.
If x is the missing variable, multiply the term by (x+x)
A = A (B + B ' ) = AB + AB '
A= ( AB + AB ' )(C + C ' )
= ABC + ABC '+ AB 'C + AB 'C '
B 'C B 'C ( A + A ' )
=
= AB 'C + A ' B 'C
= F A ' B 'C + AB 'C '+ AB 'C + ABC '+ ABC
Express the Boolean function F = xy + xy + yz in a sum of minterms form.

Solutions:
F = xyz + xyz '+ x ' yz + x ' y ' z + x ' y ' z '
13
Express the Boolean function F = AB+AC in a product of maxterms form.
Solutions:
Use the distributive law: x + yz = (x+y)(x+z).
For any missing variable x, ORed with xx and again use the distributive
law.
( AB + A ' )( AB + C )
AB + A 'C =
= ( A + A ' )(B + A ' )( A + C )(B + C )
= ( A '+ B )( A + C )(B + C )
( A '+ B ) = ( A '+ B ) + CC ' = ( A '+ B + C )( A '+ B + C ' )
( A + C ) = ( A + C ) + BB ' = ( A + B + C )( A + B '+ C )
(B + C ) = (B + C ) + AA ' = ( A + B + C )( A '+ B + C )
F = ( A + B + C )( A + B '+ C )( A '+ B + C )( A '+ B + C ' )
Express the Boolean function F = xy + xy + yz in a product of maxterms form.

Solutions:
F = ( x + y '+ z )( x '+ y + z )( x '+ y + z ' )
14
Simplification of Boolean Functions
A straight forward method is by using Karnaugh map or Veitch diagram.
Representation of a
Two variable K-map using the minterms
function F = xy+xy
x y 0 1 x y 0 1 x y 0 1
0 m0 m1 0 xy xy 0 0 1
1 m2 m3 1 xy' xy 1 1 0
Three variable K-map using Representation of a function

the minterms F = xyz+xyz+xyz
yz 00 yz 00 01 11 10
x 01 11 10 x
0 xyz xyz xyz xyz 0 0 0 1 0
1 xyz xyz xyz xyz 1 0 1 1 0
A n variable K-map consist of 2n squares.

The minterms are not in binary sequence, only one bit changes in the listing
sequence.
15
Simplify the function F = xyz+xyz+xyz+xyz.
yz 00 01 11 10
x
0 1 1 xy F = xy+xy
1 1 1
xy
Sum of product simplification steps:
The squares representing the minterms mark as 1.
Subdivide the area: put 2n adjacent cells containing 1 into groups, try to
maximize the number of cells in a group. A single 1 can be a common element
to multiple groups.
While grouping into squares, consider that the opposite sides and opposite
corners of a K-map are joined together i.e. as if any K-map is drawn on a
spherical surface.
A square containing 1 provides only one term: discard the variable/variables
which changes bit within a group, the remaining variables will provide the
16
term.
Simplify the function F = xyz+xyz+xyz+xyz.
yz 00 01 11 10
x
0 1 yz F = xz+yz
1 1 1 1 xz
Four variable K-map using the minterms Representation of a function

F = wxy+xyz+wxyz+wxy
yz 00 01 11 10 yz
wx wx 00 01 11 10
00 wxyz wxyz w'xyz w'xyz 00 1 1 1
01 w'xyz w'xyz w'xyz w'xyz 01 1
11 wxyz wxyz wxyz wxyz' 11
10 wxyz wxyz wxyz wxyz 10 1 1 1
F = xy + xz + wyz.
17
Simplify the following Boolean functions:
1. F 1 = ( 0, 4, 6, 7, 8, 14, 15 )
2. F =
2 w ' x ' y ' z '+ w ' x ' yz '+ wx ' yz '+ wx ' y ' z '+ w ' xy ' z + w ' xyz + wxy ' z + wxyz
1. Representation of the function F1 2. Representation of the function F2.
yz yz 00 01 11 10
wx 00 01 11 10 wx
00 1 00 1 1
01 1 1 1 01 1 1
11 1 1 11 1 1
10 1 10 1 1
F = xy + wyz + xyz. F = xz + xz.
18
Product of sum simplification:
Simplify the following Boolean functions:1. F 1 = ( 0, 4, 6, 7, 8, 14, 15 )
2. F 2 = ( 0, 2, 5, 7, 8, 10, 13, 15 )
1. Representation of the function F1 2. Representation of the function F2.
yz yz 00 01 11 10
wx 00 01 11 10 wx
00 1 0 0 0 00 1 0 0 1
01 1 0 1 1 01 0 1 1 0
11 0 0 1 1 11 0 1 1 0
10 1 0 0 0 10 1 0 0 1
F = (y+z)(w+x+y)(x+y). F = (x+z)(x+z).
19
Dont care condition:
In some applications, certain combinations of input variables never occur.
The function value cannot be taken as 1 or 0 for those input combinations, they
are represented by X and called the dont care condition.
When choosing adjacent squares for simplification, the Xs may be assumed as
0 or 1 or just ignore them, whichever gives the simplest expression.
Simplify the function F 1

= ( 0, 4, 6, 7, 8, 14, 15 ) with d ( 2, 3, 12 )
1. Representation of a function F1
yz 00 01 11 10
wx
Simplify the following function:
00 1 X X
=F2
= (1, 3, 7, 11, 15 ) with d ( 0, 2, 5 )
01 1 1 1
11 X 1 1 Solution: F2 = wz + yz
10 1
F = yz + xy
20
Dont care condition:
Simplify the functions and express them in product of sum form
1. F 1
= ( 0, 4, 6, 7, 8, 14, 15 ) with d ( 2, 3, 12 )
2. F 2 = (1, 3, 7, 11, 15 ) with d ( 0, 2, 5 )
1. Representation of a function F1 Solution: F 2 = z(w + y)

yz 00 01 11 10
wx
00 1 0 X X
01 1 0 1 1
11 X 0 1 1
10 1 0 0 0
F = (y+z)(x+y)
21
NAND and NOR Implementation
F = ( xyz ) ' = x ' + y ' + z ' F = (x + y + z )' = x ' y 'z '
x x
y (x.y.z) y (x+y+z) x x'
z z
NAND (AND-invert). NOR (OR-invert). NOT (Buffer-invert).
x x
y x.y.z x x
y x'+y+z
z z
AND-invert.
Invert-OR. Invert-AND.
x x
OR-invert.
22
NAND Gate as Universal Gate
F = x + y = ( x ' ) '+ ( y ' ) ' = ( x ' y ' ) '
x x+y
x
x'y
x+y
y
y
OR gate. NOR gate.
F xy
= = ( ( xy ) ' ) '
x
x.y
y
AND gate.
x x+y
X-NOR: use one more
xy+xy
NAND gate.
x+y
y x+y
X-OR gate. 23
NOR Gate as Universal Gate
x
x+y
y x
OR gate. (xy)
y
x NAND gate.
xy
y
AND gate.
xy+xy
X-OR: use one more
xy NAND gate.
y
X-NOR gate.
24
NAND Implementation
1. Steps:
Represent the simplified function in sum of product form.
Use two inverters in between the AND and OR gate.
Convert invert-OR to NAND.
Simplify the function F = AB + CD + E
A A A
B B B
C C C
F F F
D D D
E E E
25
NAND Implementation
2. Steps:
Represent the simplified function in sum of product form and implement using
the AND, OR and NOT gates.
Replace all AND, OR and NOT gates by their equivalent NAND representation.
Remove cascaded inverter if any.
x
x
x.y x+y
y
y
AND
OR
Implement the function F = AB + CD + E
A
A B
B
C
C D
F F
D
E
E 26
Combinational Logic
Logic circuits:
1. Combinational circuit: at any time, the outputs are determined directly from the
present inputs.
2. Sequential circuit: the outputs depend not only on present inputs, but also on
past inputs (memory). Circuit behavior must be specified by a time sequence of
inputs and internal states.
Implementation using combinational circuits:

1. Determination of the number of inputs and outputs is required.
2. Obtain the truth table/ their relationship and from that represent them in a
function form.
3. Simplify the function.
4. Implement by using AND, OR and NOT gates.
5. Depending on availability, convert to NAND/ NOR logic.
6. For multiple functions, if possible, try to express an output in terms of other
outputs.
27
Combinational Logic Adders
Adders:
The basic arithmetic operation.
Half-adder: perform addition of two bits.
Full-adder: perform addition of two bits and also take care of a previous carry if
any.
Half-adder:
The sum (S) and carry (C) bits can be express as
Truth table
follows:
x y C S S = x ' y + xy ' = x y =( x + y ) ( x '+ y ')
C = xy
0 0 0 0
x x
0 1 0 1 S
y y'
1 0 0 1 S
x'
1 1 1 0 C
y
Half-adder NAND gate implementation

implementation. of the sum bit.
28
Full-adder:
Carry 1
x and y are the inputs and z denotes the LSB of previous carry.
Augend 57
Addend 47
Sum 104
Truth table Solve for sum bit.
x y z C S yz
x 00 01 11 10
0 0 0 0 0 0 1 1
S = x ' y ' z + x ' yz '+
0 0 1 0 1 1 1 1 xy ' z '+ xyz .
0 1 0 0 1
0 1 1 1 0 Solve for carry bit.
1 0 0 0 1 yz
x 00 01 11 10
1 0 1 1 0
0 1
1 1 0 1 0
1 1 1 1 1
1 1 1 1 C = xy + yz + zx
29
Full-adder implementation:
x
S =z ( x y ) y S
= z ' ( xy '+ x ' y ) + z ( xy '+ x ' y ) '
= z ' ( xy '+ x ' y ) + z ( xy + x ' y ' )
C
= xy ' z '+ x ' yz '+ xyz + x ' y ' z
z
C= z ( x ' y + xy ' ) + xy= xy ' z + x ' yz + xy
Full-adder implementation.
Binary parallel adder:

Add two binary numbers of n bits.
An n bit parallel adder requires n number of full adders.
Starting from the LSB, connect the inputs and the carry sequentially.
Serial adder can be designed by using a single full adder and memory
elements.
30
Combinational Logic
Example:
Subscript i 4321 B4 A4 B3 A3 B2 A2 B1 A1
Input carry 0110 Ci
Augend 1011 Ai C5 C4 C3 C2 C1
FA FA FA FA
Addend 0011 Bi
Sum 1110 Si S4 S3 S2 S1
Output carry 0011 Ci+1
A four bit parallel adder.
Carry propagation:
Each gate takes finite time to respond: propagation delay t.
The (n+1)th carry is available only after n t (one solution is look-ahead carry).
Subtractors:
Subtraction can be accomplished by taking the complement of the subtrahend and
adding it to the minuend.
Here, it will be implement directly.
Half-subtractor: perform subtraction of two bits.
Full-subtractor: perform subtraction of two bits and also take care of a previous
borrow if any. 31
Combinational Logic
Half-subtractor: Truth table
x y B D
x<y : borrow a 1 from the next higher state.
D =x ' y + xy ' =S 0 0 0 0
B = x 'y 0 1 1 1
1 0 0 1
1 1 0 0
x
D
y
Half-adder
implementation.
32
Combinational Logic
Full-subtractor:
x: minuend, y: subtrahend, and z: previous borrow.
Truth table
(x y = D)
x y z B D
Solve for difference bit.
0 0 0 0 0 yz
x 00 01 11 10
0 0 1 1 1
0 1 1
0 1 0 1 1 D = x ' y ' z + x ' yz '+
0 1 1 1 0
1 1 1 xy ' z '+ xyz .
1 0 0 0 1
Solve for borrow bit.
1 0 1 0 0
yz
x 00 01 11 10
1 1 0 0 0
1 1 1 1 1 0 1 1 1
1 1 C = x ' y + yz + x ' z
Q. Implement the full-subtractor by two input NAND gates only.

33
Excess-3 Code
Code converter:
Input Output
Code BCD Excess-3 code
BCD Excess-3
converter
A B C D w x y z
Remaining six binary input combination 0 0 0 0 0 0 1 1

never occur: dont care condition.
0 0 0 1 0 1 0 0
CD 00 01 11 10 0 0 1 0 0 1 0 1
AB
0 0 1 1 0 1 1 0
00 1 1
0 1 0 0 0 1 1 1
01 1 1
0 1 0 1 1 0 0 0
11 X X X X
0 1 1 0 1 0 0 1
10 1 X X
0 1 1 1 1 0 1 0
z = D.
1 0 0 0 1 0 1 1
y CD + C ' D ',
=
1 0 0 1 1 1 0 0
x = B 'C + B ' D + BC ' D ',
w =A + BC + BD .
34
Binary Coded Decimal (BCD)
Binary sum BCD Decimal
Z16 Z8 Z4 Z2 Z1 S16 S8 S4 S2 S1
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 2
0 0 0 1 1 0 0 0 1 1 3
0 0 1 0 0 0 0 1 0 0 4
0 0 1 0 1 0 0 1 0 1 5
0 0 1 1 0 0 0 1 1 0 6
0 0 1 1 1 0 0 1 1 1 7
0 1 0 0 0 0 1 0 0 0 8
0 1 0 0 1 0 1 0 0 1 9
0 1 0 1 0 1 0 0 0 0 10
0 1 0 1 1 1 0 0 0 1 11
0 1 1 0 0 1 0 0 1 0 12
0 1 1 0 1 1 0 0 1 1 13
0 1 1 1 0 1 0 1 0 0 14
0 1 1 1 1 1 0 1 0 1 15
1 0 0 0 0 1 0 1 1 0 16
1 0 0 0 1 1 0 1 1 1 17
1 0 0 1 0 1 1 0 0 0 18
1 0 0 1 1 1 1 0 0 1 19
35
Gray Code and ASCII Code
Decimal Gray code (reflected 7-bit ASCII Charac
code) code ters
Z8 Z4 Z2 Z1
0 0 0 0 0 011 0000 0
1 0 0 0 1 011 0001 1
2 0 0 1 1 011 0010 2
3 0 0 1 0 011 0011 3
4 0 1 1 0 011 0100 4
5 0 1 1 1 011 0101 5
6 0 1 0 1 011 0110 6
7 0 1 0 0 011 0111 7
8 1 1 0 0 011 1000 8
9 1 1 0 1 011 1001 9
10 1 1 1 1 100 0001 A
11 1 1 1 0 100 0010 B
12 1 0 1 0 100 0011 C
13 1 0 1 1 100 0100 D
14 1 0 0 1 010 1000 (
15 1 0 0 0 010 1011 +
36
Combinational Logic
Analysis of a given network:
1. Label the inputs and determine the number of input variables.
2. Obtain the Boolean functions for each gate and continue calculation until the
outputs are obtained.
3. By repeated substitution of previously defined functions, obtain the output in
terms of input variables only.
y yz
1
z (x+yz)
3
x w(x+yz)
w
4
5 6 xy+w(x+yz)
x xy'
2
y
Analysis of the circuit.
37
Combinational Logic
X-OR and equivalence functions: yz
wx 00 01 11 10
x y= x ' y + xy ',
x y = xy + x ' y ' =( x y ) ', 00 1 1
( x y ) z =x ( y z ) =x y z , 01 1 1
(x y z )' = x y z , 11 1 1
(x y = z ) x y z. 10 1 1
w x y z
Very useful in error-detection and error-
correction codes. yz
wx 00 01 11 10
n variable X-OR operation: 2n/2 minterms
have an odd number of 1s. 00 1 1
n variable X-NOR operation: 2n/2 minterms 01 1 1
have an even number of 1s. 11 1 1
10 1 1
w x y z
38
Combinational Logic
Parity Checker: Odd-parity check Received bits Error
in a receiver. check
Parity bit: extra bit included with x y z P C
a binary message to make the 0 0 0 0 1
number of 1s either odd (odd 0 0 0 1 0
parity) or even (even parity).
0 0 1 0 0
Parity generator: generates the Odd-parity
0 0 1 1 1
parity bit in a transmitter. generation
0 1 0 0 0
Odd parity generation: P = 1 if Message Parity 0 1 0 1 1
total number of 1s including P is bit
0 1 1 0 1
odd. x y z P
0 1 1 1 0
Parity checker: check the parity 0 0 0 1
1 0 0 0 0
in a receiver. 0 0 1 0
1 0 0 1 1
0 1 0 0
1 0 1 0 1
P= x y z 0 1 1 1
1 0 1 1 0
= x y z . 1 0 0 0
1 1 0 0 1
1 0 1 1
1 1 0 1 0
C = x y z P. 1 1 0 1
1 1 1 0 0
1 1 1 0 391
1 1 1 1
Combinational Logic
Decoders:
Converts binary information from n input lines to a maximum 2n unique output
lines.
A n-to-m line decoder (m 2n) generates m unique output lines from n input lines.
If m <2n, rest (2n m) can be used as dont care condition.
Design a BCD-to-decimal decoder.

x'y
x yz
x'y wx 00 01 11 10
Decoder
y x'y 00 D0 D1 D3 D2
xy
01 D4 D5 D7 D6
11 X X X X
A 2-to-4 line decoder.
10 D8 D9 X X
= D 0 w ' x ' y= ' z ', D 3 x '=

yz , D 6 xyz
= ', D 9 wz .
10 AND gates and 4 NOT
=
gates are required for D1 w ' x ='y 'z, D 4 xy
= ' z ', D 7 xyz ,
implementation = D 2 x ' yz= ', D 5 xy
= 'z, D 8 wz ',
40
Combinational Logic
Implement a full-adder circuit with a decoder and OR gates.
Solutions:
S ( x , y , z ) = (1,2,4,7 )
C ( x , y , z ) = ( 3,5,6,7 ).
0
1
x 22 2 S
y 21 3
z 20 4
5 C
3x8 6
decoder
7
Full-adder with a decoder.
41
Combinational Logic
Demultiplexers:
A demultiplexer receives information on a single line and transmits on one of 2n
possible output lines.
A decoder with an enable input.
Enable input: take AND operation with all outputs.
D0 (xyE)
D0
D1 (xyE) x
x 2x4 D1
select
y Decoder D2
D2 (xyE) D3
y
E
D3 (xyE)
E A 2-to-4 decoder with enable
input.
Implementation of a demultiplexer with
NAND gates. 42
Combinational Logic
Design a 4x16 demultiplexer using 3x8 demultiplexers.
Solution:
.
x
3x8 . D0 to D7
y decoder .
z
x .
3x8 . D8 to D15
y decoder .
z
4x16 demultiplexer constructed

with two 3x8 demultiplexer.
43
Combinational Logic
Encoder:
Reverse operation from that of a decoder.

m x n encoder: 2n or less (m) input lines and n output lines.
Octal to binary encoder.
Inputs Outputs
D0
D0 D1 D2 D3 D4 D5 D6 D7 x y z D1 x= D4+D5+D6+D7
1 0 0 0 0 0 0 0 0 0 0 D2
0 1 0 0 0 0 0 0 0 0 1 D3
0 0 1 0 0 0 0 0 0 1 0 D4 y= D2+D3+D6+D7
0 0 0 1 0 0 0 0 0 1 1 D5
0 0 0 0 1 0 0 0 1 0 0 D6
0 0 0 0 0 1 0 0 1 0 1 D7 z= D1+D3+D5+D7
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1 Octal-to-binary encoder.
44
Combinational Logic
Multiplexers:
Selects binary information from one of many input lines and directs it to a single
output line.
Usually, 2n input lines, n selection lines and one output line.
I0
E
I1
I2 0
1 4x1
inputs MUX output
I3 2
3
s1 s0
select
s1
s0
A 4-to-1 line multiplexer.
A 4-to-1 line multiplexer. 45
Combinational Logic
Implementation of a function using MUX:
1. Implement the following function using MUX: F = ( 0,3,5,7 ).

Implementation table.
I0 I1 I2 I3 A 0
A 1 4x1 F
A 0 1 2 3 MUX
0 2
A 4 5 6 7
1 3
A A 0 1 s1 s0
B C
2. Implement the following function using MUX: F = (1,3,5,6 ).
0 0
I0 I1 I2 I3
1 1 4x1 F
A 0 1 2 3 MUX
A 2
A 4 5 6 7
A 3
s1 s0
0 1 A A
B C 46
Combinational Logic
Implementation of a function using 8x1 MUX:
1. Implement the following function using MUX: F = ( 0,1,3,4,8,9,15 ).

I0 I1 I2 I3 I4 I5 I6 I7
E=1
A 0 1 2 3 4 5 6 7
A 8 9 10 11 12 13 14 15 1 0
1 1 0 A A 0 0 A 1 1
0 2
A 3
8x1 F
A 4
MUX
0 5
0 6
A 7
s2 s1 s0
B C D
47
Combinational Logic
8x1 MUX:
S2 E=1
0
0
1 4x1
MUX 1
2
2
3
s1 s0 3
8x1 F
4
MUX
S2 5
6
0
4x1 7
1
MUX s2 s1 s0
2
3 B C D
s1 s0
select
A 8-to-1 line multiplexer from 4-to-1 line.

48
Combinational Logic
Read Only Memory (ROM):
Programmable memory device that includes both the decoder and OR gates.
IC package, eliminate all interconnecting wires.
Internal links can be fused or broken.
Each bit combination of the input variables (n) is called an address.
Each bit combination that comes out as outputs are called word (2n).
Number of bits per word = m, then the ROM is called a 2n x m ROM.
A0
A1 0
5x32 1
A2 decoder
A3
A4 31
Address 128 links

input
F1 F2 F3 F4
Logic construction of a 32x4 ROM.
49
Combinational Logic
Programmable Logic Array (PLA):
In a ROM, dont care conditions become address inputs that will never occur.
A PLA consist of a group of AND gates and OR gates.
Each of the AND gate can be programmed to generate a product term.
Implement the following functions by using a 3x3x2 (number of input x number of

product term x number of output) PLA.
F1 AB '+ AC
=
F2 AC + BC .
= A
F1
B
F2
C
Implementation of the functions with PLA.

50
Combinational Logic
nxk m
links links
k product m sum
terms terms
n nxk (AND gates) kxm (OR gates) m
inputs links links outputs
PLA block diagram.
Calculate the total number of links of a 16 x 48 x 8 PLA.

Solution:
Number of links = 2n x k + k x m + m
= 1928.
Number of links for a similar size ROM = 2n x m

= 524288.
51
Sequential Logic
Inputs Outputs
Combinational
circuit Memory
elements
Block diagram of a sequential circuit.
As shown, the outputs depend not only on the external inputs but also on the
present state of the memory element.
Depending on the timing of the signal, they are of two types:
1. Synchronous sequential circuit: behavior is defined only at discrete instant of
time. Synchronization is achieved by a master clock generator that generates
periodic pulses.
2. Asynchronous sequential circuit: can be affected at any instant of time. Usually,
time delay devices are used as a memory device.
52
Sequential Logic
RS/ SR latch: NOR gate: output is zero if any input is 1.
NAND gate: output is 1 if any input is 0.
1 1
R S
0 1 Q 0 1 Q
Q Q Q Q
1 1 2 R S
2 Q R S Q
S R
0 0
SR latch with NOR gates. SR latch with NAND gates.
S R Q Q S R Q Q
1 0 1 0 1 0 0 1
0 0 1 0 After S = 1, R = 0. 1 1 0 1 After S = 1, R = 0.
0 1 0 1 0 1 1 0
0 0 0 1 After S = 0, R = 1. 1 1 1 0 After S = 0, R = 1.
1 1 0 0 Not allowed. 0 0 1 1 Not allowed.
53
Sequential Logic
RS Flip-Flop: The basic RS latch with AND gates respond to input levels when the
clock pulse is 1: synchronous sequential circuit.
R
1 Q Characteristic table.
CP Q S R Q (t+1)
2 Q 0 0 0 0
S 0 0 1 0 Reset
0 1 0 1 Set
Clocked RS Flip-Flop.
0 1 1 NA
SR 1 0 0 1
Q 00 01 11 10 1 0 1 0 Reset
Q Q
0 X 1 1 1 0 1 Set
R S 1 1 X 1 1 1 1 NA
CP Q (t + 1) = S + R 'Q .
Graphical symbol. 54
Sequential Logic
D Flip-Flop: D flip-flop is used to transfer the data.
R
D Characteristic table.
1 Q Q D Q (t+1)
CP 0 0 0
0 1 1
2 Q
1 0 0
S 1 1 1
A gated D Flip-Flop based on RS latch.
D
Q 0 1
Q Q 0 1
D 1 1
Q (t + 1) =
D.
CP
Graphical symbol. 55
Sequential Logic
JK Flip-Flop: A refinement of the RS flip-flop by Characteristic table.
interpreting the S = R = 1 condition as a flip or toggle.
Q J K Q (t+1)
One problem is that the output for J = 1, K = 1
continue to toggle if the clock pulse is ON for long time. 0 0 0 0
0 0 1 0
0 1 0 1 Set
K 0 1 1 1
1 Q
(reset)
1 0 0 1
Q Q CP
1 0 1 0 Reset
K J 2 Q 1 1 0 1
J
(set) 1 1 1 0
CP
A gated JK flip-flop based on RS latch. JK
Q 00 01 11 10
T flip-flop: 0 1 1
Let K is the only input represented by T and it is 1 1
1
also connected to J terminal.
Then Q changes state for T =1 and remain as it Q (t + 1) = JQ '+ K 'Q .
is for T = 0. 56
Sequential Logic
Triggering of flip-flop:
1
The state of a flip-flop is switched by a momentary
change in input signal: triggering. 0
For proper operation, a specific relationship must be Positive Negative
maintained between the time interval between two edge edge
changes of input values and the propagation delay.
For synchronous circuit, propagation delay must be more Positive pulse
than the pulse width.
The above problem can be solved by choosing a circuit 1
that respond only to positive or negative transition /edges
e.g. by using capacitor coupling. 0
A master-slave flip-flop can avoid this problem.
Negative Positive
edge edge
Negative pulse
57
Sequential Logic
Master Slave flip-flop:
CP
Master Slave
S y
S S Q S
R y' y
R R Q
CP Q
Start with
reset state
Master-slave flip-flop. Timing relationship.
CP = 0: slave is enabled, Q = y, Q = y (only 0,1 or 1,0 are possible for the y, y,

respectively).
CP = 1: master is enabled. External R and S are transmitted to the master flip-
flop.
Therefore, at the positive edge of the clock pulse triggers the master, while the
negative edge triggers the slave: whole cycle occurs in one period of the pulse.
58
Questions
1. Implement OR and X-OR gates using minimum number of NMOS.
2. Design a combinational circuit that generates the 9s complement of a BCD digit.
3. Implement the following function by using minimum number of two-input NAND
gates. F = A(B+CD)+BC
4. Design a full-adder using minimum number of two-input NOR gates.
5. Design a full-subtractor using minimum number of 41 MUX.
6. Implement the following functions by using a 38 decoder and additional logic
=
gates if necessary. F
= ( 0,1,3) , F (1, 2,3) .
1 2
7. Design a BCD-to-decimal decoder that provides an output of all 0s when any

invalid input combination occurs.
8. Obtain the characteristics table of a JK flip-flop (it is a JK flip-flop with an
inverter between external input K and internal input K).
9. The carry input z of a full-adder comes from a D flip-flop. Output of the full-adder
S provides the sum of the three inputs. The carry is connected to input of the
flip-flop. Obtain the characteristic table of the sequential circuit.
59
Thank you
?
mkmandal@ece.iitkgp.ernet.in
Ph. +91-3222-283550 (o)
Department of E. & E.C.E.
I.I.T. Kharagpur, 721302.
60

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Introduction to Electronics

Intel core i9.

Symbols for digital logic circuits.

Multiple input gates: z = A.B.C.D

Realization of two input Realization of two input OR

Switches can be realized by diode and transistor DTL logic gates.

IC family Voltage supply High level Low level

Range Typical Range Typical

TTL VCC = 5 V 2.4-5 3.5 0-0.4 0.2

Two input NOR gate. Two input NAND gate.

Basic theorems and postulates:

Simplify the following functions: x y + x ' z + yz

An n variable binary number will have 2n minterms/maxterms.

Representation in terms of maxterms:

= F A ' B 'C + AB 'C '+ AB 'C + ABC '+ ABC

Express the Boolean function F = xy + xy + yz in a sum of minterms form.

Express the Boolean function F = xy + xy + yz in a product of maxterms form.

Three variable K-map using Representation of a function

A n variable K-map consist of 2n squares.

Four variable K-map using the minterms Representation of a function

1. Representation of the function F1 2. Representation of the function F2.

F = xy + wyz + xyz. F = xz + xz.

1. Representation of the function F1 2. Representation of the function F2.

Simplify the function F 1

1. Representation of a function F1 Solution: F 2 = z(w + y)

NAND (AND-invert). NOR (OR-invert). NOT (Buffer-invert).

OR gate. NOR gate.

Simplify the function F = AB + CD + E

Implementation using combinational circuits:

Half-adder NAND gate implementation

Binary parallel adder:

Q. Implement the full-subtractor by two input NAND gates only.

Remaining six binary input combination 0 0 0 0 0 0 1 1

Analysis of the circuit.

Design a BCD-to-decimal decoder.

= D 0 w ' x ' y= ' z ', D 3 x '=

Full-adder with a decoder.

4x16 demultiplexer constructed

Reverse operation from that of a decoder.

Octal to binary encoder.

1. Implement the following function using MUX: F = ( 0,3,5,7 ).

1. Implement the following function using MUX: F = ( 0,1,3,4,8,9,15 ).

A 8-to-1 line multiplexer from 4-to-1 line.

Address 128 links

Implement the following functions by using a 3x3x2 (number of input x number of

Implementation of the functions with PLA.

PLA block diagram.

Calculate the total number of links of a 16 x 48 x 8 PLA.

Number of links for a similar size ROM = 2n x m

Block diagram of a sequential circuit.

SR latch with NOR gates. SR latch with NAND gates.

Master-slave flip-flop. Timing relationship.

CP = 0: slave is enabled, Q = y, Q = y (only 0,1 or 1,0 are possible for the y, y,

7. Design a BCD-to-decimal decoder that provides an output of all 0s when any

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