Experimental Verification of Direct Dead-time

Control and DC-link Neutral-point Balancing of a

Three Level Neutral-point-clamped (3L-NPC) VSC
Michael Sprenger, Tobias Barth, Rodrigo Alvarez, Marvin Tannhaeuser, Steffen Bernet
Technische Universitaet Dresden, Germany
Faculty of Electrical and Computer Engineering
Institute of Electrical Power Engineering
Chair of Power Electronics

AbstractThe neutral-point balancing of 3L-NPC con-
verter has been studied in many works in the past.
However, all state-of-the-art methods have in common that
the information of the energy-flow direction is needed.
Recently, Direct Dead-time Control (DDTC) has been
presented which controls the converter dead-times to
balance the dc-link independent from the energy-flow di-
rection. This paper presents an experimental investigation
of DDTC for different load conditions and control schemes.
I. I NTRODUCTION
Multilevel inverters have become the dominant so-
lution for high power electrical drives [1], [2], [3],
[4]. Moreover, the three-phase, three-level neutral-point-
clamped voltage-source converter (3L-NPC VSC) is one
of the most used converters for medium voltage drives
[3], [2], [1], [5]. This topology has been successfully
transferred to low voltage high power applications [6],
becoming a serious competitor of the well established
two-level voltage-source converter (2L VSC). The 3L-
NPC VSC features following advantages:
lower switching and total losses for fs 3 . . . 5 kHz
[3], [2],
lower harmonics and improved THD and WTHD
[3], [2],
lower expense of filters to meet standards and grid
requirements [3], [2],
higher maximum switching frequency at given in-
stalled switch power [3], [2],
reduced insulation stress due to halved voltage step
magnitudes [3], [2].
One of the challenges of the 3L-NPC VSC is the
balancing of the split dc-link. The reasons for the dc-link
imbalance are diverse e.g. differences in IGBT switching
behavior, different timing of the gate-signals, dead times,
asymmetrical loads, tolerances of the capacitors, etc.
There are several methods to balance the neutral-point of
the dc-link [7], [8], [9], [10]. These methods mainly de-
pend on the modulation scheme and require the detection
of the energy-flow direction. A new balancing method for
three-phase 3L-NPC VSC, which is independent from
the energy-flow direction and the applied modulation
scheme, was presented in [5]. This method only needs
the capacitor voltages to balance the split dc-link of the
3L-NPC VSC.
This paper presents a summary of DDTC for the bal-
ancing of the split dc-link of 3L-NPC VSC. Moreover, it
presents a 600 V, 3 kW test bench for the experimentally
verification of the method and experimentally studies
the performance of the proposed method for diverse
implementations on a low cost FPGA.
II. BASICS OF DDTC
DDTC uses the semiconductor dead-times influence
on the neutral-point voltage to control its deviations
[5]. The method models the neutral-point voltage as a
function of the neutral-point current. Assuming equal
capacitances in the upper and lower part of the dc-link,
 
dvC1 dvC2
iM = C (1)
dt dt
 
dvM
iM = C , (2)
dt
follows where vM is the neutral-point voltage. To de-
scribe iM , a single phase of the 3L-NPC VSC and its
switching-states (qx = [1, 0, 1]) are examined as shown
in Fig. 1 . The neutral-point-current for one phase-leg can
be described by
iM x0 = Ix (1 |qx |) (3)

978-1-4799-0336-8/13/$31.00 2013 IEEE 409

 T1 D1 T1 D1 T1 D1
Minimal
VDC1 VDC1 VDC1 VDC1 Dead Time
V
D5 T2 D2 D5 T2 D2
Limit
D5 T2 D2
Ia Ia Ia M -1 TD13 TD1 , TD3
M A M A M A

D6 T3 D3 D6 T3 D3 D6 T3 D3 VDC2 V Controller
- Limit
VDC2 VDC2 VDC2
TD24 TD2 , TD4
T4 D4 T4 D4 T4 D4

Figure 2. Block diagram of control structure for Direct Dead-Time

Positive state Neutral state Negative state Control
(q=1) (q=0) (q=-1)
Figure 1. Switching-states of one phase-leg of a 3L-NPC
measured values FPGA
dSpace processing of measurements
current-control DDTC
phase-voltages modulation
with x = a, b, c.
Differences in dead-times cause a neutral-point im- switching signals

balance. E.g. when carrying positive phase-current and measured values

switching from the neutral to the positive state, see
Fig. 1. Turning off T3 does not affect the current path
because the current changes only after T1 turns on after
the dead-time TD1 . This means that a positive phase-
current flows through the neutral-point for a longer time
than without the dead-time TD1 . This charges the capac-
itances and therefore changes the neutral-point voltage.
Summarizing, the dead-times for T1 and T3, TD13 ,
cause a positive offset-current iM x,of f independent from
the phase-current direction and therefore increase the
neutral-point voltage. The dead-times for T2 and T4,
TD24 , cause a negative offset-current iM x,of f indepen-
dent from the phase-current direction and decrease the
neutral-point voltage. It follows
TD1
TS I x qx > 0, Ix > 0
TD3 I q > 0, I < 0
TS x x x built. Its power-part consists of a 3 kW DC voltage-
iM x,of f = (4)
TS Ix qx < 0, Ix > 0
TD2
TD4 I
qx < 0, Ix < 0
TS x
and
iM x = iM x0 + iM x,of f .
In [5] theese effects are studied in detail.
DDTC adds small offsets to a minimum dead-time
to balance the dc-link voltage. In Fig. 2 the block
diagram of the control structure for DDTC is shown. The
controller (PI, two-position etc.) is fed by the difference
of both capacitor voltages and generates the dead-time
offset. The negative offsets are inverted and added to the
minimum dead-time for T13. The positive offsets are
added to the minimum dead-times for T24.
(currents, voltages,
temperatures)
L R
C 3L-NPC
VSC
VDC
C
Figure 3. Schematic of 3L-NPC VSC test-bench
III. T EST- BENCH
To verify the functionality of DDTC, a test-bench was
source, a three-phase 3L-NPC VSC and an RL-load.
A dSpace system and an FPGA were used to control
the system. The dSpace system calculates the reference
values for the three phase voltages and sends them to the
FPGA via optic fibre. The FPGA generates the switching
(5) signals by carrier based modulation and in this FPGA
the DDTC is implemented which controls the neutral-
point voltage. Therefore, the FPGA directly controls the
dead-times between T1/T3 and T2/T4. It also collects
measured values of phase-current, temperature and dc-
link voltages and sends them to the dSpace system. With
this test-bench it is possible to realize any desired current
waveform in the RL-load. A schematic of the test-bench
is shown in Fig. 3 . The parameters of the test-bench are
listed in Tab. I . Photos of the test-bench are shown in
Fig. 4 .

410
 Table I
3L-NPC VSC TEST- BENCH PARAMETERS

Device Value
Voltage-source EA-PS 8720-15 Vmax = 720 V,
Pmax = 3 kW
DC-link capacitance C = 4 mF
(one half)
3L-NPC VSC Semikron Mini 3L VDC,max = 800 V,
Sout,max = 50 kVA
Load-inductance L = 4 mH, IL = 16 A
Load-resistance R = 15 , IR = 10 A
Output freuqency fo = [0 . . . 200 Hz]
Carrier frequency fc = 5 kHz
a) Complete test-bench
L iload R

v out

Figure 5. single phase equivalent circuit of the system

IV. E XPERIMENTAL I NVESTIGATION

b) Semikron Mini 3L
c) Load-inductance
A. Current Control
For the regulation of the load current a current con-
troller has been implemented. The equivalent single
phase circuit of the system is shown in Figure 5 . Note
that all time depending variables are space-vectors.
To achieve zero steady state error for the sinusoidal
current shapes, the controller was implemented in a
synchronous d-q-frame [11]. By transforming the space-
vector from the - -frame in the d-q-frame the ac-
quantities, with the angular frequency equal to the totaion
speed of the d-q-frame, become dc-components and can
be regulated by a simple PI-controller without steady
state error.
The transfer function with complex coefficients of the
RL-load in the synchronous d-q-frame is

1
I load R
= , (6)
V out L
1 + (s + j)
R
where I load is the space-vector of the grid current,
V out the space-vector of the converter output voltage in
the Laplace domain, R the load resistance, L the load
inductance and the rotation speed of the synchronous
d) Load-resistance d-q-frame respectively.
Figure 4. Photos of 3L-NPC VSC test-bench
411
 The complex part of the transfer function shows a 20
cross coupling between the d- and the q-current which 10
can be decoupled by a feed forward in the current

vM /V
0
controller [12]. 10
For the tuning of the PI-current regulator the delay of 20
the computation has to be considered. With symmetrical
sampling the total delay is 1.5Tsw , where Tsw is the 20

sampling period. The delay can be approximated by a 10

ia /A
first order delay element in the transfer function. The 0

resulting transfer function (decoupled) is 10

20
1.5 2 2.5 3
1 t/s
I load 1 R
= . (7) a) DDTC with two-position controller
V out 1 + s 32 Tsw 1 + s L
R 20

The controller can now be designed with the technical 10

vM /V
optimum [13]. The resulting transfer function of the PI- 0

controller is 10

20

1 + sT1 20
R(s) = with (8)
sT0 10
L
ia /A

T1 = , (9)
R 10
13
T0 = 2 Tsw . (10)
R2
B. Results
The DDTC can be realized with different controllers.
The results shown in this paper were realized with a PI-
controller and a two-position controller. The tests were
done with an L-load and an RL-load at a phase-current
of Ia = 8 A, a dc-link voltage of VDC = 600 V and an
output-frequency of fo = 50 Hz. The dc-balancing was
deactivated until the neutral-point voltage reached the
start value vms = 20 V. Then, DDTC was reactivated to
observe the dynamic balancing behaviour. Fig. 6 shows
the experimental results for RL-load. The results for L-
load are shown in Fig. 7 . It can be seen that DDTC
is able to balance the dc-link of a 3L-NPC for any
load-angle without any information about the energy-
flow direction. This makes it possible to balance the
dc-link for a load-angle of = 90 which is hard to
realize with state-of-the-art voltage balancing methods.
Depending on the chosen controller and settings, there
are differences in the dynamic and the control deviation.
Due to the high capacitance of the dc-link, the control
deviation of the two-position controller is negligible.
The PI controller needs longer to settle the steady state.
The results show that with both controller and for all
investigated loads, the achieved dynamic and accuracy
0
20
3.6 3.4 3.2 3 2.8 2.6 2.4 2.2 2
t/s
b) DDTC with PI controller
Figure 6. Neutral-point voltage and phase-current for RL-load at
Ia = 8 A and VDC = 600 V with DDTC and different controllers
is sufficient to balance the dc-link. Further, it can be
seen that DDTC does not affect the current control .
V. C ONCLUSION
This paper presented an experimental verification of
a new dc-balancing scheme, Direct Dead-time Control.
Therefore, a test-bench was built. It consists of a 3L-
NPC VSC which is fed by a DC voltage-source. On
the AC-side an RL-load was used to realise different
load conditions. The current control, which was realised
in dSpace, calculates the reference values for the three
phase-voltages. These were passed on to an FPGA which
realized modulation and dc-balancing. The experimental
results show that DDTC is able to balance the dc-link.
The verification was done for different load-angles and
controllers. DDTC is therefore a powerful and simple
way to balance the dc-link of a 3L-NPC VSC without
the need of energy-flow directions and independend from
the chosen modulation scheme.

412
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