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DI-22 Design Idea

TOPSwitch-GX

70 W, 19 V External Laptop Adapter

Application Device Power Output Input Voltage Output Voltage Topology


Laptop Adapter TOP249YN 70 W 85 265 VAC 19 V Flyback

Design Highlights eliminates power-up/down glitches and overvoltage provides line


High efciency: 84% at 85 VAC (with 50 C external ambient transient and long duration power system surge protection.
temperature) Resistor R10 programs the internal current limit to 75% of nominal
Low component count and high power density, 7 W/in.3 at the UV threshold. As a function of input voltage the current limit
Very compact design (4.1 in. 2.225 in. 1.06 in.) is further reduced by R9 to provide approximately constant
No surface mount components required overload power. The larger TOPSwitch-GX selection reduces con-
Low zero load power consumption, <370 mW at 115 VAC duction losses, raising efciency (without circuit changes or
Approximately constant overload power with line voltage increased overload power) and permits a higher inductance
Line undervoltage detection (UV) and overvoltage (OV) shut- design for reduced primary RMS currents, further increasing
down efciency.
Low EMI - switching frequency jitter helps meet CISPR22B/
EN55022B limits To reduce winding and diode dissipation the secondary is split into
Fully protected for overload, short circuit and thermal faults two windings and diode ORed into the output capacitors (C2, 3).
Regulation is provided by a secondary side reference (U3), the
Operation output voltage sensed by R4, R13 and R6.
The design utilizes a TOP249YN in a yback converter providing a
70 W output in a sealed enclosure at an external ambient of
50 C. Line UV and OV (100 V and 450 V, respectively) are
implemented using a single 2 M resistor (R1). Undervoltage
C7
2.2 nF D2
C13 C12 C11 MBR20100
0.33 MF 0.022 MF 0.01 MF
400 V 400 V 400 V Y1 Safety

1 2
VR1 D3
9 MBR20100
P6KE-
200 C3 C14
2 820 MF L1 0.1 MF
BR1 25 V 200 MH 50 V 19 V, 3.6 A
RS805 D1
8 A 600 V UF4006 11
3 8 RTN
C2 C4
820 MF R1 820 MF
D4 25 V 25 V
1N4148 270 7
L2 R11
820 MH 2 M7 R4
2A 6 U2 31.6 k7
1/2 W R8 PC817A
4.7 7 1%
C1 T1 5
150 MF R2
C15 1 k7 R13
400 V 1 MF
C6 TOPSwitch-GX 562 7
0.1 MF D L 50 V C9 1%
U1
X2 L3 TOP249YN 4.7 nF 50 V
CONTROL
RT1 75 MH R9 C
10 7 to 2A 13 M7
1.7 A C10
R3 R7 0.1 MF
S X F 6.8 7 50 V
F1 56 k7
3.15 A C8 U3
R10 TL431
20.5 k7 0.1 MF R6
50 V C5 4.75 k7
85 - 265 47 MF 1%
VAC 16 V
PI-2691-100608

Figure 1. TOPSwitch-GX 70 W Laptop Adapter Schematic.

www.powerint.com October 2008


Key Design Points
Transformer Parameters
D1 and VR1 clamp leakage inductance spikes. A Zener clamp
provides lower zero load consumption than an RCD clamp and FPQ26/20-A TDK PC40, gapped for ALG
Core Material
higher efciency below full load. of 843 nH/t
C11 reduces VR1 dissipation, raising efciency.
Bobbin TDK BPQ26/20-1112CP
Additional differential ltering is provided by C13 and L3.
C12 provides high frequency bypass, reducing high frequency
Primary: 9T + 9T, 2 26 AWG
Shield: 1T, 8 mm 0.015 mm Cu foil
EMI.
Winding Details Secondary 1: 3T, 3 26 AWG T.I.W.
Use foil windings to reduce dissipation and reduce leakage
Secondary 2: 3T, 3 26 AWG T.I.W.
inductance. Bias: 2T, 8 mm 0.015 mm Cu foil
Sandwich secondary winding between two halves of primary to
reduce leakage inductance. Primary (21), Shield (1NC), Tape,
Winding Order Secondary 1 (129), Secondary 2 (118),
High core temperature reduces saturation ux density. Keep (pin numbers)
Bias (65), Tape, Primary (32), Tape
ux density below 3000 gauss (0.3 T) to prevent saturation.
Use 100 V Schottky diodes for highest efciency. Primary: 273 H, 10%
Inductance
Good layout practices should be followed: Leakage: 3 H (maximum)
Locate C8, R3, C5, R9, R10 and R11 close to U1. Primary Resonant 1.5 MHz (minimum)
Power and signal source currents should be separated,
Frequency
joined using a Kelvin connection at the SOURCE pin. Table 1. Transformer Parameters. (AWG = American Wire Gauge,
T.I.W. = Triple Insulated Wire, NC = No Connection)
Minimize the primary and secondary loop areas to reduce
parasitic leakage and EMI.
Consult DAK-11 and EPR-11 for more information.

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5245 Hellyer Avenue Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS
San Jose, CA 95138, USA. MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED
Main: +1 408-414-9200 WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
Customer Service The products and applications illustrated herein (transformer construction and circuits external to the products) may be covered by
Phone: +1-408-414-9665 one or more U.S. and foreign patents or potentially by pending U.S. and foreign patent applications assigned to Power Integrations.
Fax: +1-408-414-9765 A complete list of Power Integrations' patents may be found at www.powerint.com. Power Integrations grants
Email: usasales@powerint.com its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm.
The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, EcoSmart, Clampless, E-Shield, Filterfuse, StackFET,
On the Web PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies.
www.powerint.com 2002, Power Integrations, Inc.

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10/08 DI-22

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