LEC Jumpstart Training Overview

Conformal Logic Equivalence Checking
(LEC)
Version 14.2
Course Agenda
Introduction to Cadence Support & Training

Introduction to Logic Equivalence Checking
Flat Comparison Flow
SETUP mode: Step 1-4
LEC mode: Step 5-8
Hierarchical Comparison Flow
What is hierarchical comparison
Run Dynamic comparison
2012 Cadence Design Systems, Inc. All rights reserved.

2
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4
Conformal L
Baseline Equivalence Checking
RTL2gate and gate2gate
equivalence checking
Verifies all transformations that X <= NOT Y;
RTL
occur during design
implementation Logic Synthesis
Exhaustive verification without Logic Optimization

the use of test vectors
FPGA EC verification targeting Test Insertion
Xilinx and Altera devices Clock Synthesis

Conformal
Equivalence
Semantic and structural Checker
checks Floor Planning
Additional capabilities beyond Placement

EC to detect bugs earlier in the
design cycle Routing
Safest EC solution P&R Optimization
Independent verification finds

ECOs
bugs others miss
Best comparison completion
rate
5
Conformal XL
Verification of Complex Designs with Datapath
Increased use of advanced
datapath optimization by logic
synthesis tools C
A B C A B
Provides formal analysis and
verification solution for X
complex datapath + Merged

Operator
Operator merging
Advanced pipelining Y Y
Retiming Operator Merging

Resource sharing
Supports wide variety of
datapath architectures
Provides analysis tools to
determine causes of non-
equivalences and aborts
Enables multi-threaded Advanced Pipeline Support
compare and functional

partitioning
6
Starting and Exiting
Starting Conformal LEC

Menu mode: lec [L| -XL | -GXL | -ECO | LPXL |
LPGXL]
Command mode: lec [L| -XL | -GXL] -nogui
Switch between menu and command modes: set gui [on |
off]
Batch mode
lec -dofile <batch_file> -nogui
dofile <batch_file>
Exiting Conformal LEC

exit [-force]
LEC automatically closes all windows upon exit.

7
Graphical User Interface (GUI)
Read library Read design Debug tools Mode
Design
hierarchy
window Golden Revised
Transcript
window Messages
Command
entry
window 100% completed
Status Status bar

8
Product Documentation: Tool Environment
Click the Help button in the Encounter Conformal environment to access
documentation for the tools.
Commands: List of all command options, usage,

examples, and related commands
Reference Manual: Command reference with
detailed command usage and definitions
User Guide: Information related to the product, such
as installation, process flow, and graphical interface
The directory location of the PDF manuals is $CONFORMAL_HOME/doc.
On the Encounter Conformal command line, type man <command> to

display command syntax. Append the -verbose option to display a command
explanation.
9
Web Interface
WEB INTERFACE allows you to view products features, Guides, FAQs, Sample dofiles. This Conformal
feature is enabled by starting a server from any Conformal tools. It does not require any additional licenses and
runs concurrently with the main program. The server is automatically shut down when you exit the tool.
Starting the Server

To start the server for web browser viewing, use the set web on -browser command as follow
Set web on browser

LEC will bring up the browser with the appropriate Web Interface starting page

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Web Interface
Documentation Current directory

11
Module 1

12
Golden Standard Revised
Design Library Design
Specify Constraints
and Design Modeling Setup Mode
Specify Compare LEC Mode

Parameters
Compare Designs
yes
Miscompare? Diagnose
no
Equivalence Checking
Complete
13
LEC Flow
SETUP Specifying blackboxes

Reading libraries and designs
Specifying design constraints
Specifying modeling directives
Mapping process
LEC
Resolving unmapped key points
Compare process
Debugging nonequivalent key points

14
Setting Blackboxes and Reading Designs
Run the blackbox command before a module is read in:

add notranslate module *ram* library both
You can read Verilog library and design files at the command line:
add search path /user1/rtl/ -golden
read design *.v verilog golden
add search path /user1/verilog/ -lib -revised
read library library.v -verilog revised
read design revised.v verilog revised

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Design Constraints
U scan_in 0 U
DFF DFF
1 scan_en (0) 1s 1
CLK
Design constraints are users inputs that control part of Golden
CLK
Revised
a designs logic. After Conformal successfully reads the designs Ties U1 DFF
output to 0
and libraries, you can place constraints on the designs U1
U1
0
DFF
DFF
to do the following: CLK
CLK
Exclude sections of a design from verification.

add pin constraint 0 scan_en -revised
DLAT DLAT DLAT DLAT
add instance constraint 0 U1 revised CLK CLK
CLK_n
Specify behavior, such as one-hot or one-cold.
Specify relationships, such as pin equivalence. GND
add pin equivalence CLK invert CLK_n \ SET
SET
-revised
DFF
DFF
Constrain internal nets, such as primary input, primary output,

and tied signals.
Z 0
add tied signal 0 GND -net revised
set undriven signal 0 revised DFF DFF
Constrain instances, such as instance equivalence. CLK CLK

Constrain feedback. net1
add cut point /U1/net1 -revised U1
Z
DLAT

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Modeling Directives
Modeling directives are needed to handle modeling styles specific to vendor

libraries or synthesis tools. en
DFF latch DFF DFF
en
CLK
Examples of Modeling Options Golden Revised
Clock gating
PO 1b1 PO 1b1
1b1 PO
set flatten model gated_clock DFF
CLK
Sequential constant in1 in1 in1
Golden Revised
set flatten model seq_constant
Sequential merging RegB
D0
RegA RegB RegB
set flatten model all_seq_merge

D0
All other modeling options are optional RegA RegC RegA1 RegC D0 RegA RegC
with an XL license:
Golden Revised
Sequential redundant
set flatten model sequential_redundant DFF
PO
DFF
PO
DFF
PO
CLK
CLK CLK
Run analyze setup for the rest of RST

RST
RST
Golden Revised
the modeling options.
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Switching to LEC Mode
set system mode lec

When you change modes from Setup to LEC:
Golden and Revised designs are flattened.
Circuit modeling is performed.
Automatic key point mapping take places after circuit modeling.
All of the steps above happen with one command.
set log file logfile.$LEC_VERSION -replace
add notranslate module *sram* -library -both
read design cpu_rtl.v -verilog -golden
read design -file verilog.vc -verilog -revised
add pin constraint 0 scan_en -revised
set flatten model -latch_fold
set system mode lec
...

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How Is Mapping Done?
What Is Key Point Mapping?

Pairing corresponding golden and revised key points:
G R
PI PI
PO PO
Key points
DFF DFF
Combinatorial logic
DLAT DLAT
BBOX BBOX
CUT CUT Golden Revised
Z Z
E E
SET MApping Method - name first //default
Name-based Followed by Function-based
/core/fd0 /core/fd0
A A /core /core_fd[0]
A /fd0 A
B DFF BB DFF B DFF B DFF
CK CK CK CK
Golden Revised
Golden Revised

19
19
Mapping Manager
Choose Tools Mapping Manager to open the Mapping

Manager, or click the mapping manager icon.
Red-filled circle
in unmapped
Unmapped points indicates
points problems.
Not-mapped
Mapped
points
Extra E
Compared
points
To show only unmapped points:

Unreachable
U
1. Choose Preference Sort by name.
2. Choose Class Disable All.
3. Choose Class Not-Mapped.
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Messages
Example of reported messages:

LEC> report messages Transcript window
// Command: report messages
Report modeling message for Golden
F34: converted X assignment(s) as dont care(s) (Occurrence: 78)
Report modeling message for Revised
F5: Folded DLAT(s) into DFF(s) (Occurrence: 340)
... Transcript window

// Warning: more than 1/3 of the key points have mis-matched names
...
Mapping Takes Too Long

Interrupt the mapping process: Control-c in a UNIX window.
To remap using the name only method, enter
LEC> delete mapped points -all
LEC> set mapping method -name only
LEC> map key points
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Add and Test Renaming Rules Window
In the Conformal LEC window, choose Setup Renaming Rule to

open the Renaming Rule window.
You can add, test, and edit rules in this window.
Middle-click on a key point

in the mapping manager to
copy the contents.
Middle-click to
paste the contents.
Test a new rule before

adding it.
Dofile now has:

add renaming rule rule0 "abc" "xyz -revised
add renaming rule rule2
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Comparison
Compare points are sink points of logic cones, for example:

Primary outputs (PO), cut gates, DFFs, D-latches, and blackboxes
(BBOX)
Only mapped points can be compared.
Comparison is an iterative process.
Conformal remembers points already compared.
Comparison can be interrupted with Control-c.
Enter compare to continue comparing.
/fd0
add compare points -all
DFF PO
compare
/bb0
IN_0 OUT_0
IN_1 OUT_1
BLACKBOX

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All nonequivalences and aborts
Comparison Results need to be resolved.
// Command: compare Transcript window

================================================================================
Compared points PO DFF DLAT BBOX Total
--------------------------------------------------------------------------------
Equivalent 2 146 2 1 151
--------------------------------------------------------------------------------
Non-equivalent 0 2 0 0 2
================================================================================
Filtering comparison
results with the
Mapping Manager
Status indicators Split status indicators show

Equivalent top-level sequential merge
instances equivalence:
Inverted-Equivalent
Design Equivalent
Nonequivalent Sequential Merge Equivalent
Abort Design Equivalent
24
? Not-Compared
Sequential Merge Abort
Displaying Debug Information
Opening the Diagnosis Manager
Use the Mapping Manager to debug:
To display only nonequivalent results
and sort them to show smaller cones
first:
1. Choose Class Disable All
2. Choose Class Non-Equivalent
3. Click the AZ icon and
select Sort by Support Size
To display the Diagnosis Manager:

1. Click left to select a nonequivalent
point (red-filled circle).
2. Click right and select Diagnose.

25
Diagnosis Manager
1 1
A 1 1
1 D
Golden seq0 DFF
11
D QQ seq1
DFF
CP
1 1
A 1 0 0
D Q Color-coded
0
seq0 DFF support points
Q1
Revised D Q seq1 Red: Nonequivalent points
DFF Green: Equivalent points

Black: Points will not be or
CP Cross- are not yet compared
highlighting of
1 1 0 Brown: Abort points
B support key
Error Candidates point and
Noncorresponding Support error pattern
- Points to possible root
Noncorresponding, cause
and not mapped (red) - Highlighted in GUI
M Noncorresponding but
mapped (yellow with M)
26
Schematic Viewer
Open the schematic viewer from the diagnosis manager.
Right-click on any gate

to open its fanin or
fanout cones.
Double-click any gate

to open Source Code.

27
Source Code Manager
From the Diagnosis Manager or the Schematic, you can

open the Source Code Manager.
Signals can be traced

across module boundaries.
Driver and load tracing can

be enabled using
set hdl diagnosis on
before reading designs.

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XL License
Analyze Commands Required
If you have mapping issues after trying renaming rules, run
analyze setup command to automatically resolve setup-
related issues.
analyze setup verbose
If you have aborts in a design with a lot of datapath
components, run the analyze datapath command.
analyze datapath -verbose
If you have aborts, run the analyze abort command after
the initial comparison to resolve the aborts:
// compare
analyze abort compare threads 4

29
Sample Dofile For Flat-Compare Flow
set log file lec.flat.log.$LEC_VERSION -replace
usage -auto -elapse
read library -replace -both ./lib/library.v
read design -replace -golden ./rtl/top.v
read design -replace -revised ./syn/top.gv
report design data
report black box
// Specify user renaming rules if needed to help mapping
add renaming rule rule1 "reg__%d" "reg[@1]" -revised
// Specify user constraints for test
add pin constraint 0 scan_en -both
add ignore output scan_out -both
// Specify modeling directives for constant optimization & clock-gating
set flatten model -seq_constant -gated_clock
// Enable parallel processing, 4 threads
set parallel option -threads 4
// Flattening, remodeling, mapping the design
set system mode lec
// Enable auto analysis to help resolving setup issues
analyze setup -verbose
// Comparison
add compare point -all
compare
// Automatic attempt to resolve abort points if any
analyze abort -compare
30
30
Sample Dofile For Flat-Compare Flow with Datapath
usage auto -elapse
report design data
report black box
add renaming rule rule1 "reg__%d" "reg[@1]" -revised
add ignore output scan_out -both
// Flattening, remodeling, mapping the design
set system mode lec
analyze setup -verbose
// Run analyze datapath on aborts in a design with a lot of datapath components
analyze datapath verbose
// Comparison
add compare point -all
compare
// Automatic attempt to resolve abort points if any
analyze
31 abort -compare 31
Module 2
Hierarchical Comparison Flow

32
What Is Hierarchical Comparison Flow?
Hierarchical comparison is a bottom-up, module-by-module

comparison.
It is done automatically with a tool-generated script or .do file
Requirement: Design must contain some hierarchy
Benefits: Shorter runtime, easier to debug
TOP TOP
U3 U4 U3 U4
U1 U2 A B U1 U2 X
Golden Revised

33
Constraint Propagation
Top-level constraints must be propagated to the lower-level modules to

prevent errors during comparison. To automatically propagate constraints
to all lower-level modules, use the -constraint option when generating the
hierarchical dofile.
Golden Revised
TOP TOP
U1 U1
scan_en SE_0
U2 SE_1
U2
SETUP> set log file hier.log -replace

SETUP> read design rtl.v -verilog -golden
SETUP> read design -file verilog.vc gate.v -revised
SETUP> add pin constraint 0 scan_en revised
SETUP> write hier dofile hier.do constraint \
noexact_pin_match replace -balanced_extraction
SETUP> run hier_compare hier.do
34
XL License
Dynamic Hierarchical Comparison Required
Using dynamic hierarchical comparison, you can

Generate the hierarchical .do file only once
Analyze aborts automatically during comparison
Stop at the first nonequivalent or the first abort result
Compare any submodules more easily
Interrupt with Control-C and continue where left off
SETUP> RUN HIER_COMPARE hier.do -Break_Noneq -Break_Abort
The hier.do file used in the run hier_compare command is generated

using this command:
write hier_compare -run_hier_compare dofile hier.do

35
Sample Dofile For Hierarchical Comparison Flow

usage -auto
report design data
report black box
add renaming rule rule1 "reg__%d" "reg[@1]" revised
add ignore output scan_out both
set analyze option -auto
// Generate & execute the hierarchical dofile script for hier comparison
write hier_compare dofile hier.do -replace -usage \
-constraint -noexact_pin_match \
-prepend_string "report design data; usage ; analyze datapath -module -resourcefile <file> -verbose; usage; \
analyze datapath -verbose; usage" \
-balanced_extraction -input_output_pin_equivalence -function_pin_mapping
run hier_compare hier.do

36
36
Training Information https://www.cadence.com Support & Training
Cadence offers training courses as part of a complete curriculum to

support you in digital implementation. Cadence helps you get the most
out of your investment in our technologies through a wide range of
education offerings.
To complete your learning join the Logic Equivalence Checking with
Encounter Conformal EC class or one of our other classes, via one of
the following:
We provide instructor-led classes that are offered at our training
centers, at your site, or through Virtual Classroom.
We also offer distance learning through our self-paced Internet
Learning Series (iLS).
We offer classes ranging from basic to advanced (our Advance with
Engineer Explorer series), and the ability for you to mix and match to
tailor just the content you need.
Go to https://www.cadence.com Support & Training for more information.

37

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Conformal Logic Equivalence Checking

Introduction to Cadence Support & Training

2012 Cadence Design Systems, Inc. All rights reserved.

Expert instructors share their Logic Equivalence

Self-help tools from Online Support http://support.cadence.com

Rapid Adoption Kits provide a

2012 Cadence Design Systems, Inc. All rights reserved.

Exhaustive verification without Logic Optimization

Xilinx and Altera devices Clock Synthesis

Additional capabilities beyond Placement

Safest EC solution P&R Optimization

Independent verification finds

complex datapath + Merged

Retiming Operator Merging

compare and functional

Starting Conformal LEC

Exiting Conformal LEC

2012 Cadence Design Systems, Inc. All rights reserved.

Read library Read design Debug tools Mode

Status Status bar

2012 Cadence Design Systems, Inc. All rights reserved.

Commands: List of all command options, usage,

The directory location of the PDF manuals is $CONFORMAL_HOME/doc.

On the Encounter Conformal command line, type man <command> to

Starting the Server

Set web on browser

2012 Cadence Design Systems, Inc. All rights reserved.

2012 Cadence Design Systems, Inc. All rights reserved.

Flat Comparison Flow

2012 Cadence Design Systems, Inc. All rights reserved.

Specify Compare LEC Mode

SETUP Specifying blackboxes

2012 Cadence Design Systems, Inc. All rights reserved.

Run the blackbox command before a module is read in:

2012 Cadence Design Systems, Inc. All rights reserved.

Exclude sections of a design from verification.

Constrain internal nets, such as primary input, primary output,

Constrain instances, such as instance equivalence. CLK CLK

2012 Cadence Design Systems, Inc. All rights reserved.

Modeling directives are needed to handle modeling styles specific to vendor

set flatten model all_seq_merge

Run analyze setup for the rest of RST

set system mode lec

2012 Cadence Design Systems, Inc. All rights reserved.

What Is Key Point Mapping?

2012 Cadence Design Systems, Inc. All rights reserved.

Choose Tools Mapping Manager to open the Mapping

To show only unmapped points:

Example of reported messages:

... Transcript window

Mapping Takes Too Long

In the Conformal LEC window, choose Setup Renaming Rule to

Middle-click on a key point

Test a new rule before

Dofile now has:

Compare points are sink points of logic cones, for example:

2012 Cadence Design Systems, Inc. All rights reserved.

// Command: compare Transcript window

Status indicators Split status indicators show

To display the Diagnosis Manager:

2012 Cadence Design Systems, Inc. All rights reserved.

DFF Green: Equivalent points

Open the schematic viewer from the diagnosis manager.

Right-click on any gate