Chapter 3

A Top-Level View of
Computer Function and
Interconnection

William Stallings
Computer Organization
and Architecture
 Revision
Bit = smallest quantity of information

Word = a group of bits, e.g. 8-bit word, 160-bit

word

Byte = 8-bit

n-bit word can be arranged into 2n unique bit

patterns

2 bits => 4 values, 8 bits => ? Values, 64 bits?

Is 8-bit word computer more accurate then 4-

bit word computer?
Computer Specifications?
Processor

RAM

Size

Operating System

Clock Speed

Max TDP / Power

?
 System Concept:
Hardware Vs Software
Problem with hardware:
Hardwired computer systems,
i.e. inflexible, particularly for a
general purpose hardware
because it has to re-route
wired connections for different
tasks.
Solution using software:
Instead of using hardwires,
supply unique control signals
to general purpose hardware
to do various different tasks.
How?
Using programs to control
or/and correctly route the
control signals.
For each operation, a set of
different control signals is
needed.
 Control Signals
What controls the signals?
A control unit or simply known as a controller

How does its implementation work?

Each operation (e.g. ADD, MOVE) is represented by a
unique code which are then converted into 1s and 0s

Then, a hardware segment accepts the converted

code, interpret it and be able to issues the correct
control signals

Hence, we get an electronic device called

a computer!
 Major/Main Computer
Components

CPU
Constitute the control Unit and ALU

Input/output
Data and instructions need to get into the
system and results out

Main memory
Storage place for code/instructions and
data
Computer Components:Top Level View
 Computer function:
Basic Instruction Cycle

Two steps:
Fetch
Execute
 Fetch Cycle

Program Counter (PC) holds address of next instruction

to fetch

Processor fetches instruction from memory location

pointed to by PC

PC is incremented unless told otherwise

Then fetched instruction loaded into Instruction

Register (IR)

Processor interprets instruction and performs required

actions
 Execute Cycle
Data movement
Processor-memory: data transfer between CPU
and main memory

Processor-I/O: data transfer between CPU and

I/O module

Data processing
Some arithmetic or logical operation on data

Control
Alteration of sequence of operations
e.g. jump

Combination of above
 Example of Program Execution
Load
(opcode 1)
into AC
the
content of
addr 940
Add
(opcode 5)
AC with
content of
addr 941

Store
(opcode 2)
result in
addr 941
 Instruction Cycle - State Diagram
Write
result in
memory or
out to I/O

Analyze Exec
instr operatn

If inv ref to operand in

Next instr
memory or I/O
addr
 Interrupt
What is an interrupt?
It is a signal sent to the processor by a
particular hardware or software unit to
indicate that an event needs immediate
attention, and that its process needs to be
executed first.

This interrupt mechanism by a module (e.g.

I/O) will interrupt the normal sequence of
processing so that an event of higher
priority can be executed.
 Sources of Interrupts
Program
e.g. overflow, division by zero

Timer
Generated by internal processor timer
Used in pre-emptive multi-tasking

I/O
from I/O controller

Hardware failure
e.g. memory parity error
Program Flow Control
 Interrupt Cycle
Added to instruction cycle
Processor checks for interrupt
Indicated by an interrupt signal
If no interrupt, fetch next instruction
If interrupt pending:
Suspend execution of current program
Save context
Set PC to start address of interrupt handler
routine
Process interrupt
Restore context and continue interrupted
program
Transfer of Control via Interrupts
Instruction Cycle with Interrupts
Program Timing Short I/O Wait
Instruction Cycle (with Interrupts) -
State Diagram
 Multiple Interrupts
Disable interrupts
Processor will ignore further interrupts whilst
processing one interrupt
Interrupts remain pending and are checked
after first interrupt has been processed
Interrupts handled in sequence as they occur

Define priorities
Low priority interrupts can be interrupted by
higher priority interrupts
When higher priority interrupt has been
processed, processor returns to previous
interrupt
Multiple Interrupts - Sequential
Multiple Interrupts Nested
Time Sequence of Multiple Interrupts
 Computer Connection
All main computer components (i.e. CPU,
memory, I/O) are connected via a system
interconnection

Each computer component has input and

output connections for communication.

Why need a connection?

Components need to work as a team. Hence,
they need to communicate, via a connection.

Hence, computer components are

designed as modules
Computer
Modules
Different types of
connections for
different modules
for the purpose of
communication
and/or data
movement
 Memory Module
(4)
Receives data (1)

(5)
Sends data (2)
(2)
(3)
Receives addresses (of
locations) (3)
(1)
Receives control
signals operations
Read (4)
Write(5)
 Input/Output
Connection(1)
Control signals operations
for
Read
Write

Receive addresses from

computer
e.g. port number to
identify peripheral

Receive internal data from

computer

Receive external data

from peripheral
 Input/Output
Connection(2)

Send internal data to

peripheral/computer

Send external data to

peripheral/computer

Send interrupt signals

to processor (control)
 CPU Module
Operations
Reads instruction
Receives data

Receives (& acts on)

interrupt signals

Sends control signals

to other units to control
all operations

Writes out data (after

processing)
Computer Interconnection Structure
Memory to processor
Processor reads instruction or data from memory

Processor to memory
Processor writes data to memory

I/O to processor
Processor reads data from I/O device
via I/O module

Processor to I/O
Processor sends data to I/O

I/O to or from memory

Data exchange using DMA
i.e. w/o involving processor
Computer Components: System Bus
 Bus
What is a bus? A communication pathway connecting
devices/components

How it looks like? Consists of multiple lines (i.e. a bundle of

wires)/communication pathways to transmit signals

How it transmit?
Using single bit signal 1s or 0s each line
Need multiple lines for multiple digits transmission

What is a system bus? Bus connecting main computer

components
3 buses data, address, control

Transmission method
When? At one time, only one device can transmit
How? Use broadcast technique
Why broadcast? One bus connects multiple devices
Bus Interconnection Scheme
 Data Bus
A collection of lines that carry data b/w
modules

Number of lines determines:

the width of bus; 8, 16, 32, 64 bit

Is a key determinant of system

performance

Why? E.g. if bus is 32-bit wide, but data

is 64-bit long, CPU must access memory
twice for each instruction cycle
 Address bus
Identify the source or destination of data

e.g. CPU needs to read an instruction (data) from a

given location in memory
Addr of instruction is transmitted along the addr
bus

e.g. a peripheral device transfers data to main

memory
Addr of data is transmitted along the addr bus

Bus width determines maximum memory capacity of

system
Now >= 32 lines
 Control Bus (1)
Control access and use of data and addr buses

Carries commands, requests and msg, timing info

Memory read/write signal
Interrupt request
Clock signals

Operations
Memory read get data of specified addr from memory
via addr bus, put onto data bus

Memory write put data onto data bus, addr onto addr
bus, transmit to memory

I/O read put addr of I/O port onto addr bus, get data
from I/O via data bus

I/O write addr of I/O port onto addr bus, put data
onto data bus, send to specified I/O
 Control Bus (2)
Msg
Transfer ACK ackowledge receipt of data or
transmission of data
Interrupt ACK ackowledge receipt of interrupt
request

Request
Bus request a module requests to use the bus
Bus grant permission to use bus sent out

Timing
Clock to synchronize operations
Reset Initializes all modules
 Bus Clock Rate

Bus clock rate = freq of bus pulses

Measured in MHz

It marks the start of new data

transmission
 Bus Cycle

Bus cycle time = time interval from one

clock pulse to the next

Bus cycle time = 1/bus clock rate

E.g. If bus clock pulse or rate = 200MHz,

bus clock time = 5 ns

Bus cycle cannot be shorter than the time

needed for an electrical signal to traverse
the bus from one module to another.
 Data Transfer Rate
Is a measure of communication capacity

Also referred to as bus capacity

Bus capacity or data transfer rate = data

transfer unit* bus clock rate

E.g. A system with 64-bit data bus has 200

MHz clock rate. What is its bus capacity?
Ans:
64 bit * 200MHz =12.8Gbits/s
=1.6GBytes/s
 High-Speed Buses in Modern
Computer System (1)

Processor Bus or Local bus

Highest-speed bus in the system
Core of the chipset and motherboard
Used primarily by processor to pass info
to and from cache or main memory

AGP (Accelerated Graphics Port) Bus

High-speed 32-bit bus for video card
manifested as a single AGP slot
 Expansion Buses
PCI (Peripheral Component Interconnect) Bus
Maximum as 64-bit bus
Manifested as several slots
For plugging network cards, video cards etc

VESA (Video Electronics Standards Association)

EISA (Extended Industry Standard Architecture)

MCA (Micro Channel Architecture)

ISA (Industry Standard Architecture) Bus

Slow in speed
Used for low-speed peripherals
No longer included in new system
 Expansion Bus and Slots
Expansion bus carried data to and from
expansion slots, which are sockets designed to
hold the circuit board for a device that adds
capability to a computer system.
The circuit board for an add-on device is called
an expansion card or expansion board or
controller cards, adapter cards or interface
cards.
An expansion card is usually connected to a
device it controls by a cable.
The socket that holds the card is connected to
an expansion that transmit data to memory or
CPU.
Expansion Slots
Point-to-Point Interconnect
At higher and higher
Principal reason for data rates it becomes
change was the electrical
increasingly difficult to
constraints encountered
perform the
with increasing the
frequency of wide synchronization and
synchronous buses arbitration functions in a
timely fashion

A conventional shared
bus on the same chip Difficulties of reducing
magnified the difficulties bus latency with
of increasing bus data increasing number of
rate to keep up with the computer peripherals
processors
 SOLUTION:
Point-to-Point Interconnect

1. QuichPath Interconecction
(QPI)

2. Peripheral Component
Interconnect (PCI)
+
Quick Path Interconnect
Introduced in 2008
QPI
Multiple direct connections

Direct pairwise connections to other

components eliminating the need for
arbitration found in shared transmission
systems
Layered protocol architecture

These processor level interconnects use

a layered protocol architecture rather
than the simple use of control signals
found in shared bus arrangements
Packetized data transfer

Data are sent as a sequence of packets

each of which includes control headers
and error control codes
 PCI
Peripheral Component Interconnect

Introduced by Intel in 1992

Solution to the problem of slow ISA bus

Designed for address and data bus

High bandwidth
Bus width at least 32-bit

Cannot be used with 8-bit and 16-bit sections

Can be extended to 64-bit

High speed
Processor independent bus
 PCI Bus

Intel released version 1.0 to public domain in

1992

Later updated in 1993, then 1995.

Designed
To support different MP-based configuratns including
single and multiple processor systems
To make use of synchronous timing

May be configured as 32-bit or 64-bit bus

 PCI Bus Structure (1)
PCI units connected to the PCI bus
E.g. network, graphics, SCSI host
adapters and I/O units

These units are also referred to as agents

PCI concept is the decoupling of the

processor and expansion bus through PCI
bridge
 PCI Bus Structure (2)
Although PCI may have 4 or 5 slots, it is actually
possible to connect PCI bus with up to 10 PCI
units.

PCI bridge connects the subsystems of the

processors RAM and the PCI bus

The interface to the expansion bus such as the

ISA bus is another PCI unit.

In principle, every bus system can be

intergrated and connected to the PCI bus.
PCI Bus Structure
 PCI Bus Lines (required)
(Table 3.3 of textbook)
Systems lines
Including clock and reset

Address & Data

32 mux lines for address/data
Interrupt & validate lines

Interface Control lines

Controls and coordinate timings

Arbitration
Not shared, i.e. each PCI master has its own
connection directly to PCI arbiter

Error lines
To report parity or other errors
 PCI Bus Lines (Optional)
(Table 3.4 of textbook)
Interrupt lines
Not shared

Cache support

64-bit Bus Extension

Additional 32 lines
Time multiplexed
2 lines to enable devices to agree to use 64-bit
transfer

JTAG/Boundary Scan
For testing procedures
 PCI Commands
Bus activity occurs in the form of transaction
between initiator (master) and target.

How?
Master claims bus and determines type of transaction
that will occur, e.g. I/O read/write

During address phase of transaction, C/BE

lines of bus extension lines are used to signal
transaction type by providing bus commands.

Data transfer on PCI bus involves a single

transaction consisting of address phase and
one or more data phases
PCI Read Timing Diagram
PCI Bus Arbitration
Discussion / Assignment
 PCI Express, AGP & PCI
Year of
Slot kind Peak transfer speed
introduction

PCI-Express x16 2004 4 GB/s write speed and 4 GB/s read speed simultaneously

PCI-Express x1 2004 250 MB/s write speed and 250 MB/s read speed simultaneously

bandwidth shared between reads and writes to a maximum of 2.133 GB/s;

AGP 8X 2002
many implementations are limited to 267 MB/s read speed

bandwidth shared between reads and writes to a maximum of 1.067 GB/s;

AGP 4X 1998
many implementations are limited to 267 MB/s read speed

bandwidth shared between reads and writes to a maximum of 533 MB/s;

AGP 2X 1996
many implementations are limited to 267 MB/s read speed

AGP 1X 1996 bandwidth shared between reads and writes to a maximum of 267 MB/s

PCI 1993 bandwidth shared between reads and writes to a maximum of 133 MB/s
 Discussion/Assignment
What is PCI?

PCI vs AGP?

For video/graphics card, AGP is faster or

PCI is faster?

What is PCI Express (PCIe)?

PCI vs PCIe?

Is PCI compatible to PCIe?

 Chapter 3 Questions
1. List ALL bus design elements.
2. What is an arbiter?
3. What is meant by bus width?
4. The width of the data bus determines
the system performance. TRUE /
FALSE
5. If the width of a data bus is 32-bit, and
an instruction is 64 bits long, how may
times a processor need to access a
memory module every time it needs to
fetch the instruction?
6. What is the purpose of having an
interrupt in a computer?
 Chapter 3 Solutions
1. Bus design elements
Type (Dedicated or Multiplexed )
Bus Width (how many lines for address and data
etc)
Method of Arbitration (Centralized or Distributed)
Data Transfer Type (Read, Write, Read-modify-write
Read-after-write, Block)
Timing (Synchronous or Asynchronous)

1. An arbiter is a bus controller.

2. The number of lines a bus has.
3. TRUE
4. 2 times or twice
 Chapter 3 More Questions
1. What is a program?

2. What is a process?

3. How does computer components communicate

among one another?

Interrupts can come from hardware and software.

1. Simply describe how a hardware component or

device issue/trigger an interrupt.

2. Why the CPU?

3. Briefly explain how software issue/trigger an

interrupt.
 Chapter 3 More Solutions
1. A program is a collection of step-by-step instructions to
be presented to a computer for accomplishing a certain
task.
2. A process is a program in execution or simply, a
process is a running program.
3. Through system interconnection structure, particularly
via system bus.

==========================

1. By sending a signal to the CPU.

2. Most the time the CPU will be executing jobs.
3. By executing a special program known as a system call
or a monitor call.