IJSTE - International Journal of Science Technology & Engineering | Volume 3 | Issue 08 | February 2017

ISSN (online): 2349-784X

A Novel Low Power, High Speed Design of Phase

Frequency Detector (PFD) using 180nm
Technology
Sumit Kumar Singh Amit Gupta
M. Tech. Student Assistant Professor
Department of Electronics & Communication Engineering Department of Electronics & Communication Engineering
Galgotiya College of Engineering, Greater Noida, India Galgotiya College of Engineering, Greater Noida, India

Abstract
As technology is shrinking down high speed, low power device demands circuitry which works faster. Considering into account,
here we proposed a new phase frequency detector (PFD) with 4 transistors. A GDI (Gate Diffusion Input) - a new technique of
low power digital circuit design is used to implement new circuit. Due to less number of transistors it consumes less power and
gives less delay in circuit. Proposed phase frequency detector is used in phase lock loop. Proposed design gives 56% reduction in
power and 76% reduction in delay. Simulation has been done in 180 nm TSMC technology CMOS environment.
Keywords: Phase Lock Loop, Dead Zone, Gate Diffusion Input
________________________________________________________________________________________________________

I. INTRODUCTION

AM radio receivers, frequency demodulators, multipliers, dividers, and as frequency synthesizers uses Phase Locked Loop
(PLL). The power consumption in the PFD contributes to a significant part of the total power consumption of a PLL. Therefore
overall power consumption in a PLL can be reduced by minimizing the power consumption in PFD. The main challenge in the
design of PFD is to obtain very high operating frequency with minimal power dissipation.

Fig. 1: Basic Block Diagram of PLL

The phase frequency detector (PFD) is one of the main parts in PLL circuits. PFD produces an error output signal which is
proportional to the phase difference between the phase of the feedback clock and the phase of the reference clock. The Charge
Pump (CP) is another important part of PLL. CP converts the phase or frequency difference information of two input signals into
a voltage which is used to tune a Voltage Controlled Oscillator (VCO) toward reference input frequency. Thus, the Loop Filter
(LF) is necessary to generate necessary control signals into the VCO and is also necessary to store the charge from the CP. The
purpose of the VCO is to either speed up or slow down the feedback signal according to the error generated by the PFD, if the
PFD generates an up (UP) signal, the VCO speeds up. On the contrary, if a down (DN) signal is generated, the VCO slows down.
The output of the VCO is then fed back to the PFD in order to recalculate the phase difference, thereby forming the closed loop
frequency
The paper is organized as follows: Section 2 discusses about some existing phase frequency detector (PFD), Section 3
describes circuit design and working principle of the proposed novel phase frequency detector (PFD). Section 4 describes the
detailed analysis of the characteristics of the proposed cell and comparison with other existing phase frequency detector (PFD)
and finally, Section 5 concludes the paper.

II. CONVENTIONAL PFD DESIGN

In order to increase the operating frequency of the PFD, reset path is eliminated by adding pass transistor logic. The proposed
PFD (PFD1) uses only 10 transistors which reduces the power consumption and area of the PLL. Fig.3. Schematic of the
designed PFD is shown in Fig 2. P3 through P6 are PMOS transistors while N7 through N12 is NMOS transistors. Principle of
operation is explained below. Initially the CLKref and CLKvco signals are at logic zero. At the rising edge of CLKref, N7, N8

All rights reserved by www.ijste.org 140

 A Novel Low Power, High Speed Design of Phase Frequency Detector (PFD) using 180nm Technology
(IJSTE/ Volume 3 / Issue 08 / 023)

and N12 turns on and the UP signal goes to logic high. At the rising edge of CLKvco, N9, N10 and N11 turn on forcing DN to
go high. When both UP and DN are high, the logic levels at points R and S in Fig. 3 are pulled down to logic zero making UP
and DN to go to logic zero without any delay for reset.

Fig. 2: The phase frequency detector (PFD).

Fig. 3: Simulation Diagram of the phase frequency detector (PFD).

All rights reserved by www.ijste.org 141

 A Novel Low Power, High Speed Design of Phase Frequency Detector (PFD) using 180nm Technology
(IJSTE/ Volume 3 / Issue 08 / 023)

III. PROPOSED PHASE FREQUENCY DETECTOR (PFD)

Fig. 4: The proposed phase frequency detector (PFD).

Fig.4 shows circuit diagram of new proposed phase frequency detector (PFD) working of proposed design is same as that of
previous conventional phase frequency detector (PFD) but here we made some modification such as, In modification, we remove
unwanted pass transistor. Here we apply input by GDI technique. GDI (Gate Diffusion Input) - a new technique of low power
digital circuit design is described. This technique allows reducing power consumption, delay and area of digital circuits, while
maintaining low complexity of logic design.

Fig. 5: Simulation Diagram of the proposed phase frequency detector (PFD).

All rights reserved by www.ijste.org 142

 A Novel Low Power, High Speed Design of Phase Frequency Detector (PFD) using 180nm Technology
(IJSTE/ Volume 3 / Issue 08 / 023)

IV. RESULT AND CONCLUSION

A proposed design is simulated using Tanner EDA Tool using TSMC 180nm technology at 1.8V supply. Fig.5 shows output
waveform of proposed phase frequency detector (PFD). Obtained result of new design is compared with old phase frequency
detector (PFD) and tabulated in table 1 as shown.
Table - 1
Conventional (PFD) vs Proposed (PFD) Comparison
Parameters Base Designs Modified Designs
Technology 180nm 180nm
Supply voltage 1.8V 1.8V
Power 4.35 uW 1.93 uW
Delay 47.341 ps 11.176 ps
PDP 209.48 aJ 22.798 aJ
Energy 442.5 fJ 155.09 fJ
EDP 20.948 yJs 1.8239 yJs

V. CONCLUSION

As, technology changes day by day power dissipation and stability are major issue of any high speed device. The proposed phase
frequency detector (PFD) is solution of this problem which uses only 4 transistor for PFD to give less power dissipation with
high speed operation. Different implementation of a novel Gate-Diffusion Input (GDI) technique for low-power design were
presented. A proposed novel phase frequency detector (PFD) gives less power dissipation than previous design. Simulation is
carried using Tanner Tolls on TSMC 180 nm technology.

REFERENCES
[1] Mansuri, M., Liu, D., Yang and C.-K.K., "Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops," Solid-State Circuits,
IEEE Journal of , vol.37, no.10, pp.1331,1334, Oct 2002.
[2] Ismail, N.M.H. and Othman, M., "CMOS phase frequency detector for high speed applications," Microelectronics (ICM), 2009 International Conference on
, vol., no., pp.201,204, 19-22 Dec. 2009.
[3] Wu-Hsin Chen, Inerowicz, M.E. and Byunghoo Jung, "Phase Frequency Detector With Minimal Blind Zone for Fast Frequency Acquisition," Circuits and
Systems II: Express Briefs, IEEE Transactions on , vol.57, no.12, pp.936,940, Dec. 2010.
[4] Fan Xiangning, Li Bin, Yuan Likai and Wang Yujie, "CMOS Phase Frequency Detector and Charge Pump for Wireless Sensor Networks," Microwave
Workshop Series on Millimeter Wave Wireless Technology and Applications (IMWS), 2012 IEEE MTT-S International , vol., no., pp.1,4, 18-20 Sept.
2012.
[5] Hwang-Cherng Chow, Yeh and N.-L., "A new phase-locked loop with high speed phase frequency detector," Circuits and Systems, 2005. 48th Midwest
Symposium on , vol., no., pp.1342,1345 Vol. 2, 7-10 Aug. 2005.
[6] N. Weste, K. Eshraghian, Principles of CMOS Digital Design, Addison-Wesley, pp. 304-307. A. P. Chandrakasan, R. W. Brodersen, Minimizing Power
Consumption in Digital CMOS Circuits, Proceedings of the IEEE, vol. 83, no. 4, pp. 498-523, April 1995.
[7] W. AI-Assadi, A. P.Jayasumana and Y. K.Malaiya, Passtransistor logic design, International Journal of Electronics, 1991, vol. 70, no. 4, pp. 739-749.
[8] I. S. Abu-Khater, A. Bellaouar, M.I. Elmastry, Circuit Techniques for CMOS Low-Power High-Performance Multipliers, IEEE Journal of Solid-state
Circuits, vol. 3 I, no. 10, pp. 1535-1546, October 1996.
[9] T. Sakurai, Closed-Form Expressions for Interconnection Delay, Coupling, and Crosstalk in VLSIs, IEEE Transactions on Electron Devices, vol. 40, no.
1, pp. 11 8- 124, January 1993.

All rights reserved by www.ijste.org 143