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HomeELECTRONICSVLSI/VHDL/VerilogDSPApplicationsAFullyDigitalFrontEndArchitectureforECGAcquisitionSystemWith0.5VSupply2016

A FULLY DIGITAL FRONT-END ARCHITECTURE FOR ECGACQUISITION SYSTEM WITH 0.5 V

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SUPPLY 2016
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DSPApplications February3,2017

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A Fully Digital FrontEnd Architecture for ECGAcquisition System With 0.5 V

Supply2016
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Abstract:
Subject
This paper presents a new powerefficient electrocardiogram acquisition system
that uses a fully digital architecture to reduce the power consumption and chip Re: A Fully Digital FrontEnd Architecture for ECGAcquisition System With 0.5 V Supp
area.TheproposedarchitectureiscompatiblewithdigitalCMOStechnologyand
Message
iscapableofoperatingwithalowsupplyvoltageof0.5V.Inthisarchitecture,no
analog block, e.g., lownoise amplifier (LNA), and filters, and no passive
elements,suchasaccouplingcapacitors,areused.Amovingaveragevoltage
totimeconverterisused,whichbehavesinsteadoftheLNAandantialiasingfilter.Adigitalfeedbackloopisemployedtocancelthe
impactofthedcoffsetonthecircuit,whicheliminatestheneedforcouplingcapacitors.Thecircuitisimplementedin0.18umCMOS
process.Thesimulationresultsshowthatthefrontendcircuitconsumes274nWofpower.

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