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# Exercise 4: Noise margin of Invertor and Realization of Logic Gates using

CMOS
Objective: (A) Identifying the V IL , V IH , V oL, points on the VTC curve for Noise margin
Analysis
(B) Logic Gates Implementation:
a) Using CMOS, realize the following Logic gates: NOT, NAND, NOR, XOR, XNOR
b) Calculate the propagation delay in each output transition
c) Perform DC analysis for obtaining VTC (voltage transfer curve) for the logic gates
A) NOISE MARGIN: Noise margin is the amount of noise that a CMOS circuit could withstand
without compromising the operation of circuit. Noise margin does makes sure that any signal
which is logic '1' with finite noise added to it, is still recognised as logic '1' and not logic '0'. It
is basically the difference between signal value and the noise value.

## a) Calculate the Noise margin of CMOS invertor (dc analysis)

[Ref: Rabaey book, pp. 152-155, Section 5.3.2]
d V out
V IL and V IH are operational points of the invertor where =1
dV
d V out
Plot : dV vs V curve and find V IH and Wp Lp Wn Ln

## V IL points and N M H =V OH V IH 10 180n 10u 180n

and
u
N M L =V ILV OL .
First plot V_out vs V_in , then select plot-> right click-> calculator-> derivative
b) Verify the noise margin from theory (for long channel) [Ref: Kang book, pp. 179-181]
From (5.59), when V out =high , V =low ,

Resulting in (5.62),
Wn

kr =
kn
=
n C ox ( )
Ln
n 2.8 p
kp Wp
where p C ox
( )
Lp
and

## From (5.64) when V out =low , V =high

Resulting in (5.67)
V T n =0.55V , V T p =0.55V
0 0

Note:
c) Comment on noise margin behaviour (Parametric dc analysis: V out vs V ) by varying
Wp W p 30
i) Wn from 10/10 to 50/10 ( V DD=1.8 V ) ii) V DD from 1V to 1.8 V ( =
W n 10 )
d) i) Simulate the symmetric CMOS invertor (dc analysis)and retrieve the noise margin
ii) Verify the results with theory [Kang book, pp. 185]
In symmetric mode of operation:

## B) Transient Analysis: a) Realization of gates and b) Propagation Delay

i) For all the gates, the symbols are created and then, each symbol is used in a new schematic with
circuit in Fig.5, for transient analysis. (NOTE: for NOT gate, only 1 input source exists)
Variables: Lp(180n), Wp(30u), Ln(180n), Wn(10u), V_dd(1.8 V), T(1n) source: vbit (transient analysis)

Fig.1 : CMOS invertor for NOT before symbol creation Fig . 2: Symbols created in Cadence for all the logic gates.
Fig. 3: Circuit for NAND symbol Fig. 4: Circuit for NOR symbol Fig. 5: Circuit for testing the logic gate symbols
(2 pmos, 2 nmos) (2 pmos, 2 nmos) (Transient analysis: input source type : vbit)

Fig. 6: Circuit for XOR symbol (Add pins V_dd and gnd) Fig. 7: Circuit for XNOR symbol

ii) Transient analysis: To test the functionality and for calculating propagation delay(as in
exercise4), two vbit sources are the input to the symbols as shown in Fig. 5.
vdc is the dc power source for the circuit with V_dd as the value.
Note: NOT gate requires only one input vbit source(Pattern parameter data:0,1)

## Pattern parameter data 0,0,1,1 (Source A) Zero Value 0

0,1,0,1 (Source B)
Pattern parameter rptstart 1 Rise Time 0.1*T
Pattern parameter rpttimes 0 Fall Time 0.1*T
One value V_dd Period T
iii) In ADE-L, import the variables and assign values as specified in (i). Analysis type : Transient
analysis: approx. five times the period (5n s). Output to be plotted are : Y, A, B
iv) Save the transient response plots for all the logic gates.
v) Complete the truth table for each symbol.
vi) Propagation delay: From the transient analysis plot, Compute the propagation delay in each
output transition (Low to High and High to Low).
DC Analysis: c) VTC Curve for the logic gates
i) Set the sources as :Power source : vdc (V_dd) Input souce: vdc (V_in)
ii) Connect the inputs as given in the table below for performing DC analysis on individual
gates:

GATE A B
NOT V_in -
NAND (Tied input) V_in V_in
NOR (Tied input) V_in V_in
XOR V_in 0 (gnd)
V_in 1 (V_dd)
XNOR V_in 0 (gnd)
V_in 1 (V_dd)
Fig. 8: DC analysis: Tied input: NOT, NAND and NOR Fig. 9: DC analysis: NAND and NOR B input: either ground or V_dd