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Abstract
As device scaling is entering the sub-25nm range, multiple gate device architectures are needed to fulfill the ITRS
requirements, since they offer a greatly improved electrostatic control of the channel. However, practical realization of
multiple gate devices face with technological issues, mainly linked to the use of very thin films or very narrow active areas.
On the other hand, these architectures are very likely to allow the performance improvement trend down to the sub-10nm
regime and can offer new circuit design opportunities.
In planar architectures, the structure can be non form a tunnel below the silicon film, and this tunnel
self-aligned, i.e. fabricated with one photo- is filled by the gate material.
lithography step for each gate, or self-aligned, using In the PAGODA architecture [8], the unpatterned
only one lithography step to define both gates. The back gate stack is deposited and encapsulated before
non self-aligned architecture by wafer bonding is the wafer bonding. After initial substrate removal, the
most straightforward approach to fabricate planar front gate is patterned and silicon spacers
double gate. The success of this approach depends on recrystallized from the channel are formed and
the lithography capability to align very short gates salicided. These salicided spacers are used as a hard-
one to the other. Figure 1 shows a 10nm non self- mask for back gate etching and undercut.
aligned planar double gate transistor, fabricated The process flow proposed in [9] starts also from
thanks to the use of wafer bonding and e-beam back gate stack deposition and wafer bonding. The
lithography. Notice that a quasi-perfect gate whole stack, comprising the front gate, the channel
alignment, with an accuracy of a few nanometers, and the back gate is then patterned. Insulated layers
could be achieved thanks to the self-aligned are formed besides the gates by use of oxidation rate
regeneration of the alignment marks after the difference between the gate and the channel
bonding step [5]. materials. Source/drain regions are then regenerated
by lateral epitaxial regrowth from the channel edges.
Salicided elevated
The key technological issues of these planar
source/drain architectures are the precise controls of the very thin
film thickness and of the back gate dimension, since
the back gate is not directly accessible from the top
of the wafer.
On the other side, structures with fingered vertical
TiN Front gate channel, such as FinFET [10], Trigate [11], :-FET
Back gate [12], 3-Gate [13] and nanowire-FET [14] have been
extensively studied. Fabrication of FinFETs relies on
high aspect ratio fin definition and short gate
6nm thick patterning on this topology (fig. 2). Contrary to
mono-Si channel planar devices, the conduction takes place on the
vertical sidewalls of the fin. The conduction width is
thus twice the fin height (hfin). As the fin height is
Fig.1 TEM cross-section of a 10nm planar bonded double limited to typically 50 to 100nm, FinFETs are usually
gate transistor with TiN metal gates.. designed as multifinger transistors, with a conduction
width quantified by 2.hfin. In order to obtain the same
Several approaches have been proposed to drive current per silicon area as planar double gate
fabricate self-aligned planar double gate MOSFETs. transistors, the pitch between the fingers has to be
The first one consisted in patterning a narrow silicon lower than the fin height.
active area on a SOI substrate, etching a localized
cavity under this active area into the buried oxide, Drain
Thus, one key technological issue lies in the :-FET and 3-Gate architectures are basically
multi-fin definition. Dense array of narrow fins have similar to Trigate, but their channel control is close to
to be patterned, with a good control of the fin width that of a quadruple-gate device, thanks to the
and shape. The use of spacers as hard-mask for fin extension of the gate below the fin into the buried
patterning seems unavoidable, as it allows to double oxide [16].
the fin density and to design sub-10nm wide fins
[15]. 3. Design of fully-depleted devices
All these multiple gate devices are designed with
very thin active area. The use of polysilicon gates
would lead to unacceptable channel doping levels,
higher than 1019cm-3, in order to get appropriate
Dr
ai
Gate
enhanced transport properties of low doped channels,
their threshold voltage being adjusted thanks to
Ga
Fin
te
and m* is the carrier confinement mass in the With an EOT of 1nm and a film thickness around 5-
transverse direction. 10nm, this condition is verified for channel doping
Figure 5 gives the dependence of the threshold levels lower than a few 1017cm-3.
voltage with the film thickness. We notice that the Low doped channel fully depleted devices are
last term of (4), due to the confinement induced by thus theoretically immune from dopant fluctuation
the quantum well formed by the thin silicon layer effects, which is one of the most important limitation
between the two gate dielectrics, becomes significant of bulk transistor scaling [18,19].
for film thickness below 5-7nm. However, with a channel doping level of 1015cm-3
(i.e. intrinsic channel), a LxW=10x20nm transistor
0,58
0.58 with a film thickness of 5nm has a probability of
0.56
0,56 'Imi=0eV, EOT=1.2nm containing a dopant atom equal to 0.1%. In other
Threshold voltage (V)
0,54
0.54 terms, 1 device over 1000 is likely to contain one
0.52
0,52
0,5
0.50
impurity atom, inducing a doping level of 1018cm-3,
0,48
0.48 while the others are dopant free. The electrostatic
0,46
0.46 effect of this impurity atom has to be simulated and
0,44
0.44
0,42
its impact on the electrical characteristics should be
0.42
0.40
0,4 carefully estimated.
0 5 10
10 15 20
20 Furthermore, from figure 5, we notice that the
Silicon film thickness (nm) threshold voltage becomes very sensitive to the film
thickness below 5nm because of quantum
Fig.5 Threshold voltage dependence with the film thickness confinement. This sensitivity can be estimated for a
in the case of a long low-doped double gate transistor. long channel device from (4). Assuming a 0.5nm
Dots: Quantum mechanical numerical simulations. Plain dispersion on the film thickness (EOT=1nm), a
line: Equation (4). Dashed line: Classical part of (4). tolerable long channel threshold voltage variation of
50mV gives a low-limit for tSi of 3nm.
Since the logarithm term in (4) is typically In addition to the gain linked to the use of low-
between 0.46 and 0.5V for an equivalent oxide doped channels, the mobility at a given inversion
thickness (EOT) of 1nm and a silicon film thickness charge is increased on fully-depleted devices with
in the 5-15nm range, one can estimate the required respect to bulk, since fully-depleted transistors
gate workfunctions for the sub-32nm nodes (table 1). operate at lower transverse electric field. Indeed, the
transverse effective field is given by:
Technology option NMOS PMOS K.Qinv Qdep
High performance 4.4-4.5 eV 4.7-4.8 eV E eff (6)
HSi
Low operating power 4.5-4.6 eV 4.6-4.7 eV
with K1/2 and 1/3 respectively for electrons and
Low standby power 4.7-4.8 eV 4.4-4.5 eV
holes
While the depletion component is as high as 0.5
Table.1 Gate workfunctions required for the different
MV/cm in a bulk device with a 1018cm-3 doping
technology options with fully-depleted devices.
level, it is negligible in the case of low doped fully-
depleted transistor. The effective field range in strong
It should be noticed from equation (4) that the
inversion regime is then reduced from 0.6-1.5
threshold voltage is independent from the channel
MV/cm for bulk device to 0.1-1.0 MV/cm for fully-
doping level. This is true as long as the depletion
depleted.
charge plays insignificantly on electrostatics in the
Moreover, these devices will benefit from the
channel. This condition corresponds to:
advantages of the Silicon-On-Insulator (SOI)
k.T technologies: reduced junction capacitances (the only
q.N channel .t Si 2.Cox . (5)
q junction is the lateral source or drain to channel
junction), immunity to single event upsets and to
382 T. Poiroux et al. / Microelectronic Engineering 80 (2005) 378385
4.04
4. Multiple-gate devices versus single gate
3,5
3.5
One important issue for multiple gate devices is D=1.6
their dynamic performance with respect to single gate 3.03 D=1.4
D=1.2
transistors. Indeed, if the drive current is multiplied 2.5
2,5
D=1.0
by a factor of 2 in the case of double gate transistors,
2.02
the gate capacitance is also twice that of single gate. 2 2,5 3 3,5 4
2.0 2.5 3.0 3.5 4.0
Thus, the same intrinsic propagation delay
(Cgate.Vdd/Ion) is obtained, but for a doubled intrinsic Supply over threshold voltage ratio
power-delay product (Cgate.Vdd) if both devices are
designed with the same width. To have the same Fig.6 Required drive current ratio between a double gate
power-delay product at a given transistor width, and a single gate device to reach the same propagation
double gate devices have to operate at a supply delay power-delay compromise, as a function of the
voltage 2 times lower than that of single gate. To supply voltage.
reach the same Cgate.Vdd/Ion, the drive current should
be, at Vdd/2, 2 times the drive current obtained Anyway, thanks to their better electrostatics
with single gate device at Vdd (condition (7)). control, multiple gate transistors are likely to allow a
triple drive current with respect to single gate at a
DG
I on
Vdd 2 ! 2 (7)
given off-state current [20].
I SG Vdd To illustrate this, we have plotted on figure 7 the
on
ratio of the drive currents obtained experimentally on
From these considerations, if we write the drive 20nm co-integrated single gate and double gate
current as a power function of the gate overdrive, devices. The drive current of the double gate
dynamic performance will be better for double gate transistor is 1230A/m for an off-state current of
MOSFET if the following condition is fulfilled on 1A/m at Vdd=1.2V.
the drive current at a given supply voltage:
D
Measured drive current ratio DG/SG
DG
Ion Vdd Vdd VthDG 1
! 2 . (8)
4,5
4.5
on Vdd
ISG Vdd
2 .VthDG 1 4,0
4.0
Same film thickness (10nm)
Rsquare (Ohm/square)
5e14
respectively lower than 100mV/dec and 250mV/V).
The film thickness is reduced to 6nm for the single 4
1e20
4
10 10
gate transistor. The current ratio is still around 3, 1e15
because of the increased access resistances due to a 1e21
3 3
thinner film for the single gate device. 10 10
1
source and drain either based on Schottky barriers
[27] or modified Schottky barrier [28]. In both cases,
selective epitaxy can be suppressed as source and
0 drain are made out of metal. The key issue in this
10 15 20 25 30 option is to find metals for N and PMOS with
Interfacial
Oxyde oxide thickness
d'implantation () () adjusted work function to design either adequate
Schottky barrier or low ohmic contacts.
7. Conclusions
Silicon film Moat recess
b) We have discussed in this study the main
advantages and technological challenges associated
Buried oxide with the use of multiple gate devices. In particular,
we have studied the benefit they can bring over
single gate devices in dynamic operations. However,
Fig.11 a) SEM cross-section- After H2 anneal, silicon the choice of one of these multiple gate architectures
agglomeration is observed for thin films. b) Pre-anneal
is still a matter of discussion, and the circuit design
temperature lowering leads to less dramatic consequences
as in this case, only moat recess is observed. opportunities brought by separated gate devices
should be carefully considered.
T. Poiroux et al. / Microelectronic Engineering 80 (2005) 378385 385
Acknowledgements [18] H.S.P. Wong, D.J. Frank, P.M. Solomon, C.H.J. Wann
and J.J. Welser, Nanoscale CMOS, in Proc. of the
This study has been partly funded by the IEEE 87 (1999), 537-570.
NESTOR European Project (IST-2001-37114) and [19] A. Asenov, G. Slavcheva, A.R. Brown, J.H. Davies
by the Advanced Devices Program of the Alliance and S. Saini, Increase in the Random Dopant Induced
(STMicroelectronics, Philips and Freescale Threshold Fluctuations and Lowering in Sub-100nm
MOSFETs Due to Quantum Effects: A 3-D Density-
Semiconductors).
Gradient Simulation Study, in IEEE Trans. on Elec.
Dev. 48 (2001), 722-729.
References [20] J.G. Fossum, L. Ge and M.H. Chiang, Speed
[1] Int. Tech. Roadmap for Semiconductors, ed. 2003. Superiority of Scaled Double-Gate CMOS, in IEEE
[2] T. Sekigawa, in Solid State Elec. 27 (1984), 827-828. Trans. on Elec. Dev. 49 (2002), 808-811.
[3] D. Hisamoto, in Technical Digest of IEDM (1989), [21] H.S.P. Wong, D.J. Frank and P.M. Solomon, Device
833-836. Design Considerations for Double-Gate, Ground-
[4] F. Balestra et al., in IEEE Elec. Dev. Lett. 8 (1987), Plane, and Single-Gated Ultra-Thin SOI MOSFETs at
410-412. the 25nm Channel Length Generation, in Technical
[5] M. Vinet, T. Poiroux, J. Widiez, J. Lolivier, B. Digest of IEDM (1998), 407-410.
Previtali, C. Vizioz et al., Planar Double Gate CMOS [22] J. Lolivier, J. Widiez, M. Vinet, T. Poiroux, F. Daug,
Transistors with 40nm Metal Gate for Multipurpose B. Previtali, Experimental Comparison between
Applications, in Proc. of the Int. Conf. on Solid-State Double Gate, Ground Plane, and Single Gate SOI
Devices and Materials (2004), 768-769. CMOSFETs, in Proc. of ESSDERC (2004), 177.
[6] J.P. Colinge, M.H. Gao, A. Romano-Rodriguez, H. [23] T. Ernst et al., in IEEE Trans. on Elec. Dev. 50 (2003),
Maes and C. Claeys, Silicon-on-Insulator Gate-All- 830-838.
Around Device, in Technical Digest of IEDM (1990), [24] F. Gamiz et al, in Journal of Appl. Phys. 94 (2003),
595-598. 5732-5741.
[7] S. Harrison et al., Highly Performant Double Gate [25] K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie and Y.
MOSFET Realized with SON Process, in Technical Arimoto, Scaling Theory for Double-Gate SOI
Digest of IEDM (2003), #18-6. MOSFETs, in IEEE Trans. on Elec. Dev. 40 (1993),
[8] K.W. Guarini, P.M. Solomon, Y. Zhang, K.K. Chan, 2326-2329.
E.C. Jones, G.M. Cohen et al., Triple-Self-Aligned, [26] R. Nuryadi, Y. Ishikawa, M. Tabe and Y. Ono,
Planar Double-Gate MOSFETs: Devices and Circuits, Thermal agglomeration of single crystalline Si layer
in Technical Digest of IEDM (2001), 425-428. on buried SiO2 in ultrahigh vacuum, in Journal Vac.
[9] J.H. Lee, G. Taraschi, A. Wei, T.A. Langdo, E.A. Sci. Tech. B20(1) (2002), 167.
Fitzgerald and D.A. Antoniadis, Super Self-Aligned [27] E. Dubois and G. Larrieu, Low Schottky barrier
Double-Gate (SSDG) MOSFETs Utilizing Oxidation source/drain for advanced MOS architecture: device
Rate Difference and Selective Epitaxy, in Technical design and material considerations, in Solid State Elec.
Digest of IEDM (1999), 71-74. (2002), 997.
[10] X. Huang, W.C. Lee, C. Kuo, D. Hisamoto, L. Chang, [28] B.Y. Tsui and C.P. Lin, A novel 25nm modified
J. Kedzierski et al., Sub 50-nm FinFET: PFET, in Schottky barrier Finfet with high performance, in
Technical Digest of IEDM (1999), 67-70. IEEE Elec. Dev. Lett. (2004), 430-433.
[11] B. Doyle, B. Boyanov, S. Datta, M. Doczy, S. [29] I.Y. Yang, C. Vieri, A. Chandrakasan and D.A.
Hareland, B. Jin et al., Tri-Gate Fully-Depleted CMOS Antoniadis, Back-Gated CMOS on SOIAS For
Transistors: Fabrication, Design and Layout, in Symp. Dynamic Threshold Voltage Control, in IEEE Trans.
on VLSI Tech. (2003), 133-134. on Elec. Dev. 44 (1997), 822-831.
[12] F.L. Yang et al., in Technical Digest of IEDM (2002), [30] E.J. Nowak, I. Aller, T. Ludwig, K. Kim, R.V. Joshi,
255-258. C.T. Chuang et al., Turning Silicon on Its Edge, in
[13] J.T. Park, J.P. Colinge, C. Diaz, in IEEE Electron IEEE Circuits and Devices Mag. Jan/Feb (2004), 20-
Device Letters 22 (2001), 405-406. 31.
[14] F.L. Yang et al., in Symp. on VLSI Tech. (2004), 196. [31] M.H. Chiang, K. Kim, C. Tretz and C.T. Chuang,
[15] Y.K. Choi, T.J. King, C. Hu, Spacer FinFET: Novel High-Density Low-Power High-Performance
Nanoscale Double-Gate CMOS Technology for the Double-Gate Logic Technique, in Proc. of Int. SOI
Terabit Era, in Solid State Elec. 46 (2002), 1595-1601. Conference (2004), 122-123.
[16] J.P. Colinge, Multiple-gate SOI MOSFETs, in Solid [32] L. Mathew, Y. Du, A.V.Y. Thean, M. Sadd, A.
State Elec. 48 (2004), 897-905. Vandooren, C. Parker et al., CMOS Vertical Multiple
[17] Y. Tsividis, Operation and Modeling of the MOS Independent Gate Field Effect Transistor (MIGFET),
Transistor, ed. McGraw-Hill. in Proc. of Int. SOI Conference (2004), 187-188.